19#ifndef _RTEMS_SCORE_CPU_H
20#define _RTEMS_SCORE_CPU_H
42#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
44#define CPU_HARDWARE_FP FALSE
46#define CPU_SOFTWARE_FP FALSE
48#define CPU_ALL_TASKS_ARE_FP FALSE
50#define CPU_IDLE_TASK_IS_FP FALSE
52#define CPU_USE_DEFERRED_FP_SWITCH FALSE
54#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
67#define CPU_STACK_GROWS_UP FALSE
70#define CPU_CACHE_LINE_BYTES 32
72#define CPU_STRUCTURE_ALIGNMENT
84#define CPU_MODES_INTERRUPT_MASK 0x00000001
86#define CPU_MAXIMUM_PROCESSORS 32
164#define _CPU_Context_Get_SP( _context ) \
165 (_context)->r3_stack_pointer
177 uint32_t special_interrupt_register;
199#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
205#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
218#define CPU_STACK_MINIMUM_SIZE (1024*4)
220#define CPU_SIZEOF_POINTER 4
230#define CPU_ALIGNMENT 8
255#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
271#define CPU_STACK_ALIGNMENT 4
273#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
294#define _CPU_ISR_Disable( _isr_cookie ) \
298 v850_get_psw( _psw ); \
299 __asm__ __volatile__( "di" ); \
300 _isr_cookie = _psw; \
314#define _CPU_ISR_Enable( _isr_cookie ) \
316 unsigned int _psw = (_isr_cookie); \
318 v850_set_psw( _psw ); \
333#define _CPU_ISR_Flash( _isr_cookie ) \
335 unsigned int _psw = (_isr_cookie); \
336 v850_set_psw( _psw ); \
337 __asm__ __volatile__( "di" ); \
342 return ( level & V850_PSW_INTERRUPT_DISABLE_MASK )
343 != V850_PSW_INTERRUPT_DISABLE;
361#define _CPU_ISR_Set_level( new_level ) \
364 __asm__ __volatile__( "di" ); \
366 __asm__ __volatile__( "ei" ); \
421 uint32_t *stack_base,
444#define _CPU_Context_Restart_self( _the_context ) \
445 _CPU_Context_restore( (_the_context) );
467#define _CPU_Context_Initialize_fp( _destination ) \
485#define _CPU_Fatal_halt( _source, _error ) \
487 __asm__ __volatile__ ( "di" ); \
488 __asm__ __volatile__ ( "mov %0, r10; " : "=r" ((_error)) ); \
489 __asm__ __volatile__ ( "halt" ); \
494#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
631static inline uint32_t CPU_swap_u32(
635 unsigned int swapped;
637 #if (V850_HAS_BYTE_SWAP_INSTRUCTION == 1)
641 __asm__ __volatile__ (
"bsw %0, %1" :
"=r" (
v),
"=&r" (swapped) );
643 uint32_t byte1, byte2, byte3, byte4;
645 byte4 = (value >> 24) & 0xff;
646 byte3 = (value >> 16) & 0xff;
647 byte2 = (value >> 8) & 0xff;
648 byte1 = value & 0xff;
650 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
667 unsigned int swapped;
669 #if (V850_HAS_BYTE_SWAP_INSTRUCTION == 1)
673 __asm__ __volatile__ (
"bsh %0, %1" :
"=r" (
v),
"=&r" (swapped) );
675 swapped = ((value & 0xff) << 8) | ((value >> 8) & 0xff);
688static inline CPU_Counter_ticks _CPU_Counter_difference(
689 CPU_Counter_ticks second,
690 CPU_Counter_ticks first
693 return second - first;
#define RTEMS_NO_RETURN
Definition: basedefs.h:102
#define RTEMS_INLINE_ROUTINE
Definition: basedefs.h:66
bool _CPU_ISR_Is_enabled(uint32_t level)
Returns true if interrupts are enabled in the specified ISR level, otherwise returns false.
Definition: cpu.h:375
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:20
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uintptr_t CPU_Uint32ptr
Definition: cpu.h:662
uint32_t _CPU_Counter_frequency(void)
Returns the current CPU counter frequency in Hz.
Definition: system-clocks.c:112
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:91
CPU_Counter_ticks _CPU_Counter_read(void)
Returns the current CPU counter value.
Definition: system-clocks.c:117
void _CPU_Context_restore(Context_Control *new_context) RTEMS_NO_RETURN
Definition: cpu_asm.c:111
#define CPU_swap_u16(value)
Definition: cpu.h:642
uint32_t _CPU_ISR_Get_level(void)
Definition: cpu.c:88
void _CPU_Context_Initialize(Context_Control *context, void *stack_area_begin, size_t stack_area_size, uint32_t new_level, void(*entry_point)(void), bool is_fp, void *tls_area)
Initializes the CPU context.
Definition: epiphany-context-initialize.c:40
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:45
register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__("g6")
The pointer to the current per-CPU control is available via register g6.
uint32_t CPU_Counter_ticks
Unsigned integer type for CPU counter values.
Definition: cpu.h:1210
#define _CPU_Context_restore_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:904
#define _CPU_Context_save_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:898
The set of registers that specifies the complete processor state.
Definition: cpu.h:629
Interrupt stack frame (ISF).
Definition: cpu.h:191
SPARC basic context.
Definition: cpu.h:194
Thread register context.
Definition: cpu.h:194
uint32_t r3_stack_pointer
Definition: cpu.h:142
unsigned v
Definition: tte.h:0
unsigned size
Definition: tte.h:1
V850 Set up Basic CPU Dependency Settings Based on Compiler Settings.