cpu.h

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/*
 *  COPYRIGHT (c) 1989-2008.
 *  On-Line Applications Research Corporation (OAR).
 *
 *  The license and distribution terms for this file may be
 *  found in the file LICENSE in this distribution or at
 *  http://www.rtems.org/license/LICENSE.
 */
 
#ifndef _RTEMS_SCORE_CPU_H
#define _RTEMS_SCORE_CPU_H
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <rtems/score/basedefs.h>
#include <rtems/score/lm32.h>
 
/* conditional compilation parameters */
 
#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
 
#define CPU_ISR_PASSES_FRAME_POINTER TRUE
 
#define CPU_HARDWARE_FP FALSE
 
#define CPU_SOFTWARE_FP FALSE
 
#define CPU_ALL_TASKS_ARE_FP     FALSE
 
#define CPU_IDLE_TASK_IS_FP      FALSE
 
#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
 
#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
 
#define CPU_STACK_GROWS_UP               FALSE
 
/* L2 cache lines are 32 bytes in Milkymist SoC */
#define CPU_CACHE_LINE_BYTES 32
 
#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
 
#define CPU_MODES_INTERRUPT_MASK   0x00000001
 
#define CPU_MAXIMUM_PROCESSORS 32
 
/*
 *  Processor defined structures required for cpukit/score.
 *
 *  Port Specific Information:
 *
 *  XXX document implementation including references if appropriate
 */
 
/* may need to put some structures here.  */
 
typedef struct {
  uint32_t r11;
  uint32_t r12;
  uint32_t r13;
  uint32_t r14;
  uint32_t r15;
  uint32_t r16;
  uint32_t r17;
  uint32_t r18;
  uint32_t r19;
  uint32_t r20;
  uint32_t r21;
  uint32_t r22;
  uint32_t r23;
  uint32_t r24;
  uint32_t r25;
  uint32_t gp;
  uint32_t fp;
  uint32_t sp;
  uint32_t ra;
  uint32_t ie;
  uint32_t epc;
} Context_Control;
 
#define _CPU_Context_Get_SP( _context ) \
  (_context)->sp
 
typedef struct {
  uint32_t r1;
  uint32_t r2;
  uint32_t r3;
  uint32_t r4;
  uint32_t r5;
  uint32_t r6;
  uint32_t r7;
  uint32_t r8;
  uint32_t r9;
  uint32_t r10;
  uint32_t ra;
  uint32_t ba;
  uint32_t ea;
} CPU_Interrupt_frame;
 
#if 0
extern Context_Control_fp _CPU_Null_fp_context;
#endif
 
/*
 * Nothing prevents the porter from declaring more CPU specific variables.
 *
 * Port Specific Information:
 *
 * XXX document implementation including references if appropriate
 */
 
/* XXX: if needed, put more variables here */
 
#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
 
#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
 
#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
 
#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
 
 
#define CPU_STACK_MINIMUM_SIZE          (1024*4)
 
#define CPU_SIZEOF_POINTER 4
 
#define CPU_ALIGNMENT              4
 
#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
 
#define CPU_STACK_ALIGNMENT        CPU_ALIGNMENT
 
#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
 
/*
 *  ISR handler macros
 */
 
#define _CPU_Initialize_vectors()
 
#define _CPU_ISR_Disable( _isr_cookie ) \
  lm32_disable_interrupts( _isr_cookie );
 
#define _CPU_ISR_Enable( _isr_cookie ) \
  lm32_enable_interrupts( _isr_cookie );
 
#define _CPU_ISR_Flash( _isr_cookie ) \
  lm32_flash_interrupts( _isr_cookie );
 
RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
{
  return ( level & 0x0001 ) != 0;
}
 
#define _CPU_ISR_Set_level( new_level ) \
  { \
    _CPU_ISR_Enable( ( new_level==0 ) ? 1 : 0 ); \
  }
 
uint32_t   _CPU_ISR_Get_level( void );
 
/* end of ISR handler macros */
 
/* Context handler macros */
 
extern char _gp[];
 
#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
                                 _isr, _entry_point, _is_fp, _tls_area ) \
   do { \
     uint32_t _stack = (uint32_t)(_stack_base) + (_size) - 4; \
     \
     (void) _is_fp; /* avoid warning for being unused */ \
     (void) _isr;  /* avoid warning for being unused */ \
     (_the_context)->gp = (uint32_t)_gp; \
     (_the_context)->fp = (uint32_t)_stack; \
     (_the_context)->sp = (uint32_t)_stack; \
     (_the_context)->ra = (uint32_t)(_entry_point); \
   } while ( 0 )
 
#define _CPU_Context_Restart_self( _the_context ) \
   _CPU_Context_restore( (_the_context) );
 
#define _CPU_Context_Initialize_fp( _destination )
#if 0
  { \
   *(*(_destination)) = _CPU_Null_fp_context; \
  }
#endif
 
/* end of Context handler macros */
 
/* Fatal Error manager macros */
 
#define _CPU_Fatal_halt( _source, _error ) \
  { \
  }
 
/* end of Fatal Error manager macros */
 
#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
 
/* functions */
 
void _CPU_Initialize(void);
 
typedef void ( *CPU_ISR_raw_handler )( void );
 
RTEMS_INLINE_ROUTINE void _CPU_ISR_install_raw_handler(
  uint32_t             vector,
  CPU_ISR_raw_handler  new_handler,
  CPU_ISR_raw_handler *old_handler
)
{
  /* TODO */
}
 
typedef void ( *CPU_ISR_handler )( uint32_t );
 
void _CPU_ISR_install_vector(
  uint32_t         vector,
  CPU_ISR_handler  new_handler,
  CPU_ISR_handler *old_handler
);
 
void *_CPU_Thread_Idle_body( uintptr_t ignored );
 
void _CPU_Context_switch(
  Context_Control  *run,
  Context_Control  *heir
);
 
void _CPU_Context_restore(
  Context_Control *new_context
) RTEMS_NO_RETURN;
 
/* FIXME */
typedef CPU_Interrupt_frame CPU_Exception_frame;
 
void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
 
static inline uint32_t CPU_swap_u32(
  uint32_t value
)
{
  uint32_t byte1, byte2, byte3, byte4, swapped;
 
  byte4 = (value >> 24) & 0xff;
  byte3 = (value >> 16) & 0xff;
  byte2 = (value >> 8)  & 0xff;
  byte1 =  value        & 0xff;
 
  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
  return swapped;
}
 
static inline uint16_t CPU_swap_u16(uint16_t v)
{
    return v << 8 | v >> 8;
}
 
typedef uint32_t CPU_Counter_ticks;
 
uint32_t _CPU_Counter_frequency( void );
 
CPU_Counter_ticks _CPU_Counter_read( void );
 
static inline CPU_Counter_ticks _CPU_Counter_difference(
  CPU_Counter_ticks second,
  CPU_Counter_ticks first
)
{
  return second - first;
}
 
typedef uintptr_t CPU_Uint32ptr;
 
#ifdef __cplusplus
}
#endif
 
#endif