51 #define CPU_ISR_PASSES_FRAME_POINTER TRUE 53 #define CPU_HARDWARE_FP FALSE 55 #define CPU_SOFTWARE_FP FALSE 57 #define CPU_ALL_TASKS_ARE_FP FALSE 59 #define CPU_IDLE_TASK_IS_FP FALSE 61 #define CPU_USE_DEFERRED_FP_SWITCH TRUE 63 #define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE 74 #define CPU_STACK_GROWS_UP FALSE 77 #define CPU_CACHE_LINE_BYTES 32 79 #define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) 88 #define CPU_MODES_INTERRUPT_MASK 0x00000001 132 #ifdef OR1K_64BIT_ARCH 133 #define or1kreg uint64_t 135 #define or1kreg uint32_t 177 #define _CPU_Context_Get_SP( _context ) \ 189 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 197 #define CPU_STACK_MINIMUM_SIZE 4096 205 #define CPU_ALIGNMENT 8 211 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE 220 #define CPU_SIZEOF_POINTER 4 243 #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT 255 #define CPU_STACK_ALIGNMENT 0 257 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES 269 #define _CPU_Initialize_vectors() 277 static inline uint32_t or1k_interrupt_disable(
void )
280 sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
282 _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_IEE));
287 static inline void or1k_interrupt_enable(uint32_t level)
292 sr = level | CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE;
293 _OR1K_mtspr(CPU_OR1K_SPR_SR, sr);
297 #define _CPU_ISR_Disable( _level ) \ 298 _level = or1k_interrupt_disable() 308 #define _CPU_ISR_Enable( _level ) \ 309 or1k_interrupt_enable( _level ) 319 #define _CPU_ISR_Flash( _level ) \ 321 _CPU_ISR_Enable( _level ); \ 322 _OR1K_mtspr(CPU_OR1K_SPR_SR, (_level & ~CPU_OR1K_SPR_SR_IEE)); \ 327 return ( level & CPU_OR1K_SPR_SR ) != 0;
352 #define OR1K_FAST_CONTEXT_SWITCH_ENABLED FALSE 394 void *stack_area_begin,
395 size_t stack_area_size,
397 void (*entry_point)(
void ),
413 #define _CPU_Context_Restart_self( _the_context ) \ 414 _CPU_Context_restore( (_the_context) ); 429 #define _CPU_Fatal_halt(_source, _error ) \ 430 printk("Fatal Error %d.%" PRId32 " Halted\n",_source, _error); \ 431 _OR1KSIM_CPU_Halt(); \ 436 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE 440 #define CPU_SIZEOF_POINTER 4 442 #define CPU_MAXIMUM_PROCESSORS 32 452 #if !OR1K_FAST_CONTEXT_SWITCH_ENABLED 487 CPU_ISR_raw_handler new_handler,
488 CPU_ISR_raw_handler *old_handler
491 typedef void ( *CPU_ISR_handler )( uint32_t );
495 CPU_ISR_handler new_handler,
496 CPU_ISR_handler *old_handler
501 (CPU_ISR_raw_handler) new_handler,
502 (CPU_ISR_raw_handler *) old_handler
546 void **fp_context_ptr
557 void **fp_context_ptr
581 static inline unsigned int CPU_swap_u32(
585 uint32_t byte1, byte2, byte3, byte4, swapped;
587 byte4 = (value >> 24) & 0xff;
588 byte3 = (value >> 16) & 0xff;
589 byte2 = (value >> 8) & 0xff;
590 byte1 = value & 0xff;
592 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
596 #define CPU_swap_u16( value ) \ 597 (((value&0xff) << 8) | ((value >> 8)&0xff)) 605 static inline CPU_Counter_ticks _CPU_Counter_difference(
606 CPU_Counter_ticks second,
607 CPU_Counter_ticks first
610 return second - first;
#define _CPU_Context_restore_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:904
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:45
void _CPU_ISR_Set_level(uint32_t level)
Sets the hardware interrupt level by the level value.
Definition: cpu.c:57
CPU_Counter_ticks _CPU_Counter_read(void)
Returns the current CPU counter value.
Definition: system-clocks.c:117
Thread register context.
Definition: cpu.h:194
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:20
Interrupt stack frame (ISF).
Definition: cpu.h:191
#define RTEMS_NO_RETURN
Definition: basedefs.h:102
void _CPU_Context_Initialize(Context_Control *context, void *stack_area_begin, size_t stack_area_size, uint32_t new_level, void(*entry_point)(void), bool is_fp, void *tls_area)
Initializes the CPU context.
Definition: epiphany-context-initialize.c:40
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:91
#define _CPU_Context_save_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:898
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
Provide printf() PRIxxx Constante Beyond Standards.
uint32_t CPU_Counter_ticks
Unsigned integer type for CPU counter values.
Definition: cpu.h:1210
Interface to Kernel Print Methods.
uint32_t _CPU_ISR_Get_level(void)
Definition: cpu.c:88
unsigned context
Definition: tlb.h:108
RTEMS_INLINE_ROUTINE void _CPU_ISR_install_raw_handler(uint32_t vector, CPU_ISR_raw_handler new_handler, CPU_ISR_raw_handler *old_handler)
SPARC specific raw ISR installer.
Definition: cpu.h:649
bool _CPU_ISR_Is_enabled(uint32_t level)
Returns true if interrupts are enabled in the specified ISR level, otherwise returns false.
Definition: cpu.h:375
void _CPU_Context_restore(Context_Control *new_context) RTEMS_NO_RETURN
Definition: cpu_asm.c:111
uintptr_t CPU_Uint32ptr
Definition: cpu.h:662
uint32_t _CPU_Counter_frequency(void)
Returns the current CPU counter frequency in Hz.
Definition: system-clocks.c:112
RTEMS_INLINE_ROUTINE void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler new_handler, CPU_ISR_handler *old_handler)
SPARC specific RTEMS ISR installer.
Definition: cpu.h:493
The set of registers that specifies the complete processor state.
Definition: cpu.h:629
#define RTEMS_INLINE_ROUTINE
Definition: basedefs.h:66