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    RTEMS
    5.1
    
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Go to the source code of this file.
Macros | |
| #define | BSP_ASM_IRQ_VECTOR_BASE 0x20 | 
| #define | PIC_MASTER_COMMAND_IO_PORT 0x20 | 
| PIC's command and mask registers.  More... | |
| #define | PIC_SLAVE_COMMAND_IO_PORT 0xa0 | 
| Slave PIC command register.  | |
| #define | PIC_MASTER_IMR_IO_PORT 0x21 | 
| Master PIC Interrupt Mask Register.  | |
| #define | PIC_SLAVE_IMR_IO_PORT 0xa1 | 
| Slave PIC Interrupt Mask Register.  | |
| #define | PIC_EOSI 0x60 | 
| Command for specific EOI (End Of Interrupt): Interrupt acknowledge.  More... | |
| #define | PIC_EOI 0x20 | 
| Generic End of Interrupt (EOI)  | |
| #define | PIC_OCW3_RIS 0x01 /* 1 = read IS, 0 = read IR */ | 
| #define | PIC_OCW3_RR 0x02 /* register read */ | 
| #define | PIC_OCW3_P 0x04 /* poll mode command */ | 
| #define | PIC_OCW3_SEL 0x08 /* must be 1 */ | 
| #define | PIC_OCW3_SMM 0x20 /* special mode mask */ | 
| #define | PIC_OCW3_ESMM 0x40 /* enable SMM */ | 
| #define PIC_EOSI 0x60 | 
Command for specific EOI (End Of Interrupt): Interrupt acknowledge.
End of Specific Interrupt (EOSI)
| #define PIC_MASTER_COMMAND_IO_PORT 0x20 | 
PIC's command and mask registers.
Master PIC command register
 1.8.15