RTEMS CPU Kit with SuperCore  4.11.3
qsm.h
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1 
20 /*
21  * This file was created by John S. Gwynne to support Motorola's 68332 MCU.
22  *
23  * Redistribution and use in source and binary forms are permitted
24  * provided that the following conditions are met:
25  * 1. Redistribution of source code and documentation must retain
26  * the above authorship, this list of conditions and the
27  * following disclaimer.
28  * 2. The name of the author may not be used to endorse or promote
29  * products derived from this software without specific prior
30  * written permission.
31  *
32  * This software is provided "AS IS" without warranty of any kind,
33  * either expressed or implied, including, but not limited to, the
34  * implied warranties of merchantability, title and fitness for a
35  * particular purpose.
36  *
37  *------------------------------------------------------------------
38  */
39 
40 #ifndef _RTEMS_M68K_QSM_H
41 #define _RTEMS_M68K_QSM_H
42 
43 /* SAM-- shift and mask */
44 #undef SAM
45 #define SAM(a,b,c) ((a << b) & c)
46 
47 
48 /* QSM_CRB (QSM Control Register Block) base address of the QSM
49  control registers */
50 #if SIM_MM == 0
51 #define QSM_CRB 0x7ffc00
52 #else
53 #undef SIM_MM
54 #define SIM_MM 1
55 #define QSM_CRB 0xfffc00
56 #endif
57 
58 
59 #define QSMCR (volatile unsigned short int * const)(0x00 + QSM_CRB)
60  /* QSM Configuration Register */
61 #define STOP 0x8000 /* Stop Enable */
62 #define FRZ 0x6000 /* Freeze Control */
63 #define SUPV 0x0080 /* Supervisor/Unrestricted */
64 #define IARB 0x000f /* Inerrupt Arbitration */
65 
66 
67 #define QTEST (volatile unsigned short int * const)(0x02 + QSM_CRB)
68  /* QSM Test Register */
69 /* Used only for factor testing */
70 
71 
72 #define QILR (volatile unsigned char * const)(0x04 + QSM_CRB)
73  /* QSM Interrupt Level Register */
74 #define ILQSPI 0x38 /* Interrupt Level for QSPI */
75 #define ILSCI 0x07 /* Interrupt Level for SCI */
76 
77 
78 #define QIVR (volatile unsigned char * const)(0x05 + QSM_CRB)
79  /* QSM Interrupt Vector Register */
80 #define INTV 0xff /* Interrupt Vector Number */
81 
82 
83 #define SCCR0 (volatile unsigned short int * const)(0x08 + QSM_CRB)
84  /* SCI Control Register 0 */
85 #define SCBR 0x1fff /* SCI Baud Rate */
86 
87 
88 #define SCCR1 (volatile unsigned short int * const)(0x0a + QSM_CRB)
89  /* SCI Control Register 1 */
90 #define LOOPS 0x4000 /* Loop Mode */
91 #define WOMS 0x2000 /* Wired-OR Mode for SCI Pins */
92 #define ILT 0x1000 /* Idle-Line Detect Type */
93 #define PT 0x0800 /* Parity Type */
94 #define PE 0x0400 /* Parity Enable */
95 #define M 0x0200 /* Mode Select */
96 #define WAKE 0x0100 /* Wakeup by Address Mark */
97 #define TIE 0x0080 /* Transmit Complete Interrupt Enable */
98 #define TCIE 0x0040 /* Transmit Complete Interrupt Enable */
99 #define RIE 0x0020 /* Receiver Interrupt Enable */
100 #define ILIE 0x0010 /* Idle-Line Interrupt Enable */
101 #define TE 0x0008 /* Transmitter Enable */
102 #define RE 0x0004 /* Receiver Enable */
103 #define RWU 0x0002 /* Receiver Wakeup */
104 #define SBK 0x0001 /* Send Break */
105 
106 
107 #define SCSR (volatile unsigned short int * const)(0x0c + QSM_CRB)
108  /* SCI Status Register */
109 #define TDRE 0x0100 /* Transmit Data Register Empty */
110 #define TC 0x0080 /* Transmit Complete */
111 #define RDRF 0x0040 /* Receive Data Register Full */
112 #define RAF 0x0020 /* Receiver Active */
113 #define IDLE 0x0010 /* Idle-Line Detected */
114 #define OR 0x0008 /* Overrun Error */
115 #define NF 0x0004 /* Noise Error Flag */
116 #define FE 0x0002 /* Framing Error */
117 #define PF 0x0001 /* Parity Error */
118 
119 
120 #define SCDR (volatile unsigned short int * const)(0x0e + QSM_CRB)
121  /* SCI Data Register */
122 
123 
124 #define PORTQS (volatile unsigned char * const)(0x15 + QSM_CRB)
125  /* Port QS Data Register */
126 
127 #define PQSPAR (volatile unsigned char * const)(0x16 + QSM_CRB)
128  /* PORT QS Pin Assignment Rgister */
129 /* Any bit cleared (zero) defines the corresponding pin to be an I/O
130  pin. Any bit set defines the corresponding pin to be a QSPI
131  signal. */
132 /* note: PQS2 is a digital I/O pin unless the SPI is enabled in which
133  case it becomes the SPI serial clock SCK. */
134 /* note: PQS7 is a digital I/O pin unless the SCI transmitter is
135  enabled in which case it becomes the SCI serial output TxD. */
136 #define QSMFun 0x0
137 #define QSMDis 0x1
138 /*
139  * PQSPAR Field | QSM Function | Discrete I/O pin
140  *------------------+--------------+------------------ */
141 #define PQSPA0 0 /* MISO | PQS0 */
142 #define PQSPA1 1 /* MOSI | PQS1 */
143 #define PQSPA2 2 /* SCK | PQS2 (see note)*/
144 #define PQSPA3 3 /* PCSO/!SS | PQS3 */
145 #define PQSPA4 4 /* PCS1 | PQS4 */
146 #define PQSPA5 5 /* PCS2 | PQS5 */
147 #define PQSPA6 6 /* PCS3 | PQS6 */
148 #define PQSPA7 7 /* TxD | PQS7 (see note)*/
149 
150 
151 #define DDRQS (volatile unsigned char * const)(0x17 + QSM_CRB)
152  /* PORT QS Data Direction Register */
153 /* Clearing a bit makes the corresponding pin an input; setting a bit
154  makes the pin an output. */
155 
156 
157 #define SPCR0 (volatile unsigned short int * const)(0x18 + QSM_CRB)
158  /* QSPI Control Register 0 */
159 #define MSTR 0x8000 /* Master/Slave Mode Select */
160 #define WOMQ 0x4000 /* Wired-OR Mode for QSPI Pins */
161 #define BITS 0x3c00 /* Bits Per Transfer */
162 #define CPOL 0x0200 /* Clock Polarity */
163 #define CPHA 0x0100 /* Clock Phase */
164 #define SPBR 0x00ff /* Serial Clock Baud Rate */
165 
166 
167 #define SPCR1 (volatile unsigned short int * const)(0x1a + QSM_CRB)
168  /* QSPI Control Register 1 */
169 #define SPE 0x8000 /* QSPI Enable */
170 #define DSCKL 0x7f00 /* Delay before SCK */
171 #define DTL 0x00ff /* Length of Delay after Transfer */
172 
173 
174 #define SPCR2 (volatile unsigned short int * const)(0x1c + QSM_CRB)
175  /* QSPI Control Register 2 */
176 #define SPIFIE 0x8000 /* SPI Finished Interrupt Enable */
177 #define WREN 0x4000 /* Wrap Enable */
178 #define WRTO 0x2000 /* Wrap To */
179 #define ENDQP 0x0f00 /* Ending Queue Pointer */
180 #define NEWQP 0x000f /* New Queue Pointer Value */
181 
182 
183 #define SPCR3 (volatile unsigned char * const)(0x1e + QSM_CRB)
184  /* QSPI Control Register 3 */
185 #define LOOPQ 0x0400 /* QSPI Loop Mode */
186 #define HMIE 0x0200 /* HALTA and MODF Interrupt Enable */
187 #define HALT 0x0100 /* Halt */
188 
189 
190 #define SPSR (volatile unsigned char * const)(0x1f + QSM_CRB)
191  /* QSPI Status Register */
192 #define SPIF 0x0080 /* QSPI Finished Flag */
193 #define MODF 0x0040 /* Mode Fault Flag */
194 #define HALTA 0x0020 /* Halt Acknowlwdge Flag */
195 #define CPTQP x0000f /* Completed Queue Pointer */
196 
197 #define QSPIRR (volatile unsigned char * const)(0x100 + QSM_CRB)
198  /* QSPI Receive Data RAM */
199 #define QSPITR (volatile unsigned char * const)(0x120 + QSM_CRB)
200  /* QSPI Transmit Data RAM */
201 #define QSPIcR (volatile unsigned char * const)(0x140 + QSM_CRB)
202  /* QSPI Command RAM */
203 
204 #endif /* _RTEMS_M68K_QSM_H */
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