RTEMS CPU Kit with SuperCore  4.11.3
iocan32.h
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1 
9 /*
10  * Copyright (c) 2004,2005, Anatoly Sokolov <aesok@pautinka.net>
11  * All rights reserved.
12  *
13  * Redistribution and use in source and binary forms, with or without
14  * modification, are permitted provided that the following conditions are met:
15  *
16  * * Redistributions of source code must retain the above copyright
17  * notice, this list of conditions and the following disclaimer.
18  *
19  * * Redistributions in binary form must reproduce the above copyright
20  * notice, this list of conditions and the following disclaimer in
21  * the documentation and/or other materials provided with the
22  * distribution.
23  *
24  * * Neither the name of the copyright holders nor the names of
25  * contributors may be used to endorse or promote products derived
26  * from this software without specific prior written permission.
27  *
28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
32  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38  * POSSIBILITY OF SUCH DAMAGE.
39  */
40 
41 #ifndef _AVR_IOCAN32_H_
42 #define _AVR_IOCAN32_H_ 1
43 
52 #include <avr/iocanxx.h>
53 
54 /* Constants */
55 #define SPM_PAGESIZE 256
56 #define RAMEND 0x08FF /* Last On-Chip SRAM Location */
57 #define XRAMEND 0xFFFF
58 #define E2END 0x03FF
59 #define E2PAGESIZE 8
60 #define FLASHEND 0x7FFF
61 
62 
63 /* Fuses */
64 
65 #define FUSE_MEMORY_SIZE 3
66 
67 /* Low Fuse Byte */
68 #define FUSE_CKSEL0 (unsigned char)~_BV(0)
69 #define FUSE_CKSEL1 (unsigned char)~_BV(1)
70 #define FUSE_CKSEL2 (unsigned char)~_BV(2)
71 #define FUSE_CKSEL3 (unsigned char)~_BV(3)
72 #define FUSE_SUT0 (unsigned char)~_BV(4)
73 #define FUSE_SUT1 (unsigned char)~_BV(5)
74 #define FUSE_CKOUT (unsigned char)~_BV(6)
75 #define FUSE_CKDIV8 (unsigned char)~_BV(7)
76 #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
77 
78 /* High Fuse Byte */
79 #define FUSE_BOOTRST (unsigned char)~_BV(0)
80 #define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
81 #define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
82 #define FUSE_EESAVE (unsigned char)~_BV(3)
83 #define FUSE_WDTON (unsigned char)~_BV(4)
84 #define FUSE_SPIEN (unsigned char)~_BV(5)
85 #define FUSE_JTAGEN (unsigned char)~_BV(6)
86 #define FUSE_OCDEN (unsigned char)~_BV(7)
87 #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
88 
89 /* Extended Fuse Byte */
90 #define FUSE_BODLEVEL0 (unsigned char)~_BV(1)
91 #define FUSE_BODLEVEL1 (unsigned char)~_BV(2)
92 #define FUSE_BODLEVEL2 (unsigned char)~_BV(3)
93 #define EFUSE_DEFAULT (0xFF)
94 
95 
96 /* Lock Bits */
97 #define __LOCK_BITS_EXIST
98 #define __BOOT_LOCK_BITS_0_EXIST
99 #define __BOOT_LOCK_BITS_1_EXIST
100 
101 
102 /* Signature */
103 #define SIGNATURE_0 0x1E
104 #define SIGNATURE_1 0x95
105 #define SIGNATURE_2 0x81
106 
107 
109 #endif /* _AVR_IOCAN32_H_ */
iocanxx.h
Definitions for AT90CAN32, AT90CAN64 and AT90CAN128.
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