RTEMS CPU Architecture Supplement
The Texas Instruments C3x/C4x processors include a Data Page
(dp) register that logically is a base address. The
dp register allows the use of shorter offsets in
instructions. Up to 64K words may be addressed using
offsets from the dp register. In order to address
words not addressable based on the current value of
dp, the register must be loaded with a different
value.
The dp register is managed automatically by
the high-level language compilers.
The various compilers for this processor family support
two memory models that manage the dp register
in very different manners. The large and small memory
models are discussed in the following sections.
NOTE: The C3x/C4x port of RTEMS has been written so that it should support either memory model. However, it has only been tested using the large memory model.
RTEMS CPU Architecture Supplement
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