MIPS Specific Information Models With Separate Interrupt Stacks
RTEMS CPU Architecture Supplement
5.4.1.2: Models With Separate Interrupt Stacks
Upon receipt of an interrupt the XXX family
members with separate interrupt stacks automatically perform the
following actions:
saves the current status register (SR),
clears the master/interrupt (M) bit of the SR to
indicate the switch from master state to interrupt state,
sets the privilege mode to supervisor,
suppresses tracing,
sets the interrupt mask level equal to the level of the
interrupt being serviced,
pushes an interrupt stack frame (ISF), which includes
the program counter (PC), the status register (SR), and the
format/exception vector offset (FVO) word, onto the supervisor
and interrupt stacks,
switches the current stack to the interrupt stack and
vectors to an interrupt service routine (ISR). If the ISR was
installed with the interrupt_catch directive, then the RTEMS
interrupt handler will begin execution. The RTEMS interrupt
handler saves all registers which are not preserved according to
the calling conventions and invokes the application's ISR.
A nested interrupt is processed similarly by these
CPU models with the exception that only a single ISF is placed
on the interrupt stack and the current stack need not be
switched.
The FVO word in the Interrupt Stack Frame is examined
by RTEMS to determine when an outer most interrupt is being
exited. Since the FVO is used by RTEMS for this purpose, the
user application code MUST NOT modify this field.
The following shows the Interrupt Stack Frame for
XXX CPU models with separate interrupt stacks:
RTEMS CPU Architecture Supplement