RTEMS  5.0.0
xdmac.h
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29 
67 #ifndef DMAC_H
68 #define DMAC_H
69 
71 /*------------------------------------------------------------------------------
72  * Headers
73  *----------------------------------------------------------------------------*/
74 
75 #include "chip.h"
76 
77 #ifndef __rtems__
78 #include <../../../../utils/utility.h>
79 #endif /* __rtems__ */
80 #include <stdint.h>
81 #include <rtems/score/assert.h>
82 
83 /*------------------------------------------------------------------------------
84  * Definitions
85  *----------------------------------------------------------------------------*/
86 
91 #define XDMAC_CONTROLLER_NUM 1
92 
93 #define XDMAC_CHANNEL_NUM 24
94 
95 #define XDMAC_MAX_BT_SIZE 0xFFFF
96 
98 /*----------------------------------------------------------------------------
99  * Macro
100  *----------------------------------------------------------------------------*/
101 #define XDMA_GET_DATASIZE(size) ((size==0)? XDMAC_CC_DWIDTH_BYTE : \
102  ((size==1)? XDMAC_CC_DWIDTH_HALFWORD : \
103  (XDMAC_CC_DWIDTH_WORD)))
104 #define XDMA_GET_CC_SAM(s) ((s==0)? XDMAC_CC_SAM_FIXED_AM : \
105  ((s==1)? XDMAC_CC_SAM_INCREMENTED_AM : \
106  ((s==2)? XDMAC_CC_SAM_UBS_AM : \
107  XDMAC_CC_SAM_UBS_DS_AM)))
108 #define XDMA_GET_CC_DAM(d) ((d==0)? XDMAC_CC_DAM_FIXED_AM : \
109  ((d==1)? XDMAC_CC_DAM_INCREMENTED_AM : \
110  ((d==2)? XDMAC_CC_DAM_UBS_AM : \
111  XDMAC_CC_DAM_UBS_DS_AM)))
112 #define XDMA_GET_CC_MEMSET(m) ((m==0)? XDMAC_CC_MEMSET_NORMAL_MODE : \
113  XDMAC_CC_MEMSET_HW_MODE)
114 
115 /*------------------------------------------------------------------------------
116  * Global functions
117  *----------------------------------------------------------------------------*/
122 #ifdef __cplusplus
123 extern "C" {
124 #endif
125 
131 static inline uint32_t XDMAC_GetType(Xdmac *pXdmac)
132 {
133  _Assert(pXdmac);
134  return pXdmac->XDMAC_GTYPE;
135 }
136 
142 static inline uint32_t XDMAC_GetConfig(Xdmac *pXdmac)
143 {
144  _Assert(pXdmac);
145  return pXdmac->XDMAC_GCFG;
146 }
147 
153 static inline uint32_t XDMAC_GetArbiter(Xdmac *pXdmac)
154 {
155  _Assert(pXdmac);
156  return pXdmac->XDMAC_GWAC;
157 }
158 
165 static inline void XDMAC_EnableGIt (Xdmac *pXdmac, uint8_t dwInteruptMask)
166 {
167  _Assert(pXdmac);
168  pXdmac->XDMAC_GIE = (XDMAC_GIE_IE0 << dwInteruptMask);
169 }
170 
177 static inline void XDMAC_DisableGIt (Xdmac *pXdmac, uint8_t dwInteruptMask)
178 {
179  _Assert(pXdmac);
180  pXdmac->XDMAC_GID = (XDMAC_GID_ID0 << dwInteruptMask);
181 }
182 
188 static inline uint32_t XDMAC_GetGItMask(Xdmac *pXdmac)
189 {
190  _Assert(pXdmac);
191  return (pXdmac->XDMAC_GIM);
192 }
193 
199 static inline uint32_t XDMAC_GetGIsr(Xdmac *pXdmac)
200 {
201  _Assert(pXdmac);
202  return (pXdmac->XDMAC_GIS);
203 }
204 
210 static inline uint32_t XDMAC_GetMaskedGIsr(Xdmac *pXdmac)
211 {
212  uint32_t _dwStatus;
213  _Assert(pXdmac);
214  _dwStatus = pXdmac->XDMAC_GIS;
215  _dwStatus &= pXdmac->XDMAC_GIM;
216  return _dwStatus;
217 }
218 
225 static inline void XDMAC_EnableChannel(Xdmac *pXdmac, uint8_t channel)
226 {
227  _Assert(pXdmac);
228  _Assert(channel < XDMAC_CHANNEL_NUM);
229  pXdmac->XDMAC_GE = (XDMAC_GE_EN0 << channel);
230 }
231 
238 static inline void XDMAC_EnableChannels(Xdmac *pXdmac, uint32_t bmChannels)
239 {
240  _Assert(pXdmac);
241  pXdmac->XDMAC_GE = bmChannels;
242 }
243 
250 static inline void XDMAC_DisableChannel(Xdmac *pXdmac, uint8_t channel)
251 {
252  _Assert(pXdmac);
253  _Assert(channel < XDMAC_CHANNEL_NUM);
254  pXdmac->XDMAC_GD = (XDMAC_GD_DI0 << channel);
255 }
256 
263 static inline void XDMAC_DisableChannels(Xdmac *pXdmac, uint32_t bmChannels)
264 {
265  _Assert(pXdmac);
266  pXdmac->XDMAC_GD = bmChannels;
267 }
268 
269 
277 static inline uint32_t XDMAC_GetGlobalChStatus(Xdmac *pXdmac)
278 {
279  _Assert(pXdmac);
280  return pXdmac->XDMAC_GS;
281 }
282 
289 static inline void XDMAC_SuspendReadChannel(Xdmac *pXdmac, uint8_t channel)
290 {
291  _Assert(pXdmac);
292  _Assert(channel < XDMAC_CHANNEL_NUM);
293  pXdmac->XDMAC_GRS |= XDMAC_GRS_RS0 << channel;
294 }
295 
302 static inline void XDMAC_SuspendWriteChannel(Xdmac *pXdmac, uint8_t channel)
303 {
304  _Assert(pXdmac);
305  _Assert(channel < XDMAC_CHANNEL_NUM);
306  pXdmac->XDMAC_GWS |= XDMAC_GWS_WS0 << channel;
307 }
308 
315 static inline void XDMAC_SuspendReadWriteChannel(Xdmac *pXdmac, uint8_t channel)
316 {
317  _Assert(pXdmac);
318  _Assert(channel < XDMAC_CHANNEL_NUM);
319  pXdmac->XDMAC_GRWS = (XDMAC_GRWS_RWS0 << channel);
320 }
321 
328 static inline void XDMAC_ResumeReadWriteChannel(Xdmac *pXdmac, uint8_t channel)
329 {
330  _Assert(pXdmac);
331  _Assert(channel < XDMAC_CHANNEL_NUM);
332  pXdmac->XDMAC_GRWR = (XDMAC_GRWR_RWR0 << channel);
333 }
334 
341 static inline void XDMAC_SoftwareTransferReq(Xdmac *pXdmac, uint8_t channel)
342 {
343 
344  _Assert(pXdmac);
345  _Assert(channel < XDMAC_CHANNEL_NUM);
346  pXdmac->XDMAC_GSWR = (XDMAC_GSWR_SWREQ0 << channel);
347 }
348 
354 static inline uint32_t XDMAC_GetSoftwareTransferStatus(Xdmac *pXdmac)
355 {
356 
357  _Assert(pXdmac);
358  return pXdmac->XDMAC_GSWS;
359 }
360 
367 static inline uint32_t XDMAC_GetChannelIsr (Xdmac *pXdmac, uint8_t channel)
368 {
369  _Assert(pXdmac);
370  _Assert(channel < XDMAC_CHANNEL_NUM);
371  return pXdmac->XDMAC_CHID[channel].XDMAC_CIS;
372 }
373 
381 static inline void XDMAC_SoftwareFlushReq(Xdmac *pXdmac, uint8_t channel)
382 {
383  _Assert(pXdmac);
384  _Assert(channel < XDMAC_CHANNEL_NUM);
385  pXdmac->XDMAC_GSWF = (XDMAC_GSWF_SWF0 << channel);
386 
387  while (!(XDMAC_GetChannelIsr(pXdmac, channel) & XDMAC_CIS_FIS));
388 }
389 
397 static inline void XDMAC_EnableChannelIt (Xdmac *pXdmac, uint8_t channel,
398  uint8_t dwInteruptMask)
399 {
400  _Assert(pXdmac);
401  _Assert(channel < XDMAC_CHANNEL_NUM);
402  pXdmac->XDMAC_CHID[channel].XDMAC_CIE = dwInteruptMask;
403 }
404 
412 static inline void XDMAC_DisableChannelIt (Xdmac *pXdmac, uint8_t channel,
413  uint8_t dwInteruptMask)
414 {
415  _Assert(pXdmac);
416  _Assert(channel < XDMAC_CHANNEL_NUM);
417  pXdmac->XDMAC_CHID[channel].XDMAC_CID = dwInteruptMask;
418 }
419 
426 static inline uint32_t XDMAC_GetChannelItMask (Xdmac *pXdmac, uint8_t channel)
427 {
428  _Assert(pXdmac);
429  _Assert(channel < XDMAC_CHANNEL_NUM);
430  return pXdmac->XDMAC_CHID[channel].XDMAC_CIM;
431 }
432 
439 static inline uint32_t XDMAC_GetMaskChannelIsr (Xdmac *pXdmac, uint8_t channel)
440 {
441  uint32_t status;
442  _Assert(pXdmac);
443  _Assert(channel < XDMAC_CHANNEL_NUM);
444  status = pXdmac->XDMAC_CHID[channel].XDMAC_CIS;
445  status &= pXdmac->XDMAC_CHID[channel].XDMAC_CIM;
446 
447  return status;
448 }
449 
457 static inline void XDMAC_SetSourceAddr(Xdmac *pXdmac, uint8_t channel, uint32_t addr)
458 {
459  _Assert(pXdmac);
460  _Assert(channel < XDMAC_CHANNEL_NUM);
461  pXdmac->XDMAC_CHID[channel].XDMAC_CSA = addr;
462 }
463 
471 static inline void XDMAC_SetDestinationAddr(Xdmac *pXdmac, uint8_t channel, uint32_t addr)
472 {
473  _Assert(pXdmac);
474  _Assert(channel < XDMAC_CHANNEL_NUM);
475  pXdmac->XDMAC_CHID[channel].XDMAC_CDA = addr;
476 }
477 
487 static inline void XDMAC_SetDescriptorAddr(Xdmac *pXdmac, uint8_t channel,
488  uint32_t addr, uint8_t ndaif)
489 {
490  _Assert(pXdmac);
491  _Assert(ndaif < 2);
492  _Assert(channel < XDMAC_CHANNEL_NUM);
493  pXdmac->XDMAC_CHID[channel].XDMAC_CNDA = (addr & 0xFFFFFFFC) | ndaif;
494 }
495 
504 static inline void XDMAC_SetDescriptorControl(Xdmac *pXdmac, uint8_t channel, uint8_t config)
505 {
506  _Assert(pXdmac);
507  _Assert(channel < XDMAC_CHANNEL_NUM);
508  pXdmac->XDMAC_CHID[channel].XDMAC_CNDC = config;
509 }
510 
518 static inline void XDMAC_SetMicroblockControl(Xdmac *pXdmac, uint8_t channel, uint32_t ublen)
519 {
520  _Assert(pXdmac);
521  _Assert(channel < XDMAC_CHANNEL_NUM);
522  pXdmac->XDMAC_CHID[channel].XDMAC_CUBC = XDMAC_CUBC_UBLEN(ublen);
523 }
524 
532 static inline void XDMAC_SetBlockControl(Xdmac *pXdmac, uint8_t channel, uint16_t blen)
533 {
534  _Assert(pXdmac);
535  _Assert(channel < XDMAC_CHANNEL_NUM);
536  pXdmac->XDMAC_CHID[channel].XDMAC_CBC = XDMAC_CBC_BLEN(blen);
537 }
538 
546 static inline void XDMAC_SetChannelConfig(Xdmac *pXdmac, uint8_t channel, uint32_t config)
547 {
548  _Assert(pXdmac);
549  _Assert(channel < XDMAC_CHANNEL_NUM);
550  pXdmac->XDMAC_CHID[channel].XDMAC_CC = config;
551 }
552 
559 static inline uint32_t XDMAC_GetChannelConfig(Xdmac *pXdmac, uint8_t channel)
560 {
561  _Assert(pXdmac);
562  _Assert(channel < XDMAC_CHANNEL_NUM);
563  return pXdmac->XDMAC_CHID[channel].XDMAC_CC;
564 }
565 
573 static inline void XDMAC_SetDataStride_MemPattern(Xdmac *pXdmac, uint8_t channel,
574  uint32_t dds_msp)
575 {
576 
577  _Assert(pXdmac);
578  _Assert(channel < XDMAC_CHANNEL_NUM);
579  pXdmac->XDMAC_CHID[channel].XDMAC_CDS_MSP = dds_msp;
580 }
581 
589 static inline void XDMAC_SetSourceMicroBlockStride(Xdmac *pXdmac, uint8_t channel,
590  uint32_t subs)
591 {
592  _Assert(pXdmac);
593  _Assert(channel < XDMAC_CHANNEL_NUM);
594  pXdmac->XDMAC_CHID[channel].XDMAC_CSUS = XDMAC_CSUS_SUBS(subs);
595 }
596 
604 static inline void XDMAC_SetDestinationMicroBlockStride(Xdmac *pXdmac, uint8_t channel,
605  uint32_t dubs)
606 {
607  _Assert(pXdmac);
608  _Assert(channel < XDMAC_CHANNEL_NUM);
609  pXdmac->XDMAC_CHID[channel].XDMAC_CDUS = XDMAC_CDUS_DUBS(dubs);
610 }
611 
618 static inline uint32_t XDMAC_GetChDestinationAddr(Xdmac *pXdmac, uint8_t channel)
619 {
620  _Assert(pXdmac);
621  _Assert(channel < XDMAC_CHANNEL_NUM);
622  return pXdmac->XDMAC_CHID[channel].XDMAC_CDA;
623 }
624 
625 static inline void XDMAC_StartTransfer(Xdmac *pXdmac, uint8_t channel)
626 {
627  _Assert(pXdmac);
628  _Assert(channel < XDMAC_CHANNEL_NUM);
629  pXdmac->XDMAC_GE = (XDMAC_GE_EN0 << channel);
630  pXdmac->XDMAC_GIE = (XDMAC_GIE_IE0 << channel);
631 }
632 
633 #ifdef __cplusplus
634 }
635 #endif
636 
639 #endif //#ifndef DMAC_H
640 
__O uint32_t XDMAC_CIE
(XdmacChid Offset: 0x0) Channel Interrupt Enable Register
Definition: component_xdmac.h:42
#define XDMAC_GSWR_SWREQ0
(XDMAC_GSWR) XDMAC Channel 0 Software Request Bit
Definition: component_xdmac.h:387
Definition: deflate.c:115
#define XDMAC_GWS_WS0
(XDMAC_GWS) XDMAC Channel 0 Write Suspend Bit
Definition: component_xdmac.h:312
__IO uint32_t XDMAC_CNDC
(XdmacChid Offset: 0x1C) Channel Next Descriptor Control Register
Definition: component_xdmac.h:49
__I uint32_t XDMAC_CIS
(XdmacChid Offset: 0xC) Channel Interrupt Status Register
Definition: component_xdmac.h:45
#define XDMAC_GID_ID0
(XDMAC_GID) XDMAC Channel 0 Interrupt Disable Bit
Definition: component_xdmac.h:137
__O uint32_t XDMAC_CID
(XdmacChid Offset: 0x4) Channel Interrupt Disable Register
Definition: component_xdmac.h:43
__IO uint32_t XDMAC_CDS_MSP
(XdmacChid Offset: 0x2C) Channel Data Stride Memory Set Pattern
Definition: component_xdmac.h:53
__O uint32_t XDMAC_GSWF
(Xdmac Offset: 0x40) Global Channel Software Flush Request Register
Definition: component_xdmac.h:77
#define XDMAC_GSWF_SWF0
(XDMAC_GSWF) XDMAC Channel 0 Software Flush Request Bit
Definition: component_xdmac.h:437
__IO uint32_t XDMAC_GWAC
(Xdmac Offset: 0x08) Global Weighted Arbiter Configuration Register
Definition: component_xdmac.h:63
__IO uint32_t XDMAC_GTYPE
(Xdmac Offset: 0x00) Global Type Register
Definition: component_xdmac.h:61
#define XDMAC_GRWR_RWR0
(XDMAC_GRWR) XDMAC Channel 0 Read Write Resume Bit
Definition: component_xdmac.h:362
XdmacChid XDMAC_CHID[XDMACCHID_NUMBER]
(Xdmac Offset: 0x50) chid = 0 .. 23
Definition: component_xdmac.h:79
__IO uint32_t XDMAC_GRS
(Xdmac Offset: 0x28) Global Channel Read Suspend Register
Definition: component_xdmac.h:71
#define XDMAC_GRWS_RWS0
(XDMAC_GRWS) XDMAC Channel 0 Read Write Suspend Bit
Definition: component_xdmac.h:337
#define XDMAC_GIE_IE0
(XDMAC_GIE) XDMAC Channel 0 Interrupt Enable Bit
Definition: component_xdmac.h:112
__O uint32_t XDMAC_GRWS
(Xdmac Offset: 0x30) Global Channel Read Write Suspend Register
Definition: component_xdmac.h:73
__O uint32_t XDMAC_GSWR
(Xdmac Offset: 0x38) Global Channel Software Request Register
Definition: component_xdmac.h:75
__I uint32_t XDMAC_GIM
(Xdmac Offset: 0x14) Global Interrupt Mask Register
Definition: component_xdmac.h:66
__O uint32_t XDMAC_GID
(Xdmac Offset: 0x10) Global Interrupt Disable Register
Definition: component_xdmac.h:65
#define XDMAC_CHANNEL_NUM
Definition: xdmac.h:93
__O uint32_t XDMAC_GD
(Xdmac Offset: 0x20) Global Channel Disable Register
Definition: component_xdmac.h:69
__IO uint32_t XDMAC_CUBC
(XdmacChid Offset: 0x20) Channel Microblock Control Register
Definition: component_xdmac.h:50
#define XDMAC_GD_DI0
(XDMAC_GD) XDMAC Channel 0 Disable Bit
Definition: component_xdmac.h:237
__I uint32_t XDMAC_GSWS
(Xdmac Offset: 0x3C) Global Channel Software Request Status Register
Definition: component_xdmac.h:76
__IO uint32_t XDMAC_CDA
(XdmacChid Offset: 0x14) Channel Destination Address Register
Definition: component_xdmac.h:47
__IO uint32_t XDMAC_CSA
(XdmacChid Offset: 0x10) Channel Source Address Register
Definition: component_xdmac.h:46
__IO uint32_t XDMAC_GWS
(Xdmac Offset: 0x2C) Global Channel Write Suspend Register
Definition: component_xdmac.h:72
#define XDMAC_GRS_RS0
(XDMAC_GRS) XDMAC Channel 0 Read Suspend Bit
Definition: component_xdmac.h:287
struct rtems_bsdnet_ifconfig * config
Network driver configuration.
__I uint32_t XDMAC_GS
(Xdmac Offset: 0x24) Global Channel Status Register
Definition: component_xdmac.h:70
__O uint32_t XDMAC_GE
(Xdmac Offset: 0x1C) Global Channel Enable Register
Definition: component_xdmac.h:68
__IO uint32_t XDMAC_CSUS
(XdmacChid Offset: 0x30) Channel Source Microblock Stride
Definition: component_xdmac.h:54
__O uint32_t XDMAC_GIE
(Xdmac Offset: 0x0C) Global Interrupt Enable Register
Definition: component_xdmac.h:64
Definition: component_xdmac.h:60
__IO uint32_t XDMAC_CC
(XdmacChid Offset: 0x28) Channel Configuration Register
Definition: component_xdmac.h:52
__IO uint32_t XDMAC_CBC
(XdmacChid Offset: 0x24) Channel Block Control Register
Definition: component_xdmac.h:51
__I uint32_t XDMAC_GIS
(Xdmac Offset: 0x18) Global Interrupt Status Register
Definition: component_xdmac.h:67
__IO uint32_t XDMAC_CDUS
(XdmacChid Offset: 0x34) Channel Destination Microblock Stride
Definition: component_xdmac.h:55
#define XDMAC_CIS_FIS
(XDMAC_CIS) End of Flush Interrupt Status Bit
Definition: component_xdmac.h:489
#define XDMAC_GE_EN0
(XDMAC_GE) XDMAC Channel 0 Enable Bit
Definition: component_xdmac.h:212
__O uint32_t XDMAC_GRWR
(Xdmac Offset: 0x34) Global Channel Read Write Resume Register
Definition: component_xdmac.h:74
__I uint32_t XDMAC_GCFG
(Xdmac Offset: 0x04) Global Configuration Register
Definition: component_xdmac.h:62
__O uint32_t XDMAC_CIM
(XdmacChid Offset: 0x8) Channel Interrupt Mask Register
Definition: component_xdmac.h:44
__IO uint32_t XDMAC_CNDA
(XdmacChid Offset: 0x18) Channel Next Descriptor Address Register
Definition: component_xdmac.h:48