RTEMS  5.0.0
Data Fields

Spi hardware registers. More...

#include <component_spi.h>

Data Fields

__O uint32_t SPI_CR
 (Spi Offset: 0x00) Control Register
 
__IO uint32_t SPI_MR
 (Spi Offset: 0x04) Mode Register
 
__I uint32_t SPI_RDR
 (Spi Offset: 0x08) Receive Data Register
 
__O uint32_t SPI_TDR
 (Spi Offset: 0x0C) Transmit Data Register
 
__I uint32_t SPI_SR
 (Spi Offset: 0x10) Status Register
 
__O uint32_t SPI_IER
 (Spi Offset: 0x14) Interrupt Enable Register
 
__O uint32_t SPI_IDR
 (Spi Offset: 0x18) Interrupt Disable Register
 
__I uint32_t SPI_IMR
 (Spi Offset: 0x1C) Interrupt Mask Register
 
__I uint32_t Reserved1 [4]
 
__IO uint32_t SPI_CSR [4]
 (Spi Offset: 0x30) Chip Select Register
 
__I uint32_t Reserved2 [41]
 
__IO uint32_t SPI_WPMR
 (Spi Offset: 0xE4) Write Protection Mode Register
 
__I uint32_t SPI_WPSR
 (Spi Offset: 0xE8) Write Protection Status Register
 
__I uint32_t Reserved3 [4]
 
__I uint32_t SPI_VERSION
 (Spi Offset: 0xFC) Version Register
 

Detailed Description

Spi hardware registers.


The documentation for this struct was generated from the following file: