RTEMS  5.0.0
Data Fields

Pmc hardware registers. More...

#include <component_pmc.h>

Data Fields

__O uint32_t PMC_SCER
 (Pmc Offset: 0x0000) System Clock Enable Register
 
__O uint32_t PMC_SCDR
 (Pmc Offset: 0x0004) System Clock Disable Register
 
__I uint32_t PMC_SCSR
 (Pmc Offset: 0x0008) System Clock Status Register
 
__I uint32_t Reserved1 [1]
 
__O uint32_t PMC_PCER0
 (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0
 
__O uint32_t PMC_PCDR0
 (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0
 
__I uint32_t PMC_PCSR0
 (Pmc Offset: 0x0018) Peripheral Clock Status Register 0
 
__IO uint32_t CKGR_UCKR
 (Pmc Offset: 0x001C) UTMI Clock Register
 
__IO uint32_t CKGR_MOR
 (Pmc Offset: 0x0020) Main Oscillator Register
 
__IO uint32_t CKGR_MCFR
 (Pmc Offset: 0x0024) Main Clock Frequency Register
 
__IO uint32_t CKGR_PLLAR
 (Pmc Offset: 0x0028) PLLA Register
 
__I uint32_t Reserved2 [1]
 
__IO uint32_t PMC_MCKR
 (Pmc Offset: 0x0030) Master Clock Register
 
__I uint32_t Reserved3 [1]
 
__IO uint32_t PMC_USB
 (Pmc Offset: 0x0038) USB Clock Register
 
__I uint32_t Reserved4 [1]
 
__IO uint32_t PMC_PCK [7]
 (Pmc Offset: 0x0040) Programmable Clock 0 Register
 
__I uint32_t Reserved5 [1]
 
__O uint32_t PMC_IER
 (Pmc Offset: 0x0060) Interrupt Enable Register
 
__O uint32_t PMC_IDR
 (Pmc Offset: 0x0064) Interrupt Disable Register
 
__I uint32_t PMC_SR
 (Pmc Offset: 0x0068) Status Register
 
__I uint32_t PMC_IMR
 (Pmc Offset: 0x006C) Interrupt Mask Register
 
__IO uint32_t PMC_FSMR
 (Pmc Offset: 0x0070) Fast Startup Mode Register
 
__IO uint32_t PMC_FSPR
 (Pmc Offset: 0x0074) Fast Startup Polarity Register
 
__O uint32_t PMC_FOCR
 (Pmc Offset: 0x0078) Fault Output Clear Register
 
__I uint32_t Reserved6 [26]
 
__IO uint32_t PMC_WPMR
 (Pmc Offset: 0x00E4) Write Protection Mode Register
 
__I uint32_t PMC_WPSR
 (Pmc Offset: 0x00E8) Write Protection Status Register
 
__I uint32_t Reserved7 [5]
 
__O uint32_t PMC_PCER1
 (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1
 
__O uint32_t PMC_PCDR1
 (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1
 
__I uint32_t PMC_PCSR1
 (Pmc Offset: 0x0108) Peripheral Clock Status Register 1
 
__IO uint32_t PMC_PCR
 (Pmc Offset: 0x010C) Peripheral Control Register
 
__IO uint32_t PMC_OCR
 (Pmc Offset: 0x0110) Oscillator Calibration Register
 
__O uint32_t PMC_SLPWK_ER0
 (Pmc Offset: 0x0114) SleepWalking Enable Register 0
 
__O uint32_t PMC_SLPWK_DR0
 (Pmc Offset: 0x0118) SleepWalking Disable Register 0
 
__I uint32_t PMC_SLPWK_SR0
 (Pmc Offset: 0x011C) SleepWalking Status Register 0
 
__I uint32_t PMC_SLPWK_ASR0
 (Pmc Offset: 0x0120) SleepWalking Activity Status Register 0
 
__I uint32_t Reserved8 [3]
 
__IO uint32_t PMC_PMMR
 (Pmc Offset: 0x0130) PLL Maximum Multiplier Value Register
 
__O uint32_t PMC_SLPWK_ER1
 (Pmc Offset: 0x0134) SleepWalking Enable Register 1
 
__O uint32_t PMC_SLPWK_DR1
 (Pmc Offset: 0x0138) SleepWalking Disable Register 1
 
__I uint32_t PMC_SLPWK_SR1
 (Pmc Offset: 0x013C) SleepWalking Status Register 1
 
__I uint32_t PMC_SLPWK_ASR1
 (Pmc Offset: 0x0140) SleepWalking Activity Status Register 1
 
__I uint32_t PMC_SLPWK_AIPR
 (Pmc Offset: 0x0144) SleepWalking Activity In Progress Register
 
__IO uint32_t PMC_PCK0
 (Pmc Offset: 0x0040) Programmable Clock 0 Register
 
__IO uint32_t PMC_PCK1
 (Pmc Offset: 0x0044) Programmable Clock 1 Register
 
__IO uint32_t PMC_PCK2
 (Pmc Offset: 0x0048) Programmable Clock 2 Register
 
__IO uint32_t PMC_PCK3
 (Pmc Offset: 0x004C) Programmable Clock 3 Register
 
__IO uint32_t PMC_PCK4
 (Pmc Offset: 0x0050) Programmable Clock 4 Register
 
__IO uint32_t PMC_PCK6
 (Pmc Offset: 0x0058) Programmable Clock 6 Register
 
__I uint32_t Reserved9 [3]
 
__I uint32_t PMC_VERSION
 (Pmc Offset: 0x00FC) Version Register
 

Detailed Description

Pmc hardware registers.


The documentation for this struct was generated from the following file: