RTEMS  5.0.0
Data Fields

Mlb hardware registers. More...

#include <component_mlb.h>

Data Fields

__IO uint32_t MLB_MLBC0
 (Mlb Offset: 0x000) MediaLB Control 0 Register
 
__I uint32_t Reserved1 [2]
 
__IO uint32_t MLB_MS0
 (Mlb Offset: 0x00C) MediaLB Channel Status 0 Register
 
__I uint32_t Reserved2 [1]
 
__IO uint32_t MLB_MS1
 (Mlb Offset: 0x014) MediaLB Channel Status1 Register
 
__I uint32_t Reserved3 [2]
 
__IO uint32_t MLB_MSS
 (Mlb Offset: 0x020) MediaLB System Status Register
 
__I uint32_t MLB_MSD
 (Mlb Offset: 0x024) MediaLB System Data Register
 
__I uint32_t Reserved4 [1]
 
__IO uint32_t MLB_MIEN
 (Mlb Offset: 0x02C) MediaLB Interrupt Enable Register
 
__I uint32_t Reserved5 [3]
 
__IO uint32_t MLB_MLBC1
 (Mlb Offset: 0x03C) MediaLB Control 1 Register
 
__I uint32_t Reserved6 [1]
 
__I uint32_t Reserved7 [15]
 
__IO uint32_t MLB_HCTL
 (Mlb Offset: 0x080) HBI Control Register
 
__I uint32_t Reserved8 [1]
 
__IO uint32_t MLB_HCMR [2]
 (Mlb Offset: 0x088) HBI Channel Mask 0 Register
 
__I uint32_t MLB_HCER [2]
 (Mlb Offset: 0x090) HBI Channel Error 0 Register
 
__I uint32_t MLB_HCBR [2]
 (Mlb Offset: 0x098) HBI Channel Busy 0 Register
 
__I uint32_t Reserved9 [8]
 
__IO uint32_t MLB_MDAT [4]
 (Mlb Offset: 0x0C0) MIF Data 0 Register
 
__IO uint32_t MLB_MDWE [4]
 (Mlb Offset: 0x0D0) MIF Data Write Enable 0 Register
 
__IO uint32_t MLB_MCTL
 (Mlb Offset: 0x0E0) MIF Control Register
 
__IO uint32_t MLB_MADR
 (Mlb Offset: 0x0E4) MIF Address Register
 
__I uint32_t Reserved10 [182]
 
__IO uint32_t MLB_ACTL
 (Mlb Offset: 0x3C0) AHB Control Register
 
__I uint32_t Reserved11 [3]
 
__IO uint32_t MLB_ACSR [2]
 (Mlb Offset: 0x3D0) AHB Channel Status 0 Register
 
__IO uint32_t MLB_ACMR [2]
 (Mlb Offset: 0x3D8) AHB Channel Mask 0 Register
 

Detailed Description

Mlb hardware registers.


The documentation for this struct was generated from the following file: