RTEMS  5.0.0
Data Fields

Data Fields

__IO uint32_t GMAC_NCR
 (Gmac Offset: 0x000) Network Control Register
 
__IO uint32_t GMAC_NCFGR
 (Gmac Offset: 0x004) Network Configuration Register
 
__I uint32_t GMAC_NSR
 (Gmac Offset: 0x008) Network Status Register
 
__IO uint32_t GMAC_UR
 (Gmac Offset: 0x00C) User Register
 
__IO uint32_t GMAC_DCFGR
 (Gmac Offset: 0x010) DMA Configuration Register
 
__IO uint32_t GMAC_TSR
 (Gmac Offset: 0x014) Transmit Status Register
 
__IO uint32_t GMAC_RBQB
 (Gmac Offset: 0x018) Receive Buffer Queue Base Address Register
 
__IO uint32_t GMAC_TBQB
 (Gmac Offset: 0x01C) Transmit Buffer Queue Base Address Register
 
__IO uint32_t GMAC_RSR
 (Gmac Offset: 0x020) Receive Status Register
 
__I uint32_t GMAC_ISR
 (Gmac Offset: 0x024) Interrupt Status Register
 
__O uint32_t GMAC_IER
 (Gmac Offset: 0x028) Interrupt Enable Register
 
__O uint32_t GMAC_IDR
 (Gmac Offset: 0x02C) Interrupt Disable Register
 
__IO uint32_t GMAC_IMR
 (Gmac Offset: 0x030) Interrupt Mask Register
 
__IO uint32_t GMAC_MAN
 (Gmac Offset: 0x034) PHY Maintenance Register
 
__I uint32_t GMAC_RPQ
 (Gmac Offset: 0x038) Received Pause Quantum Register
 
__IO uint32_t GMAC_TPQ
 (Gmac Offset: 0x03C) Transmit Pause Quantum Register
 
__IO uint32_t GMAC_TPSF
 (Gmac Offset: 0x040) TX Partial Store and Forward Register
 
__IO uint32_t GMAC_RPSF
 (Gmac Offset: 0x044) RX Partial Store and Forward Register
 
__IO uint32_t GMAC_RJFML
 (Gmac Offset: 0x048) RX Jumbo Frame Max Length Register
 
__I uint32_t Reserved1 [13]
 
__IO uint32_t GMAC_HRB
 (Gmac Offset: 0x080) Hash Register Bottom
 
__IO uint32_t GMAC_HRT
 (Gmac Offset: 0x084) Hash Register Top
 
GmacSa GMAC_SA [GMACSA_NUMBER]
 (Gmac Offset: 0x088) 1 .. 4
 
__IO uint32_t GMAC_TIDM1
 (Gmac Offset: 0x0A8) Type ID Match 1 Register
 
__IO uint32_t GMAC_TIDM2
 (Gmac Offset: 0x0AC) Type ID Match 2 Register
 
__IO uint32_t GMAC_TIDM3
 (Gmac Offset: 0x0B0) Type ID Match 3 Register
 
__IO uint32_t GMAC_TIDM4
 (Gmac Offset: 0x0B4) Type ID Match 4 Register
 
__IO uint32_t GMAC_WOL
 (Gmac Offset: 0x0B8) Wake on LAN Register
 
__IO uint32_t GMAC_IPGS
 (Gmac Offset: 0x0BC) IPG Stretch Register
 
__IO uint32_t GMAC_SVLAN
 (Gmac Offset: 0x0C0) Stacked VLAN Register
 
__IO uint32_t GMAC_TPFCP
 (Gmac Offset: 0x0C4) Transmit PFC Pause Register
 
__IO uint32_t GMAC_SAMB1
 (Gmac Offset: 0x0C8) Specific Address 1 Mask Bottom Register
 
__IO uint32_t GMAC_SAMT1
 (Gmac Offset: 0x0CC) Specific Address 1 Mask Top Register
 
__I uint32_t Reserved2 [3]
 
__IO uint32_t GMAC_NSC
 (Gmac Offset: 0x0DC) 1588 Timer Nanosecond Comparison Register
 
__IO uint32_t GMAC_SCL
 (Gmac Offset: 0x0E0) 1588 Timer Second Comparison Low Register
 
__IO uint32_t GMAC_SCH
 (Gmac Offset: 0x0E4) 1588 Timer Second Comparison High Register
 
__I uint32_t GMAC_EFTSH
 (Gmac Offset: 0x0E8) PTP Event Frame Transmitted Seconds High Register
 
__I uint32_t GMAC_EFRSH
 (Gmac Offset: 0x0EC) PTP Event Frame Received Seconds High Register
 
__I uint32_t GMAC_PEFTSH
 (Gmac Offset: 0x0F0) PTP Peer Event Frame Transmitted Seconds High Register
 
__I uint32_t GMAC_PEFRSH
 (Gmac Offset: 0x0F4) PTP Peer Event Frame Received Seconds High Register
 
__I uint32_t Reserved3 [2]
 
__I uint32_t GMAC_OTLO
 (Gmac Offset: 0x100) Octets Transmitted Low Register
 
__I uint32_t GMAC_OTHI
 (Gmac Offset: 0x104) Octets Transmitted High Register
 
__I uint32_t GMAC_FT
 (Gmac Offset: 0x108) Frames Transmitted Register
 
__I uint32_t GMAC_BCFT
 (Gmac Offset: 0x10C) Broadcast Frames Transmitted Register
 
__I uint32_t GMAC_MFT
 (Gmac Offset: 0x110) Multicast Frames Transmitted Register
 
__I uint32_t GMAC_PFT
 (Gmac Offset: 0x114) Pause Frames Transmitted Register
 
__I uint32_t GMAC_BFT64
 (Gmac Offset: 0x118) 64 Byte Frames Transmitted Register
 
__I uint32_t GMAC_TBFT127
 (Gmac Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register
 
__I uint32_t GMAC_TBFT255
 (Gmac Offset: 0x120) 128 to 255 Byte Frames Transmitted Register
 
__I uint32_t GMAC_TBFT511
 (Gmac Offset: 0x124) 256 to 511 Byte Frames Transmitted Register
 
__I uint32_t GMAC_TBFT1023
 (Gmac Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register
 
__I uint32_t GMAC_TBFT1518
 (Gmac Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register
 
__I uint32_t GMAC_GTBFT1518
 (Gmac Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register
 
__I uint32_t GMAC_TUR
 (Gmac Offset: 0x134) Transmit Underruns Register
 
__I uint32_t GMAC_SCF
 (Gmac Offset: 0x138) Single Collision Frames Register
 
__I uint32_t GMAC_MCF
 (Gmac Offset: 0x13C) Multiple Collision Frames Register
 
__I uint32_t GMAC_EC
 (Gmac Offset: 0x140) Excessive Collisions Register
 
__I uint32_t GMAC_LC
 (Gmac Offset: 0x144) Late Collisions Register
 
__I uint32_t GMAC_DTF
 (Gmac Offset: 0x148) Deferred Transmission Frames Register
 
__I uint32_t GMAC_CSE
 (Gmac Offset: 0x14C) Carrier Sense Errors Register
 
__I uint32_t GMAC_ORLO
 (Gmac Offset: 0x150) Octets Received Low Received Register
 
__I uint32_t GMAC_ORHI
 (Gmac Offset: 0x154) Octets Received High Received Register
 
__I uint32_t GMAC_FR
 (Gmac Offset: 0x158) Frames Received Register
 
__I uint32_t GMAC_BCFR
 (Gmac Offset: 0x15C) Broadcast Frames Received Register
 
__I uint32_t GMAC_MFR
 (Gmac Offset: 0x160) Multicast Frames Received Register
 
__I uint32_t GMAC_PFR
 (Gmac Offset: 0x164) Pause Frames Received Register
 
__I uint32_t GMAC_BFR64
 (Gmac Offset: 0x168) 64 Byte Frames Received Register
 
__I uint32_t GMAC_TBFR127
 (Gmac Offset: 0x16C) 65 to 127 Byte Frames Received Register
 
__I uint32_t GMAC_TBFR255
 (Gmac Offset: 0x170) 128 to 255 Byte Frames Received Register
 
__I uint32_t GMAC_TBFR511
 (Gmac Offset: 0x174) 256 to 511 Byte Frames Received Register
 
__I uint32_t GMAC_TBFR1023
 (Gmac Offset: 0x178) 512 to 1023 Byte Frames Received Register
 
__I uint32_t GMAC_TBFR1518
 (Gmac Offset: 0x17C) 1024 to 1518 Byte Frames Received Register
 
__I uint32_t GMAC_TMXBFR
 (Gmac Offset: 0x180) 1519 to Maximum Byte Frames Received Register
 
__I uint32_t GMAC_UFR
 (Gmac Offset: 0x184) Undersize Frames Received Register
 
__I uint32_t GMAC_OFR
 (Gmac Offset: 0x188) Oversize Frames Received Register
 
__I uint32_t GMAC_JR
 (Gmac Offset: 0x18C) Jabbers Received Register
 
__I uint32_t GMAC_FCSE
 (Gmac Offset: 0x190) Frame Check Sequence Errors Register
 
__I uint32_t GMAC_LFFE
 (Gmac Offset: 0x194) Length Field Frame Errors Register
 
__I uint32_t GMAC_RSE
 (Gmac Offset: 0x198) Receive Symbol Errors Register
 
__I uint32_t GMAC_AE
 (Gmac Offset: 0x19C) Alignment Errors Register
 
__I uint32_t GMAC_RRE
 (Gmac Offset: 0x1A0) Receive Resource Errors Register
 
__I uint32_t GMAC_ROE
 (Gmac Offset: 0x1A4) Receive Overrun Register
 
__I uint32_t GMAC_IHCE
 (Gmac Offset: 0x1A8) IP Header Checksum Errors Register
 
__I uint32_t GMAC_TCE
 (Gmac Offset: 0x1AC) TCP Checksum Errors Register
 
__I uint32_t GMAC_UCE
 (Gmac Offset: 0x1B0) UDP Checksum Errors Register
 
__I uint32_t Reserved4 [2]
 
__IO uint32_t GMAC_TISUBN
 (Gmac Offset: 0x1BC) 1588 Timer Increment Sub-nanoseconds Register
 
__IO uint32_t GMAC_TSH
 (Gmac Offset: 0x1C0) 1588 Timer Seconds High Register
 
__I uint32_t Reserved5 [3]
 
__IO uint32_t GMAC_TSL
 (Gmac Offset: 0x1D0) 1588 Timer Seconds Low Register
 
__IO uint32_t GMAC_TN
 (Gmac Offset: 0x1D4) 1588 Timer Nanoseconds Register
 
__O uint32_t GMAC_TA
 (Gmac Offset: 0x1D8) 1588 Timer Adjust Register
 
__IO uint32_t GMAC_TI
 (Gmac Offset: 0x1DC) 1588 Timer Increment Register
 
__I uint32_t GMAC_EFTSL
 (Gmac Offset: 0x1E0) PTP Event Frame Transmitted Seconds Low Register
 
__I uint32_t GMAC_EFTN
 (Gmac Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds Register
 
__I uint32_t GMAC_EFRSL
 (Gmac Offset: 0x1E8) PTP Event Frame Received Seconds Low Register
 
__I uint32_t GMAC_EFRN
 (Gmac Offset: 0x1EC) PTP Event Frame Received Nanoseconds Register
 
__I uint32_t GMAC_PEFTSL
 (Gmac Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds Low Register
 
__I uint32_t GMAC_PEFTN
 (Gmac Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds Register
 
__I uint32_t GMAC_PEFRSL
 (Gmac Offset: 0x1F8) PTP Peer Event Frame Received Seconds Low Register
 
__I uint32_t GMAC_PEFRN
 (Gmac Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds Register
 
__I uint32_t Reserved6 [128]
 
__I uint32_t GMAC_ISRPQ [2]
 (Gmac Offset: 0x400) Interrupt Status Register Priority Queue (index = 1)
 
__I uint32_t Reserved7 [14]
 
__IO uint32_t GMAC_TBQBAPQ [2]
 (Gmac Offset: 0x440) Transmit Buffer Queue Base Address Register Priority Queue (index = 1)
 
__I uint32_t Reserved8 [14]
 
__IO uint32_t GMAC_RBQBAPQ [2]
 (Gmac Offset: 0x480) Receive Buffer Queue Base Address Register Priority Queue (index = 1)
 
__I uint32_t Reserved9 [6]
 
__IO uint32_t GMAC_RBSRPQ [2]
 (Gmac Offset: 0x4A0) Receive Buffer Size Register Priority Queue (index = 1)
 
__I uint32_t Reserved10 [5]
 
__IO uint32_t GMAC_CBSCR
 (Gmac Offset: 0x4BC) Credit-Based Shaping Control Register
 
__IO uint32_t GMAC_CBSISQA
 (Gmac Offset: 0x4C0) Credit-Based Shaping IdleSlope Register for Queue A
 
__IO uint32_t GMAC_CBSISQB
 (Gmac Offset: 0x4C4) Credit-Based Shaping IdleSlope Register for Queue B
 
__I uint32_t Reserved11 [14]
 
__IO uint32_t GMAC_ST1RPQ [4]
 (Gmac Offset: 0x500) Screening Type 1 Register Priority Queue (index = 0)
 
__I uint32_t Reserved12 [12]
 
__IO uint32_t GMAC_ST2RPQ [8]
 (Gmac Offset: 0x540) Screening Type 2 Register Priority Queue (index = 0)
 
__I uint32_t Reserved13 [12]
 
__I uint32_t Reserved14 [28]
 
__O uint32_t GMAC_IERPQ [2]
 (Gmac Offset: 0x600) Interrupt Enable Register Priority Queue (index = 1)
 
__I uint32_t Reserved15 [6]
 
__O uint32_t GMAC_IDRPQ [2]
 (Gmac Offset: 0x620) Interrupt Disable Register Priority Queue (index = 1)
 
__I uint32_t Reserved16 [6]
 
__IO uint32_t GMAC_IMRPQ [2]
 (Gmac Offset: 0x640) Interrupt Mask Register Priority Queue (index = 1)
 
__I uint32_t Reserved17 [38]
 
__IO uint32_t GMAC_ST2ER [4]
 (Gmac Offset: 0x6E0) Screening Type 2 Ethertype Register (index = 0)
 
__I uint32_t Reserved18 [4]
 
__IO GmacSt2Compare GMAC_ST2COMP [GMACST2COMPARE_NUMBER]
 (Gmac Offset: 0x700) Screener Type 2 Compare Registers
 
__I uint32_t GMAC_MID
 (Gmac Offset: 0x0FC) Module ID Register
 

The documentation for this struct was generated from the following file: