RTEMS  5.0.0
Data Fields

Dacc hardware registers. More...

#include <component_dacc.h>

Data Fields

__O uint32_t DACC_CR
 (Dacc Offset: 0x00) Control Register
 
__IO uint32_t DACC_MR
 (Dacc Offset: 0x04) Mode Register
 
__IO uint32_t DACC_TRIGR
 (Dacc Offset: 0x08) Trigger Register
 
__I uint32_t Reserved1 [1]
 
__O uint32_t DACC_CHER
 (Dacc Offset: 0x10) Channel Enable Register
 
__O uint32_t DACC_CHDR
 (Dacc Offset: 0x14) Channel Disable Register
 
__I uint32_t DACC_CHSR
 (Dacc Offset: 0x18) Channel Status Register
 
__O uint32_t DACC_CDR [2]
 (Dacc Offset: 0x1C) Conversion Data Register
 
__O uint32_t DACC_IER
 (Dacc Offset: 0x24) Interrupt Enable Register
 
__O uint32_t DACC_IDR
 (Dacc Offset: 0x28) Interrupt Disable Register
 
__I uint32_t DACC_IMR
 (Dacc Offset: 0x2C) Interrupt Mask Register
 
__I uint32_t DACC_ISR
 (Dacc Offset: 0x30) Interrupt Status Register
 
__I uint32_t Reserved2 [24]
 
__IO uint32_t DACC_ACR
 (Dacc Offset: 0x94) Analog Current Register
 
__I uint32_t Reserved3 [19]
 
__IO uint32_t DACC_WPMR
 (Dacc Offset: 0xE4) Write Protection Mode Register
 
__I uint32_t DACC_WPSR
 (Dacc Offset: 0xE8) Write Protection Status Register
 
__I uint32_t Reserved4 [4]
 
__I uint32_t DACC_VERSION
 (Dacc Offset: 0xFC) Version Register
 

Detailed Description

Dacc hardware registers.


The documentation for this struct was generated from the following file: