RTEMS  5.0.0
Data Fields

Aes hardware registers. More...

#include <component_aes.h>

Data Fields

__O uint32_t AES_CR
 (Aes Offset: 0x00) Control Register
 
__IO uint32_t AES_MR
 (Aes Offset: 0x04) Mode Register
 
__I uint32_t Reserved1 [2]
 
__O uint32_t AES_IER
 (Aes Offset: 0x10) Interrupt Enable Register
 
__O uint32_t AES_IDR
 (Aes Offset: 0x14) Interrupt Disable Register
 
__I uint32_t AES_IMR
 (Aes Offset: 0x18) Interrupt Mask Register
 
__I uint32_t AES_ISR
 (Aes Offset: 0x1C) Interrupt Status Register
 
__O uint32_t AES_KEYWR [8]
 (Aes Offset: 0x20) Key Word Register
 
__O uint32_t AES_IDATAR [4]
 (Aes Offset: 0x40) Input Data Register
 
__I uint32_t AES_ODATAR [4]
 (Aes Offset: 0x50) Output Data Register
 
__O uint32_t AES_IVR [4]
 (Aes Offset: 0x60) Initialization Vector Register
 
__IO uint32_t AES_AADLENR
 (Aes Offset: 0x70) Additional Authenticated Data Length Register
 
__IO uint32_t AES_CLENR
 (Aes Offset: 0x74) Plaintext/Ciphertext Length Register
 
__IO uint32_t AES_GHASHR [4]
 (Aes Offset: 0x78) GCM Intermediate Hash Word Register
 
__I uint32_t AES_TAGR [4]
 (Aes Offset: 0x88) GCM Authentication Tag Word Register
 
__I uint32_t AES_CTRR
 (Aes Offset: 0x98) GCM Encryption Counter Value Register
 
__IO uint32_t AES_GCMHR [4]
 (Aes Offset: 0x9C) GCM H Word Register
 
__I uint32_t Reserved2 [20]
 
__I uint32_t AES_VERSION
 (Aes Offset: 0xFC) Version Register
 

Detailed Description

Aes hardware registers.


The documentation for this struct was generated from the following file: