RTEMS
5.0.0
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#include <alt_i2c.h>
Data Fields | |
ALT_I2C_ADDR_MODE_t | addr_mode |
bool | restart_enable |
ALT_I2C_SPEED_t | speed_mode |
uint16_t | ss_scl_hcnt |
uint16_t | ss_scl_lcnt |
uint16_t | fs_scl_hcnt |
uint16_t | fs_scl_lcnt |
uint8_t | fs_spklen |
This type defines a structure for configuration of the SCL high and low counts to ensure proper I/O timing with the device interface.
The SCL count values are only relevant if the I2C controller is enabled to as an I2C master. The SCL count values are ignored when the I2C controller is enabled as an I2C slave.
See: Clock Frequency Configuration section of Chapter 20. I2C Controller in the Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual for a complete discussion of calculation of the proper SCL clock high and low times.
ALT_I2C_ADDR_MODE_t ALT_I2C_MASTER_CONFIG_s::addr_mode |
The address mode (7 or 10 bit) when acting as a master.
uint16_t ALT_I2C_MASTER_CONFIG_s::fs_scl_hcnt |
The SCL clock high-period count for fast speed.
uint16_t ALT_I2C_MASTER_CONFIG_s::fs_scl_lcnt |
The SCL clock low-period count for fast speed.
uint8_t ALT_I2C_MASTER_CONFIG_s::fs_spklen |
The duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS or FS modes.
bool ALT_I2C_MASTER_CONFIG_s::restart_enable |
This setting determines whether RESTART conditions may be sent when acting as a master. When the restart_enable is false, the I2C controller master is incapable of performing the following functions:
ALT_I2C_SPEED_t ALT_I2C_MASTER_CONFIG_s::speed_mode |
The speed mode of the I2C operation.
uint16_t ALT_I2C_MASTER_CONFIG_s::ss_scl_hcnt |
The SCL clock high-period count for standard speed.
uint16_t ALT_I2C_MASTER_CONFIG_s::ss_scl_lcnt |
The SCL clock low-period count for standard speed.