RTEMS  5.0.0
regs.h
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1 
7 /*
8  * regs.S -- standard MIPS register names.
9  *
10  * Copyright (c) 1995 Cygnus Support
11  *
12  * The authors hereby grant permission to use, copy, modify, distribute,
13  * and license this software and its documentation for any purpose, provided
14  * that existing copyright notices are retained in all copies and that this
15  * notice is included verbatim in any distributions. No written agreement,
16  * license, or royalty fee is required for any of the authorized uses.
17  * Modifications to this software may be copyrighted by their authors
18  * and need not follow the licensing terms described here, provided that
19  * the new terms are clearly indicated on the first page of each file where
20  * they apply.
21  */
22 
35 #define zero $0
36 #define z0 $0
37 #define v0 $2
38 #define v1 $3
39 #define a0 $4
40 #define a1 $5
41 #define a2 $6
42 #define a3 $7
43 #define t0 $8
44 #define t1 $9
45 #define t2 $10
46 #define t3 $11
47 #define t4 $12
48 #define t5 $13
49 #define t6 $14
50 #define t7 $15
51 #define s0 $16
52 #define s1 $17
53 #define s2 $18
54 #define s3 $19
55 #define s4 $20
56 #define s5 $21
57 #define s6 $22
58 #define s7 $23
59 #define t8 $24
60 #define t9 $25
61 #define k0 $26
62 #define k1 $27
63 #define gp $28
64 #define sp $29
65 #define fp $30
66 #define ra $31
67 #define pc $pc
68 
69 #define fp0 $f0
70 #define fp1 $f1
71 
79 #define K0BASE 0x80000000
80 #ifndef __mips64
81 #define K1BASE 0xA0000000
82 #else
83 #define K1BASE 0xFFFFFFFFA0000000LL
84 #endif
85 
88 #define PHYS_TO_K1(a) ((unsigned)(a) | K1BASE)
89 
95 #define C0_COUNT $9
96 #define C0_SR $12
97 #define C0_CAUSE $13
98 #define C0_EPC $14
99 #define C0_CONFIG $16
100 
101 
108 #define SR_CU1 0x20000000
109 #define SR_FR 0x04000000
110 #define SR_BEV 0x00400000
111 #define SR_PE 0x00100000
112 
113 #define SR_KX 0x00000080
114 #define SR_SX 0x00000040
115 #define SR_UX 0x00000020
116 
117 
125 #define CACHE_I (0)
126 #define CACHE_D (1)
127 #define CACHE_SI (2)
128 #define CACHE_SD (3)
129 
130 #define INDEX_INVALIDATE (0)
131 #define INDEX_LOAD_TAG (1)
132 #define INDEX_STORE_TAG (2)
133 #define CREATE_DIRTY_EXCLUSIVE (3)
134 #define HIT_INVALIDATE (4)
135 #define CACHE_FILL (5)
136 #define HIT_WRITEBACK_INVALIDATE (5)
137 #define HIT_WRITEBACK (6)
138 #define HIT_SET_VIRTUAL (7)
139 
140 #define BUILD_CACHE_OP(o,c) (((o) << 2) | (c))
141 
149 #define INDEX_INVALIDATE_I BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I)
150 #define INDEX_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D)
151 #define INDEX_INVALIDATE_SI BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI)
152 #define INDEX_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD)
153 
154 #define INDEX_LOAD_TAG_I BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I)
155 #define INDEX_LOAD_TAG_D BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D)
156 #define INDEX_LOAD_TAG_SI BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI)
157 #define INDEX_LOAD_TAG_SD BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD)
158 
159 #define INDEX_STORE_TAG_I BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I)
160 #define INDEX_STORE_TAG_D BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D)
161 #define INDEX_STORE_TAG_SI BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI)
162 #define INDEX_STORE_TAG_SD BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SD)
163 
164 #define CREATE_DIRTY_EXCLUSIVE_D BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_D)
165 #define CREATE_DIRTY_EXCLUSIVE_SD BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_SD)
166 
167 #define HIT_INVALIDATE_I BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_I)
168 #define HIT_INVALIDATE_D BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_D)
169 #define HIT_INVALIDATE_SI BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SI)
170 #define HIT_INVALIDATE_SD BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SD)
171 
172 #define CACHE_FILL_I BUILD_CACHE_OP(CACHE_FILL,CACHE_I)
173 #define HIT_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_D)
174 #define HIT_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_SD)
175 
176 #define HIT_WRITEBACK_I BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_I)
177 #define HIT_WRITEBACK_D BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_D)
178 #define HIT_WRITEBACK_SD BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD)
179 
180 #define HIT_SET_VIRTUAL_SI BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI)
181 #define HIT_SET_VIRTUAL_SD BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD)
182 
187 /*> EOF regs.S <*/