RTEMS  5.0.0
Data Structures | Macros

Data Structures

struct  Rswdt
 Rswdt hardware registers. More...
 

Macros

#define RSWDT_CR_WDRSTT   (0x1u << 0)
 (RSWDT_CR) Watchdog Restart
 
#define RSWDT_CR_KEY_Pos   24
 
#define RSWDT_CR_KEY_Msk   (0xffu << RSWDT_CR_KEY_Pos)
 (RSWDT_CR) Password
 
#define RSWDT_CR_KEY(value)   ((RSWDT_CR_KEY_Msk & ((value) << RSWDT_CR_KEY_Pos)))
 
#define RSWDT_CR_KEY_PASSWD   (0xC4u << 24)
 (RSWDT_CR) Writing any other value in this field aborts the write operation.
 
#define RSWDT_MR_WDV_Pos   0
 
#define RSWDT_MR_WDV_Msk   (0xfffu << RSWDT_MR_WDV_Pos)
 (RSWDT_MR) Watchdog Counter Value
 
#define RSWDT_MR_WDV(value)   ((RSWDT_MR_WDV_Msk & ((value) << RSWDT_MR_WDV_Pos)))
 
#define RSWDT_MR_WDFIEN   (0x1u << 12)
 (RSWDT_MR) Watchdog Fault Interrupt Enable
 
#define RSWDT_MR_WDRSTEN   (0x1u << 13)
 (RSWDT_MR) Watchdog Reset Enable
 
#define RSWDT_MR_WDRPROC   (0x1u << 14)
 (RSWDT_MR) Watchdog Reset Processor
 
#define RSWDT_MR_WDDIS   (0x1u << 15)
 (RSWDT_MR) Watchdog Disable
 
#define RSWDT_MR_ALLONES_Pos   16
 
#define RSWDT_MR_ALLONES_Msk   (0xfffu << RSWDT_MR_ALLONES_Pos)
 (RSWDT_MR) Must Always Be Written with 0xFFF
 
#define RSWDT_MR_ALLONES(value)   ((RSWDT_MR_ALLONES_Msk & ((value) << RSWDT_MR_ALLONES_Pos)))
 
#define RSWDT_MR_WDDBGHLT   (0x1u << 28)
 (RSWDT_MR) Watchdog Debug Halt
 
#define RSWDT_MR_WDIDLEHLT   (0x1u << 29)
 (RSWDT_MR) Watchdog Idle Halt
 
#define RSWDT_SR_WDUNF   (0x1u << 0)
 (RSWDT_SR) Watchdog Underflow
 

Detailed Description

SOFTWARE API DEFINITION FOR Reinforced Safety Watchdog Timer