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#define | AFEC_CR_SWRST (0x1u << 0) |
| | (AFEC_CR) Software Reset
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#define | AFEC_CR_START (0x1u << 1) |
| | (AFEC_CR) Start Conversion
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#define | AFEC_MR_TRGEN (0x1u << 0) |
| | (AFEC_MR) Trigger Enable
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#define | AFEC_MR_TRGEN_DIS (0x0u << 0) |
| | (AFEC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software.
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#define | AFEC_MR_TRGEN_EN (0x1u << 0) |
| | (AFEC_MR) Hardware trigger selected by TRGSEL field is enabled.
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#define | AFEC_MR_TRGSEL_Pos 1 |
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#define | AFEC_MR_TRGSEL_Msk (0x7u << AFEC_MR_TRGSEL_Pos) |
| | (AFEC_MR) Trigger Selection
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#define | AFEC_MR_TRGSEL(value) ((AFEC_MR_TRGSEL_Msk & ((value) << AFEC_MR_TRGSEL_Pos))) |
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#define | AFEC_MR_TRGSEL_AFEC_TRIG0 (0x0u << 1) |
| | (AFEC_MR) AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1
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#define | AFEC_MR_TRGSEL_AFEC_TRIG1 (0x1u << 1) |
| | (AFEC_MR) TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1
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#define | AFEC_MR_TRGSEL_AFEC_TRIG2 (0x2u << 1) |
| | (AFEC_MR) TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1
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#define | AFEC_MR_TRGSEL_AFEC_TRIG3 (0x3u << 1) |
| | (AFEC_MR) TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1
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#define | AFEC_MR_TRGSEL_AFEC_TRIG4 (0x4u << 1) |
| | (AFEC_MR) PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1
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#define | AFEC_MR_TRGSEL_AFEC_TRIG5 (0x5u << 1) |
| | (AFEC_MR) PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1
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#define | AFEC_MR_TRGSEL_AFEC_TRIG6 (0x6u << 1) |
| | (AFEC_MR) Analog Comparator
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#define | AFEC_MR_SLEEP (0x1u << 5) |
| | (AFEC_MR) Sleep Mode
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#define | AFEC_MR_SLEEP_NORMAL (0x0u << 5) |
| | (AFEC_MR) Normal mode: The AFE and reference voltage circuitry are kept ON between conversions.
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#define | AFEC_MR_SLEEP_SLEEP (0x1u << 5) |
| | (AFEC_MR) Sleep mode: The AFE and reference voltage circuitry are OFF between conversions.
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#define | AFEC_MR_FWUP (0x1u << 6) |
| | (AFEC_MR) Fast Wake-up
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#define | AFEC_MR_FWUP_OFF (0x0u << 6) |
| | (AFEC_MR) Normal Sleep mode: The sleep mode is defined by the SLEEP bit.
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#define | AFEC_MR_FWUP_ON (0x1u << 6) |
| | (AFEC_MR) Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF.
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#define | AFEC_MR_FREERUN (0x1u << 7) |
| | (AFEC_MR) Free Run Mode
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#define | AFEC_MR_FREERUN_OFF (0x0u << 7) |
| | (AFEC_MR) Normal mode
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#define | AFEC_MR_FREERUN_ON (0x1u << 7) |
| | (AFEC_MR) Free Run mode: Never wait for any trigger.
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#define | AFEC_MR_PRESCAL_Pos 8 |
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#define | AFEC_MR_PRESCAL_Msk (0xffu << AFEC_MR_PRESCAL_Pos) |
| | (AFEC_MR) Prescaler Rate Selection
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#define | AFEC_MR_PRESCAL(value) ((AFEC_MR_PRESCAL_Msk & ((value) << AFEC_MR_PRESCAL_Pos))) |
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#define | AFEC_MR_STARTUP_Pos 16 |
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#define | AFEC_MR_STARTUP_Msk (0xfu << AFEC_MR_STARTUP_Pos) |
| | (AFEC_MR) Start-up Time
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#define | AFEC_MR_STARTUP(value) ((AFEC_MR_STARTUP_Msk & ((value) << AFEC_MR_STARTUP_Pos))) |
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#define | AFEC_MR_STARTUP_SUT0 (0x0u << 16) |
| | (AFEC_MR) 0 periods of AFE clock
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#define | AFEC_MR_STARTUP_SUT8 (0x1u << 16) |
| | (AFEC_MR) 8 periods of AFE clock
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#define | AFEC_MR_STARTUP_SUT16 (0x2u << 16) |
| | (AFEC_MR) 16 periods of AFE clock
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#define | AFEC_MR_STARTUP_SUT24 (0x3u << 16) |
| | (AFEC_MR) 24 periods of AFE clock
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#define | AFEC_MR_STARTUP_SUT64 (0x4u << 16) |
| | (AFEC_MR) 64 periods of AFE clock
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#define | AFEC_MR_STARTUP_SUT80 (0x5u << 16) |
| | (AFEC_MR) 80 periods of AFE clock
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#define | AFEC_MR_STARTUP_SUT96 (0x6u << 16) |
| | (AFEC_MR) 96 periods of AFE clock
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#define | AFEC_MR_STARTUP_SUT112 (0x7u << 16) |
| | (AFEC_MR) 112 periods of AFE clock
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#define | AFEC_MR_STARTUP_SUT512 (0x8u << 16) |
| | (AFEC_MR) 512 periods of AFE clock
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#define | AFEC_MR_STARTUP_SUT576 (0x9u << 16) |
| | (AFEC_MR) 576 periods of AFE clock
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#define | AFEC_MR_STARTUP_SUT640 (0xAu << 16) |
| | (AFEC_MR) 640 periods of AFE clock
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#define | AFEC_MR_STARTUP_SUT704 (0xBu << 16) |
| | (AFEC_MR) 704 periods of AFE clock
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#define | AFEC_MR_STARTUP_SUT768 (0xCu << 16) |
| | (AFEC_MR) 768 periods of AFE clock
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#define | AFEC_MR_STARTUP_SUT832 (0xDu << 16) |
| | (AFEC_MR) 832 periods of AFE clock
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#define | AFEC_MR_STARTUP_SUT896 (0xEu << 16) |
| | (AFEC_MR) 896 periods of AFE clock
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#define | AFEC_MR_STARTUP_SUT960 (0xFu << 16) |
| | (AFEC_MR) 960 periods of AFE clock
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#define | AFEC_MR_ONE (0x1u << 23) |
| | (AFEC_MR) One
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#define | AFEC_MR_TRACKTIM_Pos 24 |
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#define | AFEC_MR_TRACKTIM_Msk (0xfu << AFEC_MR_TRACKTIM_Pos) |
| | (AFEC_MR) Tracking Time
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#define | AFEC_MR_TRACKTIM(value) ((AFEC_MR_TRACKTIM_Msk & ((value) << AFEC_MR_TRACKTIM_Pos))) |
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#define | AFEC_MR_TRANSFER_Pos 28 |
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#define | AFEC_MR_TRANSFER_Msk (0x3u << AFEC_MR_TRANSFER_Pos) |
| | (AFEC_MR) Transfer Period
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#define | AFEC_MR_TRANSFER(value) ((AFEC_MR_TRANSFER_Msk & ((value) << AFEC_MR_TRANSFER_Pos))) |
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#define | AFEC_MR_USEQ (0x1u << 31) |
| | (AFEC_MR) User Sequence Enable
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#define | AFEC_MR_USEQ_NUM_ORDER (0x0u << 31) |
| | (AFEC_MR) Normal mode: The controller converts channels in a simple numeric order.
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#define | AFEC_MR_USEQ_REG_ORDER (0x1u << 31) |
| | (AFEC_MR) User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R.
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#define | AFEC_EMR_CMPMODE_Pos 0 |
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#define | AFEC_EMR_CMPMODE_Msk (0x3u << AFEC_EMR_CMPMODE_Pos) |
| | (AFEC_EMR) Comparison Mode
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#define | AFEC_EMR_CMPMODE(value) ((AFEC_EMR_CMPMODE_Msk & ((value) << AFEC_EMR_CMPMODE_Pos))) |
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#define | AFEC_EMR_CMPMODE_LOW (0x0u << 0) |
| | (AFEC_EMR) Generates an event when the converted data is lower than the low threshold of the window.
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#define | AFEC_EMR_CMPMODE_HIGH (0x1u << 0) |
| | (AFEC_EMR) Generates an event when the converted data is higher than the high threshold of the window.
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#define | AFEC_EMR_CMPMODE_IN (0x2u << 0) |
| | (AFEC_EMR) Generates an event when the converted data is in the comparison window.
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#define | AFEC_EMR_CMPMODE_OUT (0x3u << 0) |
| | (AFEC_EMR) Generates an event when the converted data is out of the comparison window.
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#define | AFEC_EMR_CMPSEL_Pos 3 |
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#define | AFEC_EMR_CMPSEL_Msk (0x1fu << AFEC_EMR_CMPSEL_Pos) |
| | (AFEC_EMR) Comparison Selected Channel
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#define | AFEC_EMR_CMPSEL(value) ((AFEC_EMR_CMPSEL_Msk & ((value) << AFEC_EMR_CMPSEL_Pos))) |
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#define | AFEC_EMR_CMPALL (0x1u << 9) |
| | (AFEC_EMR) Compare All Channels
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#define | AFEC_EMR_CMPFILTER_Pos 12 |
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#define | AFEC_EMR_CMPFILTER_Msk (0x3u << AFEC_EMR_CMPFILTER_Pos) |
| | (AFEC_EMR) Compare Event Filtering
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#define | AFEC_EMR_CMPFILTER(value) ((AFEC_EMR_CMPFILTER_Msk & ((value) << AFEC_EMR_CMPFILTER_Pos))) |
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#define | AFEC_EMR_RES_Pos 16 |
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#define | AFEC_EMR_RES_Msk (0x7u << AFEC_EMR_RES_Pos) |
| | (AFEC_EMR) Resolution
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#define | AFEC_EMR_RES(value) ((AFEC_EMR_RES_Msk & ((value) << AFEC_EMR_RES_Pos))) |
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#define | AFEC_EMR_RES_NO_AVERAGE (0x0u << 16) |
| | (AFEC_EMR) 12-bit resolution, AFE sample rate is maximum (no averaging).
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#define | AFEC_EMR_RES_OSR4 (0x2u << 16) |
| | (AFEC_EMR) 13-bit resolution, AFE sample rate divided by 4 (averaging).
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#define | AFEC_EMR_RES_OSR16 (0x3u << 16) |
| | (AFEC_EMR) 14-bit resolution, AFE sample rate divided by 16 (averaging).
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#define | AFEC_EMR_RES_OSR64 (0x4u << 16) |
| | (AFEC_EMR) 15-bit resolution, AFE sample rate divided by 64 (averaging).
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#define | AFEC_EMR_RES_OSR256 (0x5u << 16) |
| | (AFEC_EMR) 16-bit resolution, AFE sample rate divided by 256 (averaging).
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#define | AFEC_EMR_TAG (0x1u << 24) |
| | (AFEC_EMR) TAG of the AFEC_LDCR
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#define | AFEC_EMR_STM (0x1u << 25) |
| | (AFEC_EMR) Single Trigger Mode
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#define | AFEC_EMR_SIGNMODE_Pos 28 |
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#define | AFEC_EMR_SIGNMODE_Msk (0x3u << AFEC_EMR_SIGNMODE_Pos) |
| | (AFEC_EMR) Sign Mode
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#define | AFEC_EMR_SIGNMODE(value) ((AFEC_EMR_SIGNMODE_Msk & ((value) << AFEC_EMR_SIGNMODE_Pos))) |
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#define | AFEC_EMR_SIGNMODE_SE_UNSG_DF_SIGN (0x0u << 28) |
| | (AFEC_EMR) Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions.
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#define | AFEC_EMR_SIGNMODE_SE_SIGN_DF_UNSG (0x1u << 28) |
| | (AFEC_EMR) Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions.
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#define | AFEC_EMR_SIGNMODE_ALL_UNSIGNED (0x2u << 28) |
| | (AFEC_EMR) All channels: Unsigned conversions.
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#define | AFEC_EMR_SIGNMODE_ALL_SIGNED (0x3u << 28) |
| | (AFEC_EMR) All channels: Signed conversions.
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#define | AFEC_SEQ1R_USCH0_Pos 0 |
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#define | AFEC_SEQ1R_USCH0_Msk (0xfu << AFEC_SEQ1R_USCH0_Pos) |
| | (AFEC_SEQ1R) User Sequence Number 0
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#define | AFEC_SEQ1R_USCH0(value) ((AFEC_SEQ1R_USCH0_Msk & ((value) << AFEC_SEQ1R_USCH0_Pos))) |
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#define | AFEC_SEQ1R_USCH1_Pos 4 |
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#define | AFEC_SEQ1R_USCH1_Msk (0xfu << AFEC_SEQ1R_USCH1_Pos) |
| | (AFEC_SEQ1R) User Sequence Number 1
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#define | AFEC_SEQ1R_USCH1(value) ((AFEC_SEQ1R_USCH1_Msk & ((value) << AFEC_SEQ1R_USCH1_Pos))) |
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#define | AFEC_SEQ1R_USCH2_Pos 8 |
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#define | AFEC_SEQ1R_USCH2_Msk (0xfu << AFEC_SEQ1R_USCH2_Pos) |
| | (AFEC_SEQ1R) User Sequence Number 2
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#define | AFEC_SEQ1R_USCH2(value) ((AFEC_SEQ1R_USCH2_Msk & ((value) << AFEC_SEQ1R_USCH2_Pos))) |
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#define | AFEC_SEQ1R_USCH3_Pos 12 |
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#define | AFEC_SEQ1R_USCH3_Msk (0xfu << AFEC_SEQ1R_USCH3_Pos) |
| | (AFEC_SEQ1R) User Sequence Number 3
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#define | AFEC_SEQ1R_USCH3(value) ((AFEC_SEQ1R_USCH3_Msk & ((value) << AFEC_SEQ1R_USCH3_Pos))) |
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#define | AFEC_SEQ1R_USCH4_Pos 16 |
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#define | AFEC_SEQ1R_USCH4_Msk (0xfu << AFEC_SEQ1R_USCH4_Pos) |
| | (AFEC_SEQ1R) User Sequence Number 4
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#define | AFEC_SEQ1R_USCH4(value) ((AFEC_SEQ1R_USCH4_Msk & ((value) << AFEC_SEQ1R_USCH4_Pos))) |
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#define | AFEC_SEQ1R_USCH5_Pos 20 |
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#define | AFEC_SEQ1R_USCH5_Msk (0xfu << AFEC_SEQ1R_USCH5_Pos) |
| | (AFEC_SEQ1R) User Sequence Number 5
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#define | AFEC_SEQ1R_USCH5(value) ((AFEC_SEQ1R_USCH5_Msk & ((value) << AFEC_SEQ1R_USCH5_Pos))) |
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#define | AFEC_SEQ1R_USCH6_Pos 24 |
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#define | AFEC_SEQ1R_USCH6_Msk (0xfu << AFEC_SEQ1R_USCH6_Pos) |
| | (AFEC_SEQ1R) User Sequence Number 6
|
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#define | AFEC_SEQ1R_USCH6(value) ((AFEC_SEQ1R_USCH6_Msk & ((value) << AFEC_SEQ1R_USCH6_Pos))) |
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#define | AFEC_SEQ1R_USCH7_Pos 28 |
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#define | AFEC_SEQ1R_USCH7_Msk (0xfu << AFEC_SEQ1R_USCH7_Pos) |
| | (AFEC_SEQ1R) User Sequence Number 7
|
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#define | AFEC_SEQ1R_USCH7(value) ((AFEC_SEQ1R_USCH7_Msk & ((value) << AFEC_SEQ1R_USCH7_Pos))) |
| |
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#define | AFEC_SEQ2R_USCH8_Pos 0 |
| |
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#define | AFEC_SEQ2R_USCH8_Msk (0xfu << AFEC_SEQ2R_USCH8_Pos) |
| | (AFEC_SEQ2R) User Sequence Number 8
|
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#define | AFEC_SEQ2R_USCH8(value) ((AFEC_SEQ2R_USCH8_Msk & ((value) << AFEC_SEQ2R_USCH8_Pos))) |
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#define | AFEC_SEQ2R_USCH9_Pos 4 |
| |
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#define | AFEC_SEQ2R_USCH9_Msk (0xfu << AFEC_SEQ2R_USCH9_Pos) |
| | (AFEC_SEQ2R) User Sequence Number 9
|
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#define | AFEC_SEQ2R_USCH9(value) ((AFEC_SEQ2R_USCH9_Msk & ((value) << AFEC_SEQ2R_USCH9_Pos))) |
| |
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#define | AFEC_SEQ2R_USCH10_Pos 8 |
| |
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#define | AFEC_SEQ2R_USCH10_Msk (0xfu << AFEC_SEQ2R_USCH10_Pos) |
| | (AFEC_SEQ2R) User Sequence Number 10
|
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#define | AFEC_SEQ2R_USCH10(value) ((AFEC_SEQ2R_USCH10_Msk & ((value) << AFEC_SEQ2R_USCH10_Pos))) |
| |
|
#define | AFEC_SEQ2R_USCH11_Pos 12 |
| |
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#define | AFEC_SEQ2R_USCH11_Msk (0xfu << AFEC_SEQ2R_USCH11_Pos) |
| | (AFEC_SEQ2R) User Sequence Number 11
|
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#define | AFEC_SEQ2R_USCH11(value) ((AFEC_SEQ2R_USCH11_Msk & ((value) << AFEC_SEQ2R_USCH11_Pos))) |
| |
|
#define | AFEC_SEQ2R_USCH12_Pos 16 |
| |
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#define | AFEC_SEQ2R_USCH12_Msk (0xfu << AFEC_SEQ2R_USCH12_Pos) |
| | (AFEC_SEQ2R) User Sequence Number 12
|
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#define | AFEC_SEQ2R_USCH12(value) ((AFEC_SEQ2R_USCH12_Msk & ((value) << AFEC_SEQ2R_USCH12_Pos))) |
| |
|
#define | AFEC_SEQ2R_USCH13_Pos 20 |
| |
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#define | AFEC_SEQ2R_USCH13_Msk (0xfu << AFEC_SEQ2R_USCH13_Pos) |
| | (AFEC_SEQ2R) User Sequence Number 13
|
| |
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#define | AFEC_SEQ2R_USCH13(value) ((AFEC_SEQ2R_USCH13_Msk & ((value) << AFEC_SEQ2R_USCH13_Pos))) |
| |
|
#define | AFEC_SEQ2R_USCH14_Pos 24 |
| |
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#define | AFEC_SEQ2R_USCH14_Msk (0xfu << AFEC_SEQ2R_USCH14_Pos) |
| | (AFEC_SEQ2R) User Sequence Number 14
|
| |
|
#define | AFEC_SEQ2R_USCH14(value) ((AFEC_SEQ2R_USCH14_Msk & ((value) << AFEC_SEQ2R_USCH14_Pos))) |
| |
|
#define | AFEC_SEQ2R_USCH15_Pos 28 |
| |
|
#define | AFEC_SEQ2R_USCH15_Msk (0xfu << AFEC_SEQ2R_USCH15_Pos) |
| | (AFEC_SEQ2R) User Sequence Number 15
|
| |
|
#define | AFEC_SEQ2R_USCH15(value) ((AFEC_SEQ2R_USCH15_Msk & ((value) << AFEC_SEQ2R_USCH15_Pos))) |
| |
|
#define | AFEC_CHER_CH0 (0x1u << 0) |
| | (AFEC_CHER) Channel 0 Enable
|
| |
|
#define | AFEC_CHER_CH1 (0x1u << 1) |
| | (AFEC_CHER) Channel 1 Enable
|
| |
|
#define | AFEC_CHER_CH2 (0x1u << 2) |
| | (AFEC_CHER) Channel 2 Enable
|
| |
|
#define | AFEC_CHER_CH3 (0x1u << 3) |
| | (AFEC_CHER) Channel 3 Enable
|
| |
|
#define | AFEC_CHER_CH4 (0x1u << 4) |
| | (AFEC_CHER) Channel 4 Enable
|
| |
|
#define | AFEC_CHER_CH5 (0x1u << 5) |
| | (AFEC_CHER) Channel 5 Enable
|
| |
|
#define | AFEC_CHER_CH6 (0x1u << 6) |
| | (AFEC_CHER) Channel 6 Enable
|
| |
|
#define | AFEC_CHER_CH7 (0x1u << 7) |
| | (AFEC_CHER) Channel 7 Enable
|
| |
|
#define | AFEC_CHER_CH8 (0x1u << 8) |
| | (AFEC_CHER) Channel 8 Enable
|
| |
|
#define | AFEC_CHER_CH9 (0x1u << 9) |
| | (AFEC_CHER) Channel 9 Enable
|
| |
|
#define | AFEC_CHER_CH10 (0x1u << 10) |
| | (AFEC_CHER) Channel 10 Enable
|
| |
|
#define | AFEC_CHER_CH11 (0x1u << 11) |
| | (AFEC_CHER) Channel 11 Enable
|
| |
|
#define | AFEC_CHDR_CH0 (0x1u << 0) |
| | (AFEC_CHDR) Channel 0 Disable
|
| |
|
#define | AFEC_CHDR_CH1 (0x1u << 1) |
| | (AFEC_CHDR) Channel 1 Disable
|
| |
|
#define | AFEC_CHDR_CH2 (0x1u << 2) |
| | (AFEC_CHDR) Channel 2 Disable
|
| |
|
#define | AFEC_CHDR_CH3 (0x1u << 3) |
| | (AFEC_CHDR) Channel 3 Disable
|
| |
|
#define | AFEC_CHDR_CH4 (0x1u << 4) |
| | (AFEC_CHDR) Channel 4 Disable
|
| |
|
#define | AFEC_CHDR_CH5 (0x1u << 5) |
| | (AFEC_CHDR) Channel 5 Disable
|
| |
|
#define | AFEC_CHDR_CH6 (0x1u << 6) |
| | (AFEC_CHDR) Channel 6 Disable
|
| |
|
#define | AFEC_CHDR_CH7 (0x1u << 7) |
| | (AFEC_CHDR) Channel 7 Disable
|
| |
|
#define | AFEC_CHDR_CH8 (0x1u << 8) |
| | (AFEC_CHDR) Channel 8 Disable
|
| |
|
#define | AFEC_CHDR_CH9 (0x1u << 9) |
| | (AFEC_CHDR) Channel 9 Disable
|
| |
|
#define | AFEC_CHDR_CH10 (0x1u << 10) |
| | (AFEC_CHDR) Channel 10 Disable
|
| |
|
#define | AFEC_CHDR_CH11 (0x1u << 11) |
| | (AFEC_CHDR) Channel 11 Disable
|
| |
|
#define | AFEC_CHSR_CH0 (0x1u << 0) |
| | (AFEC_CHSR) Channel 0 Status
|
| |
|
#define | AFEC_CHSR_CH1 (0x1u << 1) |
| | (AFEC_CHSR) Channel 1 Status
|
| |
|
#define | AFEC_CHSR_CH2 (0x1u << 2) |
| | (AFEC_CHSR) Channel 2 Status
|
| |
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#define | AFEC_CHSR_CH3 (0x1u << 3) |
| | (AFEC_CHSR) Channel 3 Status
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#define | AFEC_CHSR_CH4 (0x1u << 4) |
| | (AFEC_CHSR) Channel 4 Status
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#define | AFEC_CHSR_CH5 (0x1u << 5) |
| | (AFEC_CHSR) Channel 5 Status
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#define | AFEC_CHSR_CH6 (0x1u << 6) |
| | (AFEC_CHSR) Channel 6 Status
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#define | AFEC_CHSR_CH7 (0x1u << 7) |
| | (AFEC_CHSR) Channel 7 Status
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#define | AFEC_CHSR_CH8 (0x1u << 8) |
| | (AFEC_CHSR) Channel 8 Status
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#define | AFEC_CHSR_CH9 (0x1u << 9) |
| | (AFEC_CHSR) Channel 9 Status
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#define | AFEC_CHSR_CH10 (0x1u << 10) |
| | (AFEC_CHSR) Channel 10 Status
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#define | AFEC_CHSR_CH11 (0x1u << 11) |
| | (AFEC_CHSR) Channel 11 Status
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#define | AFEC_LCDR_LDATA_Pos 0 |
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#define | AFEC_LCDR_LDATA_Msk (0xffffu << AFEC_LCDR_LDATA_Pos) |
| | (AFEC_LCDR) Last Data Converted
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#define | AFEC_LCDR_CHNB_Pos 24 |
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#define | AFEC_LCDR_CHNB_Msk (0xfu << AFEC_LCDR_CHNB_Pos) |
| | (AFEC_LCDR) Channel Number
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#define | AFEC_IER_EOC0 (0x1u << 0) |
| | (AFEC_IER) End of Conversion Interrupt Enable 0
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#define | AFEC_IER_EOC1 (0x1u << 1) |
| | (AFEC_IER) End of Conversion Interrupt Enable 1
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#define | AFEC_IER_EOC2 (0x1u << 2) |
| | (AFEC_IER) End of Conversion Interrupt Enable 2
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#define | AFEC_IER_EOC3 (0x1u << 3) |
| | (AFEC_IER) End of Conversion Interrupt Enable 3
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#define | AFEC_IER_EOC4 (0x1u << 4) |
| | (AFEC_IER) End of Conversion Interrupt Enable 4
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#define | AFEC_IER_EOC5 (0x1u << 5) |
| | (AFEC_IER) End of Conversion Interrupt Enable 5
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#define | AFEC_IER_EOC6 (0x1u << 6) |
| | (AFEC_IER) End of Conversion Interrupt Enable 6
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#define | AFEC_IER_EOC7 (0x1u << 7) |
| | (AFEC_IER) End of Conversion Interrupt Enable 7
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#define | AFEC_IER_EOC8 (0x1u << 8) |
| | (AFEC_IER) End of Conversion Interrupt Enable 8
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#define | AFEC_IER_EOC9 (0x1u << 9) |
| | (AFEC_IER) End of Conversion Interrupt Enable 9
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#define | AFEC_IER_EOC10 (0x1u << 10) |
| | (AFEC_IER) End of Conversion Interrupt Enable 10
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#define | AFEC_IER_EOC11 (0x1u << 11) |
| | (AFEC_IER) End of Conversion Interrupt Enable 11
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#define | AFEC_IER_DRDY (0x1u << 24) |
| | (AFEC_IER) Data Ready Interrupt Enable
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#define | AFEC_IER_GOVRE (0x1u << 25) |
| | (AFEC_IER) General Overrun Error Interrupt Enable
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#define | AFEC_IER_COMPE (0x1u << 26) |
| | (AFEC_IER) Comparison Event Interrupt Enable
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#define | AFEC_IER_TEMPCHG (0x1u << 30) |
| | (AFEC_IER) Temperature Change Interrupt Enable
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#define | AFEC_IDR_EOC0 (0x1u << 0) |
| | (AFEC_IDR) End of Conversion Interrupt Disable 0
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#define | AFEC_IDR_EOC1 (0x1u << 1) |
| | (AFEC_IDR) End of Conversion Interrupt Disable 1
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#define | AFEC_IDR_EOC2 (0x1u << 2) |
| | (AFEC_IDR) End of Conversion Interrupt Disable 2
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#define | AFEC_IDR_EOC3 (0x1u << 3) |
| | (AFEC_IDR) End of Conversion Interrupt Disable 3
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#define | AFEC_IDR_EOC4 (0x1u << 4) |
| | (AFEC_IDR) End of Conversion Interrupt Disable 4
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#define | AFEC_IDR_EOC5 (0x1u << 5) |
| | (AFEC_IDR) End of Conversion Interrupt Disable 5
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#define | AFEC_IDR_EOC6 (0x1u << 6) |
| | (AFEC_IDR) End of Conversion Interrupt Disable 6
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#define | AFEC_IDR_EOC7 (0x1u << 7) |
| | (AFEC_IDR) End of Conversion Interrupt Disable 7
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#define | AFEC_IDR_EOC8 (0x1u << 8) |
| | (AFEC_IDR) End of Conversion Interrupt Disable 8
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#define | AFEC_IDR_EOC9 (0x1u << 9) |
| | (AFEC_IDR) End of Conversion Interrupt Disable 9
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#define | AFEC_IDR_EOC10 (0x1u << 10) |
| | (AFEC_IDR) End of Conversion Interrupt Disable 10
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#define | AFEC_IDR_EOC11 (0x1u << 11) |
| | (AFEC_IDR) End of Conversion Interrupt Disable 11
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#define | AFEC_IDR_DRDY (0x1u << 24) |
| | (AFEC_IDR) Data Ready Interrupt Disable
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#define | AFEC_IDR_GOVRE (0x1u << 25) |
| | (AFEC_IDR) General Overrun Error Interrupt Disable
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#define | AFEC_IDR_COMPE (0x1u << 26) |
| | (AFEC_IDR) Comparison Event Interrupt Disable
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#define | AFEC_IDR_TEMPCHG (0x1u << 30) |
| | (AFEC_IDR) Temperature Change Interrupt Disable
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#define | AFEC_IMR_EOC0 (0x1u << 0) |
| | (AFEC_IMR) End of Conversion Interrupt Mask 0
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#define | AFEC_IMR_EOC1 (0x1u << 1) |
| | (AFEC_IMR) End of Conversion Interrupt Mask 1
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#define | AFEC_IMR_EOC2 (0x1u << 2) |
| | (AFEC_IMR) End of Conversion Interrupt Mask 2
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#define | AFEC_IMR_EOC3 (0x1u << 3) |
| | (AFEC_IMR) End of Conversion Interrupt Mask 3
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#define | AFEC_IMR_EOC4 (0x1u << 4) |
| | (AFEC_IMR) End of Conversion Interrupt Mask 4
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#define | AFEC_IMR_EOC5 (0x1u << 5) |
| | (AFEC_IMR) End of Conversion Interrupt Mask 5
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#define | AFEC_IMR_EOC6 (0x1u << 6) |
| | (AFEC_IMR) End of Conversion Interrupt Mask 6
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#define | AFEC_IMR_EOC7 (0x1u << 7) |
| | (AFEC_IMR) End of Conversion Interrupt Mask 7
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#define | AFEC_IMR_EOC8 (0x1u << 8) |
| | (AFEC_IMR) End of Conversion Interrupt Mask 8
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#define | AFEC_IMR_EOC9 (0x1u << 9) |
| | (AFEC_IMR) End of Conversion Interrupt Mask 9
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#define | AFEC_IMR_EOC10 (0x1u << 10) |
| | (AFEC_IMR) End of Conversion Interrupt Mask 10
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#define | AFEC_IMR_EOC11 (0x1u << 11) |
| | (AFEC_IMR) End of Conversion Interrupt Mask 11
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#define | AFEC_IMR_DRDY (0x1u << 24) |
| | (AFEC_IMR) Data Ready Interrupt Mask
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#define | AFEC_IMR_GOVRE (0x1u << 25) |
| | (AFEC_IMR) General Overrun Error Interrupt Mask
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#define | AFEC_IMR_COMPE (0x1u << 26) |
| | (AFEC_IMR) Comparison Event Interrupt Mask
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#define | AFEC_IMR_TEMPCHG (0x1u << 30) |
| | (AFEC_IMR) Temperature Change Interrupt Mask
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#define | AFEC_ISR_EOC0 (0x1u << 0) |
| | (AFEC_ISR) End of Conversion 0 (cleared by reading AFEC_CDRx)
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#define | AFEC_ISR_EOC1 (0x1u << 1) |
| | (AFEC_ISR) End of Conversion 1 (cleared by reading AFEC_CDRx)
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#define | AFEC_ISR_EOC2 (0x1u << 2) |
| | (AFEC_ISR) End of Conversion 2 (cleared by reading AFEC_CDRx)
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#define | AFEC_ISR_EOC3 (0x1u << 3) |
| | (AFEC_ISR) End of Conversion 3 (cleared by reading AFEC_CDRx)
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#define | AFEC_ISR_EOC4 (0x1u << 4) |
| | (AFEC_ISR) End of Conversion 4 (cleared by reading AFEC_CDRx)
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#define | AFEC_ISR_EOC5 (0x1u << 5) |
| | (AFEC_ISR) End of Conversion 5 (cleared by reading AFEC_CDRx)
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#define | AFEC_ISR_EOC6 (0x1u << 6) |
| | (AFEC_ISR) End of Conversion 6 (cleared by reading AFEC_CDRx)
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#define | AFEC_ISR_EOC7 (0x1u << 7) |
| | (AFEC_ISR) End of Conversion 7 (cleared by reading AFEC_CDRx)
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#define | AFEC_ISR_EOC8 (0x1u << 8) |
| | (AFEC_ISR) End of Conversion 8 (cleared by reading AFEC_CDRx)
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#define | AFEC_ISR_EOC9 (0x1u << 9) |
| | (AFEC_ISR) End of Conversion 9 (cleared by reading AFEC_CDRx)
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#define | AFEC_ISR_EOC10 (0x1u << 10) |
| | (AFEC_ISR) End of Conversion 10 (cleared by reading AFEC_CDRx)
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#define | AFEC_ISR_EOC11 (0x1u << 11) |
| | (AFEC_ISR) End of Conversion 11 (cleared by reading AFEC_CDRx)
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#define | AFEC_ISR_DRDY (0x1u << 24) |
| | (AFEC_ISR) Data Ready (cleared by reading AFEC_LCDR)
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#define | AFEC_ISR_GOVRE (0x1u << 25) |
| | (AFEC_ISR) General Overrun Error (cleared by reading AFEC_ISR)
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#define | AFEC_ISR_COMPE (0x1u << 26) |
| | (AFEC_ISR) Comparison Error (cleared by reading AFEC_ISR)
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#define | AFEC_ISR_TEMPCHG (0x1u << 30) |
| | (AFEC_ISR) Temperature Change (cleared on read)
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#define | AFEC_OVER_OVRE0 (0x1u << 0) |
| | (AFEC_OVER) Overrun Error 0
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#define | AFEC_OVER_OVRE1 (0x1u << 1) |
| | (AFEC_OVER) Overrun Error 1
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#define | AFEC_OVER_OVRE2 (0x1u << 2) |
| | (AFEC_OVER) Overrun Error 2
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#define | AFEC_OVER_OVRE3 (0x1u << 3) |
| | (AFEC_OVER) Overrun Error 3
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#define | AFEC_OVER_OVRE4 (0x1u << 4) |
| | (AFEC_OVER) Overrun Error 4
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#define | AFEC_OVER_OVRE5 (0x1u << 5) |
| | (AFEC_OVER) Overrun Error 5
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#define | AFEC_OVER_OVRE6 (0x1u << 6) |
| | (AFEC_OVER) Overrun Error 6
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#define | AFEC_OVER_OVRE7 (0x1u << 7) |
| | (AFEC_OVER) Overrun Error 7
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#define | AFEC_OVER_OVRE8 (0x1u << 8) |
| | (AFEC_OVER) Overrun Error 8
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#define | AFEC_OVER_OVRE9 (0x1u << 9) |
| | (AFEC_OVER) Overrun Error 9
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#define | AFEC_OVER_OVRE10 (0x1u << 10) |
| | (AFEC_OVER) Overrun Error 10
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#define | AFEC_OVER_OVRE11 (0x1u << 11) |
| | (AFEC_OVER) Overrun Error 11
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#define | AFEC_CWR_LOWTHRES_Pos 0 |
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#define | AFEC_CWR_LOWTHRES_Msk (0xffffu << AFEC_CWR_LOWTHRES_Pos) |
| | (AFEC_CWR) Low Threshold
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#define | AFEC_CWR_LOWTHRES(value) ((AFEC_CWR_LOWTHRES_Msk & ((value) << AFEC_CWR_LOWTHRES_Pos))) |
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#define | AFEC_CWR_HIGHTHRES_Pos 16 |
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#define | AFEC_CWR_HIGHTHRES_Msk (0xffffu << AFEC_CWR_HIGHTHRES_Pos) |
| | (AFEC_CWR) High Threshold
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#define | AFEC_CWR_HIGHTHRES(value) ((AFEC_CWR_HIGHTHRES_Msk & ((value) << AFEC_CWR_HIGHTHRES_Pos))) |
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#define | AFEC_CGR_GAIN0_Pos 0 |
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#define | AFEC_CGR_GAIN0_Msk (0x3u << AFEC_CGR_GAIN0_Pos) |
| | (AFEC_CGR) Gain for Channel 0
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#define | AFEC_CGR_GAIN0(value) ((AFEC_CGR_GAIN0_Msk & ((value) << AFEC_CGR_GAIN0_Pos))) |
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#define | AFEC_CGR_GAIN1_Pos 2 |
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#define | AFEC_CGR_GAIN1_Msk (0x3u << AFEC_CGR_GAIN1_Pos) |
| | (AFEC_CGR) Gain for Channel 1
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#define | AFEC_CGR_GAIN1(value) ((AFEC_CGR_GAIN1_Msk & ((value) << AFEC_CGR_GAIN1_Pos))) |
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#define | AFEC_CGR_GAIN2_Pos 4 |
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#define | AFEC_CGR_GAIN2_Msk (0x3u << AFEC_CGR_GAIN2_Pos) |
| | (AFEC_CGR) Gain for Channel 2
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#define | AFEC_CGR_GAIN2(value) ((AFEC_CGR_GAIN2_Msk & ((value) << AFEC_CGR_GAIN2_Pos))) |
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#define | AFEC_CGR_GAIN3_Pos 6 |
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#define | AFEC_CGR_GAIN3_Msk (0x3u << AFEC_CGR_GAIN3_Pos) |
| | (AFEC_CGR) Gain for Channel 3
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#define | AFEC_CGR_GAIN3(value) ((AFEC_CGR_GAIN3_Msk & ((value) << AFEC_CGR_GAIN3_Pos))) |
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#define | AFEC_CGR_GAIN4_Pos 8 |
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#define | AFEC_CGR_GAIN4_Msk (0x3u << AFEC_CGR_GAIN4_Pos) |
| | (AFEC_CGR) Gain for Channel 4
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#define | AFEC_CGR_GAIN4(value) ((AFEC_CGR_GAIN4_Msk & ((value) << AFEC_CGR_GAIN4_Pos))) |
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#define | AFEC_CGR_GAIN5_Pos 10 |
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#define | AFEC_CGR_GAIN5_Msk (0x3u << AFEC_CGR_GAIN5_Pos) |
| | (AFEC_CGR) Gain for Channel 5
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#define | AFEC_CGR_GAIN5(value) ((AFEC_CGR_GAIN5_Msk & ((value) << AFEC_CGR_GAIN5_Pos))) |
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#define | AFEC_CGR_GAIN6_Pos 12 |
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#define | AFEC_CGR_GAIN6_Msk (0x3u << AFEC_CGR_GAIN6_Pos) |
| | (AFEC_CGR) Gain for Channel 6
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#define | AFEC_CGR_GAIN6(value) ((AFEC_CGR_GAIN6_Msk & ((value) << AFEC_CGR_GAIN6_Pos))) |
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#define | AFEC_CGR_GAIN7_Pos 14 |
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#define | AFEC_CGR_GAIN7_Msk (0x3u << AFEC_CGR_GAIN7_Pos) |
| | (AFEC_CGR) Gain for Channel 7
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#define | AFEC_CGR_GAIN7(value) ((AFEC_CGR_GAIN7_Msk & ((value) << AFEC_CGR_GAIN7_Pos))) |
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#define | AFEC_CGR_GAIN8_Pos 16 |
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#define | AFEC_CGR_GAIN8_Msk (0x3u << AFEC_CGR_GAIN8_Pos) |
| | (AFEC_CGR) Gain for Channel 8
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#define | AFEC_CGR_GAIN8(value) ((AFEC_CGR_GAIN8_Msk & ((value) << AFEC_CGR_GAIN8_Pos))) |
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#define | AFEC_CGR_GAIN9_Pos 18 |
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#define | AFEC_CGR_GAIN9_Msk (0x3u << AFEC_CGR_GAIN9_Pos) |
| | (AFEC_CGR) Gain for Channel 9
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#define | AFEC_CGR_GAIN9(value) ((AFEC_CGR_GAIN9_Msk & ((value) << AFEC_CGR_GAIN9_Pos))) |
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#define | AFEC_CGR_GAIN10_Pos 20 |
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#define | AFEC_CGR_GAIN10_Msk (0x3u << AFEC_CGR_GAIN10_Pos) |
| | (AFEC_CGR) Gain for Channel 10
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#define | AFEC_CGR_GAIN10(value) ((AFEC_CGR_GAIN10_Msk & ((value) << AFEC_CGR_GAIN10_Pos))) |
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#define | AFEC_CGR_GAIN11_Pos 22 |
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#define | AFEC_CGR_GAIN11_Msk (0x3u << AFEC_CGR_GAIN11_Pos) |
| | (AFEC_CGR) Gain for Channel 11
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#define | AFEC_CGR_GAIN11(value) ((AFEC_CGR_GAIN11_Msk & ((value) << AFEC_CGR_GAIN11_Pos))) |
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#define | AFEC_DIFFR_DIFF0 (0x1u << 0) |
| | (AFEC_DIFFR) Differential inputs for channel 0
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#define | AFEC_DIFFR_DIFF1 (0x1u << 1) |
| | (AFEC_DIFFR) Differential inputs for channel 1
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#define | AFEC_DIFFR_DIFF2 (0x1u << 2) |
| | (AFEC_DIFFR) Differential inputs for channel 2
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#define | AFEC_DIFFR_DIFF3 (0x1u << 3) |
| | (AFEC_DIFFR) Differential inputs for channel 3
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#define | AFEC_DIFFR_DIFF4 (0x1u << 4) |
| | (AFEC_DIFFR) Differential inputs for channel 4
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#define | AFEC_DIFFR_DIFF5 (0x1u << 5) |
| | (AFEC_DIFFR) Differential inputs for channel 5
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#define | AFEC_DIFFR_DIFF6 (0x1u << 6) |
| | (AFEC_DIFFR) Differential inputs for channel 6
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#define | AFEC_DIFFR_DIFF7 (0x1u << 7) |
| | (AFEC_DIFFR) Differential inputs for channel 7
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#define | AFEC_DIFFR_DIFF8 (0x1u << 8) |
| | (AFEC_DIFFR) Differential inputs for channel 8
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#define | AFEC_DIFFR_DIFF9 (0x1u << 9) |
| | (AFEC_DIFFR) Differential inputs for channel 9
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#define | AFEC_DIFFR_DIFF10 (0x1u << 10) |
| | (AFEC_DIFFR) Differential inputs for channel 10
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#define | AFEC_DIFFR_DIFF11 (0x1u << 11) |
| | (AFEC_DIFFR) Differential inputs for channel 11
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#define | AFEC_CSELR_CSEL_Pos 0 |
| |
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#define | AFEC_CSELR_CSEL_Msk (0xfu << AFEC_CSELR_CSEL_Pos) |
| | (AFEC_CSELR) Channel Selection
|
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#define | AFEC_CSELR_CSEL(value) ((AFEC_CSELR_CSEL_Msk & ((value) << AFEC_CSELR_CSEL_Pos))) |
| |
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#define | AFEC_CDR_DATA_Pos 0 |
| |
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#define | AFEC_CDR_DATA_Msk (0xffffu << AFEC_CDR_DATA_Pos) |
| | (AFEC_CDR) Converted Data
|
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#define | AFEC_COCR_AOFF_Pos 0 |
| |
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#define | AFEC_COCR_AOFF_Msk (0x3ffu << AFEC_COCR_AOFF_Pos) |
| | (AFEC_COCR) Analog Offset
|
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#define | AFEC_COCR_AOFF(value) ((AFEC_COCR_AOFF_Msk & ((value) << AFEC_COCR_AOFF_Pos))) |
| |
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#define | AFEC_TEMPMR_RTCT (0x1u << 0) |
| | (AFEC_TEMPMR) Temperature Sensor RTC Trigger Mode
|
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#define | AFEC_TEMPMR_TEMPCMPMOD_Pos 4 |
| |
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#define | AFEC_TEMPMR_TEMPCMPMOD_Msk (0x3u << AFEC_TEMPMR_TEMPCMPMOD_Pos) |
| | (AFEC_TEMPMR) Temperature Comparison Mode
|
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#define | AFEC_TEMPMR_TEMPCMPMOD(value) ((AFEC_TEMPMR_TEMPCMPMOD_Msk & ((value) << AFEC_TEMPMR_TEMPCMPMOD_Pos))) |
| |
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#define | AFEC_TEMPMR_TEMPCMPMOD_LOW (0x0u << 4) |
| | (AFEC_TEMPMR) Generates an event when the converted data is lower than the low threshold of the window.
|
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#define | AFEC_TEMPMR_TEMPCMPMOD_HIGH (0x1u << 4) |
| | (AFEC_TEMPMR) Generates an event when the converted data is higher than the high threshold of the window.
|
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#define | AFEC_TEMPMR_TEMPCMPMOD_IN (0x2u << 4) |
| | (AFEC_TEMPMR) Generates an event when the converted data is in the comparison window.
|
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#define | AFEC_TEMPMR_TEMPCMPMOD_OUT (0x3u << 4) |
| | (AFEC_TEMPMR) Generates an event when the converted data is out of the comparison window.
|
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#define | AFEC_TEMPCWR_TLOWTHRES_Pos 0 |
| |
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#define | AFEC_TEMPCWR_TLOWTHRES_Msk (0xffffu << AFEC_TEMPCWR_TLOWTHRES_Pos) |
| | (AFEC_TEMPCWR) Temperature Low Threshold
|
| |
|
#define | AFEC_TEMPCWR_TLOWTHRES(value) ((AFEC_TEMPCWR_TLOWTHRES_Msk & ((value) << AFEC_TEMPCWR_TLOWTHRES_Pos))) |
| |
|
#define | AFEC_TEMPCWR_THIGHTHRES_Pos 16 |
| |
|
#define | AFEC_TEMPCWR_THIGHTHRES_Msk (0xffffu << AFEC_TEMPCWR_THIGHTHRES_Pos) |
| | (AFEC_TEMPCWR) Temperature High Threshold
|
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#define | AFEC_TEMPCWR_THIGHTHRES(value) ((AFEC_TEMPCWR_THIGHTHRES_Msk & ((value) << AFEC_TEMPCWR_THIGHTHRES_Pos))) |
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#define | AFEC_ACR_PGA0EN (0x1u << 2) |
| | (AFEC_ACR) PGA0 Enable
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#define | AFEC_ACR_PGA1EN (0x1u << 3) |
| | (AFEC_ACR) PGA1 Enable
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#define | AFEC_ACR_IBCTL_Pos 8 |
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#define | AFEC_ACR_IBCTL_Msk (0x3u << AFEC_ACR_IBCTL_Pos) |
| | (AFEC_ACR) AFE Bias Current Control
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#define | AFEC_ACR_IBCTL(value) ((AFEC_ACR_IBCTL_Msk & ((value) << AFEC_ACR_IBCTL_Pos))) |
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#define | AFEC_SHMR_DUAL0 (0x1u << 0) |
| | (AFEC_SHMR) Dual Sample & Hold for channel 0
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#define | AFEC_SHMR_DUAL1 (0x1u << 1) |
| | (AFEC_SHMR) Dual Sample & Hold for channel 1
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#define | AFEC_SHMR_DUAL2 (0x1u << 2) |
| | (AFEC_SHMR) Dual Sample & Hold for channel 2
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#define | AFEC_SHMR_DUAL3 (0x1u << 3) |
| | (AFEC_SHMR) Dual Sample & Hold for channel 3
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#define | AFEC_SHMR_DUAL4 (0x1u << 4) |
| | (AFEC_SHMR) Dual Sample & Hold for channel 4
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#define | AFEC_SHMR_DUAL5 (0x1u << 5) |
| | (AFEC_SHMR) Dual Sample & Hold for channel 5
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#define | AFEC_SHMR_DUAL6 (0x1u << 6) |
| | (AFEC_SHMR) Dual Sample & Hold for channel 6
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#define | AFEC_SHMR_DUAL7 (0x1u << 7) |
| | (AFEC_SHMR) Dual Sample & Hold for channel 7
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#define | AFEC_SHMR_DUAL8 (0x1u << 8) |
| | (AFEC_SHMR) Dual Sample & Hold for channel 8
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#define | AFEC_SHMR_DUAL9 (0x1u << 9) |
| | (AFEC_SHMR) Dual Sample & Hold for channel 9
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#define | AFEC_SHMR_DUAL10 (0x1u << 10) |
| | (AFEC_SHMR) Dual Sample & Hold for channel 10
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#define | AFEC_SHMR_DUAL11 (0x1u << 11) |
| | (AFEC_SHMR) Dual Sample & Hold for channel 11
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#define | AFEC_COSR_CSEL (0x1u << 0) |
| | (AFEC_COSR) Sample & Hold unit Correction Select
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#define | AFEC_CVR_OFFSETCORR_Pos 0 |
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#define | AFEC_CVR_OFFSETCORR_Msk (0xffffu << AFEC_CVR_OFFSETCORR_Pos) |
| | (AFEC_CVR) Offset Correction
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#define | AFEC_CVR_OFFSETCORR(value) ((AFEC_CVR_OFFSETCORR_Msk & ((value) << AFEC_CVR_OFFSETCORR_Pos))) |
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#define | AFEC_CVR_GAINCORR_Pos 16 |
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#define | AFEC_CVR_GAINCORR_Msk (0xffffu << AFEC_CVR_GAINCORR_Pos) |
| | (AFEC_CVR) Gain Correction
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#define | AFEC_CVR_GAINCORR(value) ((AFEC_CVR_GAINCORR_Msk & ((value) << AFEC_CVR_GAINCORR_Pos))) |
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#define | AFEC_CECR_ECORR0 (0x1u << 0) |
| | (AFEC_CECR) Error Correction Enable for channel 0
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#define | AFEC_CECR_ECORR1 (0x1u << 1) |
| | (AFEC_CECR) Error Correction Enable for channel 1
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#define | AFEC_CECR_ECORR2 (0x1u << 2) |
| | (AFEC_CECR) Error Correction Enable for channel 2
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#define | AFEC_CECR_ECORR3 (0x1u << 3) |
| | (AFEC_CECR) Error Correction Enable for channel 3
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#define | AFEC_CECR_ECORR4 (0x1u << 4) |
| | (AFEC_CECR) Error Correction Enable for channel 4
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#define | AFEC_CECR_ECORR5 (0x1u << 5) |
| | (AFEC_CECR) Error Correction Enable for channel 5
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#define | AFEC_CECR_ECORR6 (0x1u << 6) |
| | (AFEC_CECR) Error Correction Enable for channel 6
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#define | AFEC_CECR_ECORR7 (0x1u << 7) |
| | (AFEC_CECR) Error Correction Enable for channel 7
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#define | AFEC_CECR_ECORR8 (0x1u << 8) |
| | (AFEC_CECR) Error Correction Enable for channel 8
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#define | AFEC_CECR_ECORR9 (0x1u << 9) |
| | (AFEC_CECR) Error Correction Enable for channel 9
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#define | AFEC_CECR_ECORR10 (0x1u << 10) |
| | (AFEC_CECR) Error Correction Enable for channel 10
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#define | AFEC_CECR_ECORR11 (0x1u << 11) |
| | (AFEC_CECR) Error Correction Enable for channel 11
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#define | AFEC_WPMR_WPEN (0x1u << 0) |
| | (AFEC_WPMR) Write Protection Enable
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#define | AFEC_WPMR_WPKEY_Pos 8 |
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#define | AFEC_WPMR_WPKEY_Msk (0xffffffu << AFEC_WPMR_WPKEY_Pos) |
| | (AFEC_WPMR) Write Protect KEY
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#define | AFEC_WPMR_WPKEY(value) ((AFEC_WPMR_WPKEY_Msk & ((value) << AFEC_WPMR_WPKEY_Pos))) |
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#define | AFEC_WPMR_WPKEY_PASSWD (0x414443u << 8) |
| | (AFEC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
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#define | AFEC_WPSR_WPVS (0x1u << 0) |
| | (AFEC_WPSR) Write Protect Violation Status
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#define | AFEC_WPSR_WPVSRC_Pos 8 |
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#define | AFEC_WPSR_WPVSRC_Msk (0xffffu << AFEC_WPSR_WPVSRC_Pos) |
| | (AFEC_WPSR) Write Protect Violation Source
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1.8.13