RTEMS  5.0.0
Data Structures | Macros | Variables
Cache Support

Cache Functions and Defitions. More...

Data Structures

struct  L2CC
 L2CC Register Offsets. More...
 

Macros

#define CPU_DATA_CACHE_ALIGNMENT   ARM_CACHE_L1_CPU_DATA_ALIGNMENT
 Cache definitions and functions. More...
 
#define L2C_310_ID_RTL_MASK   0x3f
 
#define L2C_310_ID_PART_MASK   ( 0xf << 6 )
 
#define L2C_310_ID_PART_L210   ( 1 << 6 )
 
#define L2C_310_ID_PART_L310   ( 3 << 6 )
 
#define L2C_310_ID_IMPL_MASK   ( 0xff << 24 )
 
#define L2C_310_TYPE_DATA_BANKING_MASK   0x80000000
 1 if data banking implemented, 0 if not
 
#define L2C_310_TYPE_CTYPE_MASK   0x1E000000
 11xy, where: x=1 if pl310_LOCKDOWN_BY_MASTER is defined, otherwise 0
 
#define L2C_310_TYPE_CTYPE_SHIFT   25
 y=1 if pl310_LOCKDOWN_BY_LINE is defined, otherwise 0.
 
#define L2C_310_TYPE_HARVARD_MASK   0x01000000
 1 for Harvard architecture, 0 for unified architecture
 
#define L2C_310_TYPE_SIZE_D_WAYS_MASK   0x00700000
 Data cache way size = 2 Exp(value + 2) KB.
 
#define L2C_310_TYPE_SIZE_D_WAYS_SHIFT   20
 
#define L2C_310_TYPE_NUM_D_WAYS_MASK   0x00040000
 Assoziativity aka number of data ways = (value * 8) + 8.
 
#define L2C_310_TYPE_NUM_D_WAYS_SHIFT   18
 
#define L2C_310_TYPE_LENGTH_D_LINE_MASK   0x00003000
 Data cache line length 00 - 32.
 
#define L2C_310_TYPE_LENGTH_D_LINE_SHIFT   12
 
#define L2C_310_TYPE_LENGTH_D_LINE_VAL_32   0x0
 
#define L2C_310_TYPE_SIZE_I_WAYS_MASK   0x00000700
 Instruction cache way size = 2 Exp(value + 2) KB.
 
#define L2C_310_TYPE_SIZE_I_WAYS_SHIFT   8
 
#define L2C_310_TYPE_NUM_I_WAYS_MASK   0x00000040
 Assoziativity aka number of instruction ways = (value * 8) + 8.
 
#define L2C_310_TYPE_NUM_I_WAYS_SHIFT   6
 
#define L2C_310_TYPE_LENGTH_I_LINE_MASK   0x00000003
 Instruction cache line length 00 - 32.
 
#define L2C_310_TYPE_LENGTH_I_LINE_SHIFT   0
 
#define L2C_310_TYPE_LENGTH_I_LINE_VAL_32   0x0
 
#define L2C_310_CTRL_ENABLE   0x00000001
 Enables the L2CC.
 
#define L2C_310_CTRL_EXCL_CONFIG   (1 << 12)
 
#define L2C_310_AUX_EBRESPE_MASK   0x40000000
 Early BRESP Enable.
 
#define L2C_310_AUX_IPFE_MASK   0x20000000
 Instruction Prefetch Enable.
 
#define L2C_310_AUX_DPFE_MASK   0x10000000
 Data Prefetch Enable.
 
#define L2C_310_AUX_NSIC_MASK   0x08000000
 Non-secure interrupt access control.
 
#define L2C_310_AUX_NSLE_MASK   0x04000000
 Non-secure lockdown enable.
 
#define L2C_310_AUX_CRP_MASK   0x02000000
 Cache replacement policy.
 
#define L2C_310_AUX_FWE_MASK   0x01800000
 Force write allocate.
 
#define L2C_310_AUX_SAOE_MASK   0x00400000
 Shared attribute override enable.
 
#define L2C_310_AUX_PE_MASK   0x00200000
 Parity enable.
 
#define L2C_310_AUX_EMBE_MASK   0x00100000
 Event monitor bus enable.
 
#define L2C_310_AUX_WAY_SIZE_MASK   0x000E0000
 Way-size.
 
#define L2C_310_AUX_WAY_SIZE_SHIFT   17
 
#define L2C_310_AUX_ASSOC_MASK   0x00010000
 Way-size.
 
#define L2C_310_AUX_SAIE_MASK   0x00002000
 Shared attribute invalidate enable.
 
#define L2C_310_AUX_EXCL_CACHE_MASK   0x00001000
 Exclusive cache configuration.
 
#define L2C_310_AUX_SBDLE_MASK   0x00000800
 Store buffer device limitation Enable.
 
#define L2C_310_AUX_HPSODRE_MASK   0x00000400
 High Priority for SO and Dev Reads Enable.
 
#define L2C_310_AUX_FLZE_MASK   0x00000001
 Full line of zero enable.
 
#define L2C_310_AUX_REG_DEFAULT_MASK
 Enable all prefetching,. More...
 
#define L2C_310_AUX_REG_ZERO_MASK   0xFFF1FFFF
 
#define L2C_310_RAM_1_CYCLE_LAT_VAL   0x00000000
 1 cycle of latency, there is no additional latency fot tag RAM
 
#define L2C_310_RAM_2_CYCLE_LAT_VAL   0x00000001
 2 cycles of latency for tag RAM
 
#define L2C_310_RAM_3_CYCLE_LAT_VAL   0x00000002
 3 cycles of latency for tag RAM
 
#define L2C_310_RAM_4_CYCLE_LAT_VAL   0x00000003
 4 cycles of latency for tag RAM
 
#define L2C_310_RAM_5_CYCLE_LAT_VAL   0x00000004
 5 cycles of latency for tag RAM
 
#define L2C_310_RAM_6_CYCLE_LAT_VAL   0x00000005
 6 cycles of latency for tag RAM
 
#define L2C_310_RAM_7_CYCLE_LAT_VAL   0x00000006
 7 cycles of latency for tag RAM
 
#define L2C_310_RAM_8_CYCLE_LAT_VAL   0x00000007
 8 cycles of latency for tag RAM
 
#define L2C_310_RAM_SETUP_SHIFT   0x00000000
 Shift left setup latency values by this value.
 
#define L2C_310_RAM_READ_SHIFT   0x00000004
 Shift left read latency values by this value.
 
#define L2C_310_RAM_WRITE_SHIFT   0x00000008
 Shift left write latency values by this value.
 
#define L2C_310_RAM_SETUP_LAT_MASK   0x00000007
 Mask for RAM setup latency.
 
#define L2C_310_RAM_READ_LAT_MASK   0x00000070
 Mask for RAM read latency.
 
#define L2C_310_RAM_WRITE_LAT_MASK   0x00000700
 Mask for RAM read latency.
 
#define L2C_310_TAG_RAM_DEFAULT_LAT
 
#define L2C_310_DATA_RAM_DEFAULT_MASK
 Latency for data RAM. More...
 
#define L2C_310_ADDR_FILTER_VALID_MASK   0xFFF00000
 Address filtering valid bits.
 
#define L2C_310_ADDR_FILTER_ENABLE_MASK   0x00000001
 Address filtering enable bit.
 
#define L2C_310_DEBUG_SPIDEN_MASK   0x00000004
 Debug SPIDEN bit.
 
#define L2C_310_DEBUG_DWB_MASK   0x00000002
 Debug DWB bit, forces write through.
 
#define L2C_310_DEBUG_DCL_MASK   0x00000002
 Debug DCL bit, disables cache line fill.
 
#define L2C_310_PREFETCH_OFFSET_MASK   0x0000001F
 Prefetch offset.
 
#define L2C_310_ERRATA_IS_APPLICABLE_588369
 
#define CACHE_ARM_ERRATA_775420_HANDLER()
 

Variables

uint32_t L2CC::cache_id
 Cache ID.
 
uint32_t L2CC::cache_type
 Cache type.
 
uint8_t L2CC::reserved_8 [0x100 - 8]
 
uint32_t L2CC::ctrl
 
uint32_t L2CC::aux_ctrl
 Auxiliary control.
 
uint32_t L2CC::tag_ram_ctrl
 Latency for tag RAM.
 
uint32_t L2CC::data_ram_ctrl
 Latency for data RAM.
 
uint8_t L2CC::reserved_110 [0x200 - 0x110]
 
uint32_t L2CC::ev_ctrl
 Event counter control.
 
uint32_t L2CC::ev_cnt1_cfg
 Event counter 1 configuration.
 
uint32_t L2CC::ev_cnt0_cfg
 Event counter 0 configuration.
 
uint32_t L2CC::ev_cnt1
 Event counter 1 value.
 
uint32_t L2CC::ev_cnt0
 Event counter 0 value.
 
uint32_t L2CC::int_mask
 Interrupt enable mask.
 
uint32_t L2CC::int_mask_status
 Masked interrupt status (read-only)
 
uint32_t L2CC::int_raw_status
 Unmasked interrupt status.
 
uint32_t L2CC::int_clr
 Interrupt clear.
 
uint8_t L2CC::reserved_224 [0x730 - 0x224]
 
uint32_t L2CC::cache_sync
 Drain the STB.
 
uint8_t L2CC::reserved_734 [0x740 - 0x734]
 
uint32_t L2CC::dummy_cache_sync_reg
 ARM Errata 753970 for pl310-r3p0.
 
uint8_t L2CC::reserved_744 [0x770 - 0x744]
 
uint32_t L2CC::inv_pa
 Invalidate line by PA.
 
uint8_t L2CC::reserved_774 [0x77c - 0x774]
 
uint32_t L2CC::inv_way
 Invalidate by Way.
 
uint8_t L2CC::reserved_780 [0x7b0 - 0x780]
 
uint32_t L2CC::clean_pa
 Clean Line by PA.
 
uint8_t L2CC::reserved_7b4 [0x7b8 - 0x7b4]
 
uint32_t L2CC::clean_index
 Clean Line by Set/Way.
 
uint32_t L2CC::clean_way
 Clean by Way.
 
uint8_t L2CC::reserved_7c0 [0x7f0 - 0x7c0]
 
uint32_t L2CC::clean_inv_pa
 Clean and Invalidate Line by PA.
 
uint8_t L2CC::reserved_7f4 [0x7f8 - 0x7f4]
 
uint32_t L2CC::clean_inv_indx
 Clean and Invalidate Line by Set/Way.
 
uint32_t L2CC::clean_inv_way
 Clean and Invalidate by Way.
 
uint32_t L2CC::d_lockdown_0
 Data lock down 0.
 
uint32_t L2CC::i_lockdown_0
 Instruction lock down 0.
 
uint32_t L2CC::d_lockdown_1
 Data lock down 1.
 
uint32_t L2CC::i_lockdown_1
 Instruction lock down 1.
 
uint32_t L2CC::d_lockdown_2
 Data lock down 2.
 
uint32_t L2CC::i_lockdown_2
 Instruction lock down 2.
 
uint32_t L2CC::d_lockdown_3
 Data lock down 3.
 
uint32_t L2CC::i_lockdown_3
 Instruction lock down 3.
 
uint32_t L2CC::d_lockdown_4
 Data lock down 4.
 
uint32_t L2CC::i_lockdown_4
 Instruction lock down 4.
 
uint32_t L2CC::d_lockdown_5
 Data lock down 5.
 
uint32_t L2CC::i_lockdown_5
 Instruction lock down 5.
 
uint32_t L2CC::d_lockdown_6
 Data lock down 6.
 
uint32_t L2CC::i_lockdown_6
 Instruction lock down 6.
 
uint32_t L2CC::d_lockdown_7
 Data lock down 7.
 
uint32_t L2CC::i_lockdown_7
 Instruction lock down 7.
 
uint8_t L2CC::reserved_940 [0x950 - 0x940]
 
uint32_t L2CC::lock_line_en
 Lockdown by Line Enable.
 
uint32_t L2CC::unlock_way
 Cache lockdown by way.
 
uint8_t L2CC::reserved_958 [0xc00 - 0x958]
 
uint32_t L2CC::addr_filtering_start
 Address range redirect, part 1.
 
uint32_t L2CC::addr_filtering_end
 Address range redirect, part 2.
 
uint8_t L2CC::reserved_c08 [0xf40 - 0xc08]
 
uint32_t L2CC::debug_ctrl
 Debug control.
 
uint8_t L2CC::reserved_f44 [0xf60 - 0xf44]
 
uint32_t L2CC::prefetch_ctrl
 Purpose prefetch enables.
 
uint8_t L2CC::reserved_f64 [0xf80 - 0xf64]
 
uint32_t L2CC::power_ctrl
 Purpose power controls.
 
rtems_interrupt_lock l2c_310_lock
 

Interrupt bit masks

#define L2C_310_INT_DECERR_MASK   0x00000100
 DECERR from L3.
 
#define L2C_310_INT_SLVERR_MASK   0x00000080
 SLVERR from L3.
 
#define L2C_310_INT_ERRRD_MASK   0x00000040
 Error on L2 data RAM (Read)
 
#define L2C_310_INT_ERRRT_MASK   0x00000020
 Error on L2 tag RAM (Read)
 
#define L2C_310_INT_ERRWD_MASK   0x00000010
 Error on L2 data RAM (Write)
 
#define L2C_310_INT_ERRWT_MASK   0x00000008
 Error on L2 tag RAM (Write)
 
#define L2C_310_INT_PARRD_MASK   0x00000004
 Parity Error on L2 data RAM (Read)
 
#define L2C_310_INT_PARRT_MASK   0x00000002
 Parity Error on L2 tag RAM (Read)
 
#define L2C_310_INT_ECNTR_MASK   0x00000001
 Event Counter1/0 Overflow Increment.
 

Detailed Description

Cache Functions and Defitions.

Macro Definition Documentation

◆ CACHE_ARM_ERRATA_775420_HANDLER

#define CACHE_ARM_ERRATA_775420_HANDLER ( )
Value:
if( arm_errata_is_applicable_processor_errata_775420 ) { \
} \

◆ CPU_DATA_CACHE_ALIGNMENT

#define CPU_DATA_CACHE_ALIGNMENT   ARM_CACHE_L1_CPU_DATA_ALIGNMENT

Cache definitions and functions.

This file implements handling for the ARM L2C-310 cache controller

◆ L2C_310_AUX_REG_DEFAULT_MASK

#define L2C_310_AUX_REG_DEFAULT_MASK
Value:
( L2C_310_AUX_WAY_SIZE_MASK & ( 0x3 << L2C_310_AUX_WAY_SIZE_SHIFT ) ) \
| L2C_310_AUX_PE_MASK /* Prefetch enable */ \
| L2C_310_AUX_SAOE_MASK /* Shared attribute override enable */ \
| L2C_310_AUX_CRP_MASK /* Cache replacement policy */ \
| L2C_310_AUX_DPFE_MASK /* Data prefetch enable */ \
| L2C_310_AUX_IPFE_MASK /* Instruction prefetch enable */ \
| L2C_310_AUX_EBRESPE_MASK /* Early BRESP enable */
#define L2C_310_AUX_SAOE_MASK
Shared attribute override enable.
Definition: cache-l2c-310.c:180
#define L2C_310_AUX_IPFE_MASK
Instruction Prefetch Enable.
Definition: cache-l2c-310.c:162
#define L2C_310_AUX_EBRESPE_MASK
Early BRESP Enable.
Definition: cache-l2c-310.c:159
#define L2C_310_AUX_PE_MASK
Parity enable.
Definition: cache-l2c-310.c:183
#define L2C_310_AUX_CRP_MASK
Cache replacement policy.
Definition: cache-l2c-310.c:174
#define L2C_310_AUX_DPFE_MASK
Data Prefetch Enable.
Definition: cache-l2c-310.c:165
#define L2C_310_AUX_WAY_SIZE_MASK
Way-size.
Definition: cache-l2c-310.c:189

Enable all prefetching,.

◆ L2C_310_DATA_RAM_DEFAULT_MASK

#define L2C_310_DATA_RAM_DEFAULT_MASK
Value:
#define L2C_310_RAM_SETUP_SHIFT
Shift left setup latency values by this value.
Definition: cache-l2c-310.c:239
#define L2C_310_RAM_WRITE_SHIFT
Shift left write latency values by this value.
Definition: cache-l2c-310.c:243
#define L2C_310_RAM_2_CYCLE_LAT_VAL
2 cycles of latency for tag RAM
Definition: cache-l2c-310.c:225
#define L2C_310_RAM_3_CYCLE_LAT_VAL
3 cycles of latency for tag RAM
Definition: cache-l2c-310.c:227
#define L2C_310_RAM_READ_SHIFT
Shift left read latency values by this value.
Definition: cache-l2c-310.c:241

Latency for data RAM.

◆ L2C_310_TAG_RAM_DEFAULT_LAT

#define L2C_310_TAG_RAM_DEFAULT_LAT
Value:
#define L2C_310_RAM_SETUP_SHIFT
Shift left setup latency values by this value.
Definition: cache-l2c-310.c:239
#define L2C_310_RAM_WRITE_SHIFT
Shift left write latency values by this value.
Definition: cache-l2c-310.c:243
#define L2C_310_RAM_2_CYCLE_LAT_VAL
2 cycles of latency for tag RAM
Definition: cache-l2c-310.c:225
#define L2C_310_RAM_READ_SHIFT
Shift left read latency values by this value.
Definition: cache-l2c-310.c:241

Variable Documentation

◆ l2c_310_lock

rtems_interrupt_lock l2c_310_lock
Initial value:
"L2-310 cache controller"
)
#define RTEMS_INTERRUPT_LOCK_INITIALIZER(_name)
Initializer for static initialization of interrupt locks.
Definition: intr.h:253