RTEMS  5.0.0
Typedefs | Enumerations | Functions

Typedefs

typedef enum ALT_CLK_SAFE_DOMAIN_e ALT_CLK_SAFE_DOMAIN_t
 

Enumerations

enum  ALT_CLK_SAFE_DOMAIN_e { ALT_CLK_DOMAIN_NORMAL, ALT_CLK_DOMAIN_DEBUG }
 

Functions

ALT_STATUS_CODE alt_clk_safe_mode_clear (void)
 
bool alt_clk_is_in_safe_mode (ALT_CLK_SAFE_DOMAIN_t clk_domain)
 

Detailed Description

When safe mode is enabled, clocks in the HPS are directly generated from the osc1_clk clock. Safe mode is enabled by the assertion of a safe mode request from the reset manager or by a cold reset. Assertion of the safe mode request from the reset manager sets the safe mode bit in the clock manager control register. No other control register bits are affected by the safe mode request from the reset manager.

While in safe mode, clock manager register settings which control clock behavior are not changed. However, the output of the registers which control the clock manager state are forced to the safe mode values such that the following conditions occur:

A write by software is the only way to clear the safe mode bit. All registers and clocks need to be configured correctly and all software-managed clocks need to be gated off before clearing safe mode. Software can then gate clocks on as required.

On cold reset, all clocks are put in safe mode.

On warm reset, safe mode is optionally and independently applied to debug clocks and normal (i.e.non-debug) clocks based on clock manager register settings. The default response for warm reset is to put all clocks in safe mode.

The APIs in this group provide control of the Clock Manager safe mode warm reset response behavior.

Typedef Documentation

◆ ALT_CLK_SAFE_DOMAIN_t

This type definition enumerates the safe mode clock domains under control of the Clock Manager.

Enumeration Type Documentation

◆ ALT_CLK_SAFE_DOMAIN_e

This type definition enumerates the safe mode clock domains under control of the Clock Manager.

Enumerator
ALT_CLK_DOMAIN_NORMAL 

This enumeration literal specifies the normal safe mode domain. The normal domain consists of all clocks except debug clocks.

ALT_CLK_DOMAIN_DEBUG 

This enumeration literal specifies the debug safe mode domain. The debug domain consists of all debug clocks.

Function Documentation

◆ alt_clk_is_in_safe_mode()

bool alt_clk_is_in_safe_mode ( ALT_CLK_SAFE_DOMAIN_t  clk_domain)

Return whether the specified safe mode clock domain is in safe mode or not.

Parameters
clk_domainThe safe mode clock domain to check whether in safe mode or not.
Return values
TRUEThe safe mode clock domain is in safe mode.
FALSEThe safe mode clock domain is not in safe mode.

◆ alt_clk_safe_mode_clear()

ALT_STATUS_CODE alt_clk_safe_mode_clear ( void  )

Clear the safe mode status of the Clock Manager following a reset.

NOTE: Safe mode should only be cleared once clocks have been correctly configured.

Return values
ALT_E_SUCCESSThe operation was succesful.
ALT_E_ERRORThe operation failed.