This functional group provides gating control of selected clock signals.
When a clock is enabled, then its clock signal propogates to its respective clocked IP block(s). When a clock is disabled, then its clock signal is prevented from propogating to its respective clocked IP block(s).
The following clocks may be gated:
- Main PLL Group
- l4_main_clk
- l3_mp_clk
- l4_mp_clk
- l4_sp_clk
- dbg_at_clk
- dbg_clk
- dbg_trace_clk
- dbg_timer_clk
- cfg_clk
- s2f_user0_clk
- SDRAM PLL Group
- ddr_dqs_clk
- ddr_2x_clk
- ddr_dq_clk
- s2f_user2_clk
- Peripheral PLL Group
- emac0_clk
- emac1_clk
- usb_mp_clk
- spi_m_clk
- can0_clk
- can1_clk
- gpio_db_clk
- s2f_user1_clk
- sdmmc_clk
- nand_clk
- nand_x_clk
- qspi_clk
◆ alt_clk_clock_disable()
Disable the specified clock. Once the clock is disabled, its clock signal does not propogate to its clocked elements.
- Parameters
-
- Return values
-
ALT_E_SUCCESS | The operation was succesful. |
ALT_E_ERROR | The operation failed. |
ALT_E_BAD_ARG | The clk argument designates a non gated clock value. |
◆ alt_clk_clock_enable()
Enable the specified clock. Once the clock is enabled, its clock signal propogates to its elements.
- Parameters
-
- Return values
-
ALT_E_SUCCESS | The operation was succesful. |
ALT_E_ERROR | The operation failed. |
ALT_E_BAD_ARG | The clk argument designates a non gated clock value. |
◆ alt_clk_is_enabled()
Return whether the specified clock is enabled or not.
- Parameters
-
clk | The clock to check whether enabled or not. |
- Return values
-
ALT_E_TRUE | The clock is enabled. |
ALT_E_FALSE | The clock is not enabled. |
ALT_E_BAD_ARG | The clk argument designates a non gated clock value. |