Typedefs
typedef enum ALT_ADDR_SPACE_MPU_ATTR_e	ALT_ADDR_SPACE_MPU_ATTR_t

typedef enum ALT_ADDR_SPACE_NONMPU_ATTR_e	ALT_ADDR_SPACE_NONMPU_ATTR_t

typedef enum ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_e	ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_t

typedef enum ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_e	ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_t

Enumerations
enum	ALT_ADDR_SPACE_MPU_ATTR_e { ALT_ADDR_SPACE_MPU_ZERO_AT_BOOTROM, ALT_ADDR_SPACE_MPU_ZERO_AT_OCRAM }

enum	ALT_ADDR_SPACE_NONMPU_ATTR_e { ALT_ADDR_SPACE_NONMPU_ZERO_AT_SDRAM, ALT_ADDR_SPACE_NONMPU_ZERO_AT_OCRAM }

enum	ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_e { ALT_ADDR_SPACE_H2F_INACCESSIBLE, ALT_ADDR_SPACE_H2F_ACCESSIBLE }

enum	ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_e { ALT_ADDR_SPACE_LWH2F_INACCESSIBLE, ALT_ADDR_SPACE_LWH2F_ACCESSIBLE }

Functions
ALT_STATUS_CODE	alt_addr_space_remap (ALT_ADDR_SPACE_MPU_ATTR_t mpu_attr, ALT_ADDR_SPACE_NONMPU_ATTR_t nonmpu_attr, ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_t h2f_attr, ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_t lwh2f_attr)

ALT_STATUS_CODE	alt_mpu_addr_space_remap_0_to_sdram (void)

Detailed Description

This group API provides functions to map and remap selected address ranges into the accessible (visible) views of the MPU and non MPU address spaces.

Caveats

NOTE: Caution should be observed when remapping address 0 to different memory. The code performing the remapping operation should not be executing in the address range being remapped to different memory.

For example, if address 0 is presently mapped to OCRAM and the code is preparing to remap address 0 to SDRAM, then the code must not be executing in the range 0 to 64 KB as this address space is about to be remapped to different memory. If the code performing the remap operation is executing from OCRAM then it needs to be executing from its permanently mapped OCRAM address range in upper memory (i.e. ALT_OCRAM_LB_ADDR to ALT_OCRAM_UB_ADDR).

NOTE: The MPU address space view is controlled by two disparate hardware control interfaces: the L3 remap register and the L2 cache address filtering registers. To complicate matters, the L3 remap register is write-only which means not only that current remap register state cannot be read but also that a read-modify-write operation cannot be performed on the register.

This should not present a problem in most use case scenarios except for the case where a current MPU address space mapping of 0 to SDRAM is being changed to to a mapping of 0 to Boot ROM or OCRAM.

In this case, a two step process whereby the L3 remap register is first set to the new desired MPU address 0 mapping and then the L2 cache address filtering registers have their address ranges adjusted accordingly must be followed. An example follows:

// 1 MB reset default value for address filtering start
#define L2_CACHE_ADDR_FILTERING_START_RESET     0x100000
uint32_t addr_filt_start;
uint32_t addr_filt_end;

// Perform L3 remap register programming first by setting the desired new MPU
// address space 0 mapping. Assume OCRAM for the example.
alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ZERO_AT_OCRAM, ...);

// Next, adjust the L2 cache address filtering range. Set the start address to
// the default reset value and retain the existing end address configuration.
alt_l2_addr_filter_cfg_get(&addr_filt_start, &addr_filt_end);
if (addr_filt_start != L2_CACHE_ADDR_FILTERING_START_RESET)
{
    alt_l2_addr_filter_cfg_set(L2_CACHE_ADDR_FILTERING_START_RESET, addr_filt_end);
}

Typedef Documentation

◆ ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_t

typedef enum ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_e ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_t

This type definition enumerates the HPS to FPGA bridge accessiblity attributes.

◆ ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_t

typedef enum ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_e ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_t

This type definition enumerates the Lightweight HPS to FPGA bridge accessiblity attributes.

◆ ALT_ADDR_SPACE_MPU_ATTR_t

typedef enum ALT_ADDR_SPACE_MPU_ATTR_e ALT_ADDR_SPACE_MPU_ATTR_t

This type definition enumerates the MPU address space attributes.

The MPU address space consists of the ARM Cortex A9 processors and associated processor peripherals (cache, MMU).

◆ ALT_ADDR_SPACE_NONMPU_ATTR_t

typedef enum ALT_ADDR_SPACE_NONMPU_ATTR_e ALT_ADDR_SPACE_NONMPU_ATTR_t

This type definition enumerates the non-MPU address space attributes.

The non-MPU address space consists of the non-MPU L3 masters including the DMA controllers (standalone and those built into peripherals), the F2H AXI Bridge, and the DAP.

Enumeration Type Documentation

◆ ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_e

enum ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_e

This type definition enumerates the HPS to FPGA bridge accessiblity attributes.

Enumerator
ALT_ADDR_SPACE_H2F_INACCESSIBLE	The H2F AXI Bridge is not visible to L3 masters. Accesses to the associated address range return an AXI decode error to the master.
ALT_ADDR_SPACE_H2F_ACCESSIBLE	The H2F AXI Bridge is visible to L3 masters.

◆ ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_e

enum ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_e

This type definition enumerates the Lightweight HPS to FPGA bridge accessiblity attributes.

Enumerator
ALT_ADDR_SPACE_LWH2F_INACCESSIBLE	The LWH2F AXI Bridge is not visible to L3 masters. Accesses to the associated address range return an AXI decode error to the master.
ALT_ADDR_SPACE_LWH2F_ACCESSIBLE	The LWH2F AXI Bridge is visible to L3 masters.

◆ ALT_ADDR_SPACE_MPU_ATTR_e

enum ALT_ADDR_SPACE_MPU_ATTR_e

This type definition enumerates the MPU address space attributes.

The MPU address space consists of the ARM Cortex A9 processors and associated processor peripherals (cache, MMU).

Enumerator
ALT_ADDR_SPACE_MPU_ZERO_AT_BOOTROM	Maps the Boot ROM to address 0x0 for the MPU L3 master. Note that the Boot ROM is also always mapped to address 0xfffd_0000 for the MPU L3 master independent of attribute.
ALT_ADDR_SPACE_MPU_ZERO_AT_OCRAM	Maps the On-chip RAM to address 0x0 for the MPU L3 master. Note that the On-chip RAM is also always mapped to address 0xffff_0000 for the MPU L3 master independent of this attribute.

◆ ALT_ADDR_SPACE_NONMPU_ATTR_e

enum ALT_ADDR_SPACE_NONMPU_ATTR_e

This type definition enumerates the non-MPU address space attributes.

The non-MPU address space consists of the non-MPU L3 masters including the DMA controllers (standalone and those built into peripherals), the F2H AXI Bridge, and the DAP.

Enumerator
ALT_ADDR_SPACE_NONMPU_ZERO_AT_SDRAM	Maps the SDRAM to address 0x0 for the non-MPU L3 masters.
ALT_ADDR_SPACE_NONMPU_ZERO_AT_OCRAM	Maps the On-chip RAM to address 0x0 for the non-MPU L3 masters. Note that the On-chip RAM is also always mapped to address 0xffff_0000 for the non-MPU L3 masters independent of this attribute.

Function Documentation

◆ alt_addr_space_remap()

ALT_STATUS_CODE alt_addr_space_remap	(	ALT_ADDR_SPACE_MPU_ATTR_t	mpu_attr,
		ALT_ADDR_SPACE_NONMPU_ATTR_t	nonmpu_attr,
		ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_t	h2f_attr,
		ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_t	lwh2f_attr
	)

Configures the mapped and accessible (visible) address ranges for the HPS MPU, non-MPU, and Bridge address spaces.

Parameters

mpu_attr	The MPU address space configuration attributes.
nonmpu_attr	The non-MPU address space configuration attributes.
h2f_attr	The H2F Bridge attribute mapping and accessibility attributes.
lwh2f_attr	The Lightweight H2F Bridge attribute mapping and accessibility attributes.

Return values

ALT_E_SUCCESS	The operation was succesful.
ALT_E_ERROR	The operation failed.
ALT_E_INV_OPTION	One or more invalid attribute options were specified.

◆ alt_mpu_addr_space_remap_0_to_sdram()

ALT_STATUS_CODE alt_mpu_addr_space_remap_0_to_sdram ( void )

Maps SDRAM to address 0x0 for the MPU address space view.

When address 0x0 is mapped to the Boot ROM or on-chip RAM, only the lowest 64KB of the boot region are accessible because the size of the Boot ROM and on-chip RAM are only 64KB. Addresses in the range 0x100000 (1MiB) to 0xC0000000 (3GiB) access SDRAM and addresses in the range 0xC0000000 (3GiB) to 0xFFFFFFFF access the L3 interconnect. Thus, the lowest 1MiB of SDRAM is not accessible to the MPU unless address 0 is remapped to SDRAM after reset.

This function remaps the addresses between 0x0 to 0x100000 (1MiB) to access SDRAM.