RTEMS  5.0.0
emc.h
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1 
9 /*
10  * Copyright (c) 2010-2011 embedded brains GmbH. All rights reserved.
11  *
12  * embedded brains GmbH
13  * Obere Lagerstr. 30
14  * 82178 Puchheim
15  * Germany
16  * <rtems@embedded-brains.de>
17  *
18  * The license and distribution terms for this file may be
19  * found in the file LICENSE in this distribution or at
20  * http://www.rtems.org/license/LICENSE.
21  */
22 
23 #ifndef LIBBSP_ARM_LPC32XX_EMC_H
24 #define LIBBSP_ARM_LPC32XX_EMC_H
25 
26 #include <rtems.h>
27 
28 #include <bsp/lpc-emc.h>
29 
30 #ifdef __cplusplus
31 extern "C" {
32 #endif /* __cplusplus */
33 
48 #define SDRAMCLK_CLOCKS_DIS BSP_BIT32(0)
49 #define SDRAMCLK_DDR_MODE BSP_BIT32(1)
50 #define SDRAMCLK_DDR_DQSIN_DELAY(val) BSP_FLD32(val, 2, 6)
51 #define SDRAMCLK_RTC_TICK_EN BSP_BIT32(7)
52 #define SDRAMCLK_SW_DDR_CAL BSP_BIT32(8)
53 #define SDRAMCLK_CAL_DELAY BSP_BIT32(9)
54 #define SDRAMCLK_SENSITIVITY_FACTOR(val) BSP_FLD32(val, 10, 12)
55 #define SDRAMCLK_DCA_STATUS BSP_BIT32(13)
56 #define SDRAMCLK_COMMAND_DELAY(val) BSP_FLD32(val, 14, 18)
57 #define SDRAMCLK_SW_DDR_RESET BSP_BIT32(19)
58 #define SDRAMCLK_PIN_1_FAST BSP_BIT32(20)
59 #define SDRAMCLK_PIN_2_FAST BSP_BIT32(21)
60 #define SDRAMCLK_PIN_3_FAST BSP_BIT32(22)
61 
70 #define EMC_AHB_PORT_BUFF_EN BSP_BIT32(0)
71 
80 #define EMC_AHB_TIMEOUT(val) BSP_FLD32(val, 0, 9)
81 
90 #define SDRAM_ADDR_ROW_16MB(val) ((uint32_t) (val) << 10)
91 #define SDRAM_ADDR_ROW_32MB(val) ((uint32_t) (val) << 11)
92 #define SDRAM_ADDR_ROW_64MB(val) ((uint32_t) (val) << 11)
93 
94 #define SDRAM_ADDR_BANK_16MB(ba1, ba0) \
95  (((uint32_t) (ba1) << 23) | ((uint32_t) (ba0) << 22))
96 #define SDRAM_ADDR_BANK_32MB(ba1, ba0) \
97  (((uint32_t) (ba1) << 23) | ((uint32_t) (ba0) << 24))
98 #define SDRAM_ADDR_BANK_64MB(ba1, ba0) \
99  (((uint32_t) (ba1) << 25) | ((uint32_t) (ba0) << 24))
100 
101 #define SDRAM_MODE_16MB(mode) \
102  (SDRAM_ADDR_BANK_16MB(0, 0) | SDRAM_ADDR_ROW_16MB(mode))
103 #define SDRAM_MODE_32MB(mode) \
104  (SDRAM_ADDR_BANK_32MB(0, 0) | SDRAM_ADDR_ROW_32MB(mode))
105 #define SDRAM_MODE_64MB(mode) \
106  (SDRAM_ADDR_BANK_64MB(0, 0) | SDRAM_ADDR_ROW_64MB(mode))
107 
108 #define SDRAM_EXTMODE_16MB(mode) \
109  (SDRAM_ADDR_BANK_16MB(1, 0) | SDRAM_ADDR_ROW_16MB(mode))
110 #define SDRAM_EXTMODE_32MB(mode) \
111  (SDRAM_ADDR_BANK_32MB(1, 0) | SDRAM_ADDR_ROW_32MB(mode))
112 #define SDRAM_EXTMODE_64MB(mode) \
113  (SDRAM_ADDR_BANK_64MB(1, 0) | SDRAM_ADDR_ROW_64MB(mode))
114 
115 #define SDRAM_MODE_BURST_LENGTH(val) BSP_FLD32(val, 0, 2)
116 #define SDRAM_MODE_BURST_INTERLEAVE BSP_BIT32(3)
117 #define SDRAM_MODE_CAS(val) BSP_FLD32(val, 4, 6)
118 #define SDRAM_MODE_TEST_MODE(val) BSP_FLD32(val, 7, 8)
119 #define SDRAM_MODE_WRITE_BURST_SINGLE_BIT BSP_BIT32(9)
120 
121 #define SDRAM_EXTMODE_PASR(val) BSP_FLD32(val, 0, 2)
122 #define SDRAM_EXTMODE_DRIVER_STRENGTH(val) BSP_FLD32(val, 5, 6)
123 
126 typedef struct {
127  uint32_t size;
128  uint32_t config;
129  uint32_t rascas;
130  uint32_t mode;
131  uint32_t extmode;
133 
134 typedef struct {
135  uint32_t sdramclk_ctrl;
136  uint32_t nop_time_in_us;
137  uint32_t control;
138  uint32_t refresh;
139  uint32_t readconfig;
140  uint32_t trp;
141  uint32_t tras;
142  uint32_t tsrex;
143  uint32_t twr;
144  uint32_t trc;
145  uint32_t trfc;
146  uint32_t txsr;
147  uint32_t trrd;
148  uint32_t tmrd;
149  uint32_t tcdlr;
150  lpc32xx_emc_dynamic_chip_config chip [EMC_DYN_CHIP_COUNT];
152 
153 void lpc32xx_emc_init(const lpc32xx_emc_dynamic_config *dyn_cfg);
154 
157 #ifdef __cplusplus
158 }
159 #endif /* __cplusplus */
160 
161 #endif /* LIBBSP_ARM_LPC32XX_EMC_H */
Definition: emc.h:134
Definition: emc.h:126
struct rtems_bsdnet_ifconfig * config
Network driver configuration.
Definition: intercom.c:74
EMC support API.
unsigned size
Definition: tte.h:74