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#define | EMC_DYN_CHIP_COUNT 4 |
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#define | EMC_STATIC_CHIP_COUNT 4 |
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#define | EMC_CTRL_E BSP_BIT32(0) |
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#define | EMC_CTRL_M BSP_BIT32(0) |
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#define | EMC_CTRL_L BSP_BIT32(2) |
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#define | EMC_DYN_CTRL_CE BSP_BIT32(0) |
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#define | EMC_DYN_CTRL_CS BSP_BIT32(1) |
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#define | EMC_DYN_CTRL_SR BSP_BIT32(2) |
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#define | EMC_DYN_CTRL_SRMCC BSP_BIT32(3) |
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#define | EMC_DYN_CTRL_IMCC BSP_BIT32(4) |
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#define | EMC_DYN_CTRL_MCC BSP_BIT32(5) |
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#define | EMC_DYN_CTRL_I_MASK BSP_MSK32(7, 8) |
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#define | EMC_DYN_CTRL_I_NORMAL BSP_FLD32(0x0, 7, 8) |
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#define | EMC_DYN_CTRL_I_MODE BSP_FLD32(0x1, 7, 8) |
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#define | EMC_DYN_CTRL_I_PALL BSP_FLD32(0x2, 7, 8) |
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#define | EMC_DYN_CTRL_I_NOP BSP_FLD32(0x3, 7, 8) |
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#define | EMC_DYN_CTRL_DP BSP_BIT32(13) |
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#define | EMC_DYN_READ_CONFIG_SDR_STRAT(val) BSP_FLD32(val, 0, 1) |
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#define | EMC_DYN_READ_CONFIG_SDR_POL_POS BSP_BIT32(4) |
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#define | EMC_DYN_READ_CONFIG_DDR_STRAT(val) BSP_FLD32(val, 8, 9) |
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#define | EMC_DYN_READ_CONFIG_DDR_POL_POS BSP_BIT32(12) |
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#define | EMC_DYN_CFG_MD_LPC24XX(val) BSP_FLD32(val, 3, 4) |
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#define | EMC_DYN_CFG_MD_LPC32XX(val) BSP_FLD32(val, 0, 2) |
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#define | EMC_DYN_CFG_AM(val) BSP_FLD32(val, 7, 14) |
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#define | EMC_DYN_CFG_B BSP_BIT32(19) |
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#define | EMC_DYN_CFG_P BSP_BIT32(20) |
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#define | EMC_DYN_RASCAS_RAS(val) BSP_FLD32(val, 0, 3) |
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#define | EMC_DYN_RASCAS_CAS(val, half) BSP_FLD32(((val) << 1) | (half), 7, 10) |
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