Interrupt definitions.
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#define | ZYNQ_IRQ_CPU_0 32 |
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#define | ZYNQ_IRQ_CPU_1 33 |
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#define | ZYNQ_IRQ_L2_CACHE 34 |
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#define | ZYNQ_IRQ_OCM 35 |
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#define | ZYNQ_IRQ_PMU_0 37 |
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#define | ZYNQ_IRQ_PMU_1 38 |
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#define | ZYNQ_IRQ_XADC 39 |
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#define | ZYNQ_IRQ_DVI 40 |
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#define | ZYNQ_IRQ_SWDT 41 |
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#define | ZYNQ_IRQ_TTC_0_0 42 |
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#define | ZYNQ_IRQ_TTC_1_0 43 |
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#define | ZYNQ_IRQ_TTC_2_0 44 |
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#define | ZYNQ_IRQ_DMAC_ABORT 45 |
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#define | ZYNQ_IRQ_DMAC_0 46 |
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#define | ZYNQ_IRQ_DMAC_1 47 |
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#define | ZYNQ_IRQ_DMAC_2 48 |
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#define | ZYNQ_IRQ_DMAC_3 49 |
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#define | ZYNQ_IRQ_SMC 50 |
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#define | ZYNQ_IRQ_QUAD_SPI 51 |
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#define | ZYNQ_IRQ_GPIO 52 |
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#define | ZYNQ_IRQ_USB_0 53 |
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#define | ZYNQ_IRQ_ETHERNET_0 54 |
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#define | ZYNQ_IRQ_ETHERNET_0_WAKEUP 55 |
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#define | ZYNQ_IRQ_SDIO_0 56 |
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#define | ZYNQ_IRQ_I2C_0 57 |
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#define | ZYNQ_IRQ_SPI_0 58 |
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#define | ZYNQ_IRQ_UART_0 59 |
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#define | ZYNQ_IRQ_CAN_0 60 |
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#define | ZYNQ_IRQ_FPGA_0 61 |
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#define | ZYNQ_IRQ_FPGA_1 62 |
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#define | ZYNQ_IRQ_FPGA_2 63 |
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#define | ZYNQ_IRQ_FPGA_3 64 |
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#define | ZYNQ_IRQ_FPGA_4 65 |
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#define | ZYNQ_IRQ_FPGA_5 66 |
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#define | ZYNQ_IRQ_FPGA_6 67 |
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#define | ZYNQ_IRQ_FPGA_7 68 |
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#define | ZYNQ_IRQ_TTC_0_1 69 |
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#define | ZYNQ_IRQ_TTC_1_1 70 |
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#define | ZYNQ_IRQ_TTC_2_1 71 |
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#define | ZYNQ_IRQ_DMAC_4 72 |
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#define | ZYNQ_IRQ_DMAC_5 73 |
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#define | ZYNQ_IRQ_DMAC_6 74 |
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#define | ZYNQ_IRQ_DMAC_7 75 |
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#define | ZYNQ_IRQ_USB_1 76 |
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#define | ZYNQ_IRQ_ETHERNET_1 77 |
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#define | ZYNQ_IRQ_ETHERNET_1_WAKEUP 78 |
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#define | ZYNQ_IRQ_SDIO_1 79 |
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#define | ZYNQ_IRQ_I2C_1 80 |
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#define | ZYNQ_IRQ_SPI_1 81 |
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#define | ZYNQ_IRQ_UART_1 82 |
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#define | ZYNQ_IRQ_CAN_1 83 |
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#define | ZYNQ_IRQ_FPGA_8 84 |
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#define | ZYNQ_IRQ_FPGA_9 85 |
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#define | ZYNQ_IRQ_FPGA_10 86 |
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#define | ZYNQ_IRQ_FPGA_11 87 |
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#define | ZYNQ_IRQ_FPGA_12 88 |
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#define | ZYNQ_IRQ_FPGA_13 89 |
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#define | ZYNQ_IRQ_FPGA_14 90 |
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#define | ZYNQ_IRQ_FPGA_15 91 |
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#define | ZYNQ_IRQ_PARITY 92 |
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#define | BSP_INTERRUPT_VECTOR_MIN 0 |
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#define | BSP_INTERRUPT_VECTOR_MAX 92 |
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