RTEMS  5.0.0
bsp.h
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1 
9 /*
10  * Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved.
11  *
12  * embedded brains GmbH
13  * Obere Lagerstr. 30
14  * 82178 Puchheim
15  * Germany
16  * <rtems@embedded-brains.de>
17  *
18  * The license and distribution terms for this file may be
19  * found in the file LICENSE in this distribution or at
20  * http://www.rtems.org/license/LICENSE.
21  */
22 
23 #ifndef LIBBSP_ARM_LPC32XX_BSP_H
24 #define LIBBSP_ARM_LPC32XX_BSP_H
25 
36 #include <bspopts.h>
37 
38 #define BSP_FEATURE_IRQ_EXTENSION
39 
40 #ifndef ASM
41 
42 #include <rtems.h>
43 
44 #include <bsp/lpc32xx.h>
46 
47 #ifdef __cplusplus
48 extern "C" {
49 #endif /* __cplusplus */
50 
51 struct rtems_bsdnet_ifconfig;
52 
57  struct rtems_bsdnet_ifconfig *config,
58  int attaching
59 );
60 
64 #define RTEMS_BSP_NETWORK_DRIVER_ATTACH lpc_eth_attach_detach
65 
69 #define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0"
70 
91 void *lpc32xx_idle(uintptr_t ignored);
92 
93 #define LPC32XX_STANDARD_TIMER (&lpc32xx.timer_1)
94 
95 static inline unsigned lpc32xx_timer(void)
96 {
97  volatile lpc_timer *timer = LPC32XX_STANDARD_TIMER;
98 
99  return timer->tc;
100 }
101 
102 static inline void lpc32xx_micro_seconds_delay(unsigned us)
103 {
104  unsigned start = lpc32xx_timer();
105  unsigned delay = us * (LPC32XX_PERIPH_CLK / 1000000);
106  unsigned elapsed = 0;
107 
108  do {
109  elapsed = lpc32xx_timer() - start;
110  } while (elapsed < delay);
111 }
112 
113 #if LPC32XX_OSCILLATOR_MAIN == 13000000U
114  #define LPC32XX_HCLKPLL_CTRL_INIT_VALUE \
115  (HCLK_PLL_POWER | HCLK_PLL_DIRECT | HCLK_PLL_M(16 - 1))
116  #define LPC32XX_HCLKDIV_CTRL_INIT_VALUE \
117  (HCLK_DIV_HCLK(2 - 1) | HCLK_DIV_PERIPH_CLK(16 - 1) | HCLK_DIV_DDRAM_CLK(0))
118 #else
119  #error "unexpected main oscillator frequency"
120 #endif
121 
122 bool lpc32xx_start_pll_setup(
123  uint32_t hclkpll_ctrl,
124  uint32_t hclkdiv_ctrl,
125  bool force
126 );
127 
128 uint32_t lpc32xx_sysclk(void);
129 
130 uint32_t lpc32xx_hclkpll_clk(void);
131 
132 uint32_t lpc32xx_periph_clk(void);
133 
134 uint32_t lpc32xx_hclk(void);
135 
136 uint32_t lpc32xx_arm_clk(void);
137 
138 uint32_t lpc32xx_ddram_clk(void);
139 
140 typedef enum {
141  LPC32XX_NAND_CONTROLLER_NONE,
142  LPC32XX_NAND_CONTROLLER_MLC,
143  LPC32XX_NAND_CONTROLLER_SLC
144 } lpc32xx_nand_controller;
145 
146 void lpc32xx_select_nand_controller(lpc32xx_nand_controller nand_controller);
147 
148 void bsp_restart(void *addr);
149 
150 void *bsp_idle_thread(uintptr_t arg);
151 
152 #define BSP_IDLE_TASK_BODY bsp_idle_thread
153 
154 #define BSP_CONSOLE_UART_BASE LPC32XX_BASE_UART_5
155 
161 extern uint32_t lpc32xx_magic_zero_begin [];
162 
168 extern uint32_t lpc32xx_magic_zero_end [];
169 
175 extern uint32_t lpc32xx_magic_zero_size [];
176 
177 #ifdef LPC32XX_SCRATCH_AREA_SIZE
178 
183  extern uint8_t lpc32xx_scratch_area [LPC32XX_SCRATCH_AREA_SIZE]
184  __attribute__((aligned(32)));
185 #endif
186 
187 #define LPC32XX_DO_STOP_GPDMA \
188  do { \
189  if ((LPC32XX_DMACLK_CTRL & 0x1) != 0) { \
190  if ((lpc32xx.dma.cfg & DMA_CFG_E) != 0) { \
191  int i = 0; \
192  for (i = 0; i < 8; ++i) { \
193  lpc32xx.dma.channels [i].cfg = 0; \
194  } \
195  lpc32xx.dma.cfg &= ~DMA_CFG_E; \
196  } \
197  LPC32XX_DMACLK_CTRL = 0; \
198  } \
199  } while (0)
200 
201 #define LPC32XX_DO_STOP_ETHERNET \
202  do { \
203  if ((LPC32XX_MAC_CLK_CTRL & 0x7) == 0x7) { \
204  lpc32xx.eth.command = 0x38; \
205  lpc32xx.eth.mac1 = 0xcf00; \
206  lpc32xx.eth.mac1 = 0; \
207  LPC32XX_MAC_CLK_CTRL = 0; \
208  } \
209  } while (0)
210 
211 #define LPC32XX_DO_STOP_USB \
212  do { \
213  if ((LPC32XX_USB_CTRL & 0x010e8000) != 0) { \
214  LPC32XX_OTG_CLK_CTRL = 0; \
215  LPC32XX_USB_CTRL = 0x80000; \
216  } \
217  } while (0)
218 
219 #define LPC32XX_DO_RESTART(addr) \
220  do { \
221  ARM_SWITCH_REGISTERS; \
222  rtems_interrupt_level level; \
223  uint32_t ctrl = 0; \
224  \
225  rtems_interrupt_disable(level); \
226  (void) level; /* avoid set but not used warning */ \
227  \
228  arm_cp15_data_cache_test_and_clean(); \
229  arm_cp15_instruction_cache_invalidate(); \
230  \
231  ctrl = arm_cp15_get_control(); \
232  ctrl &= ~(ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M); \
233  arm_cp15_set_control(ctrl); \
234  \
235  __asm__ volatile ( \
236  ARM_SWITCH_TO_ARM \
237  "mov pc, %[addr]\n" \
238  ARM_SWITCH_BACK \
239  : ARM_SWITCH_OUTPUT \
240  : [addr] "r" (addr) \
241  ); \
242  } while (0)
243 
244 #ifdef __cplusplus
245 }
246 #endif /* __cplusplus */
247 
248 #endif /* ASM */
249 
252 #endif /* LIBBSP_ARM_LPC32XX_BSP_H */
Definition: deflate.c:115
void * lpc32xx_idle(uintptr_t ignored)
Optimized idle task.
int lpc_eth_attach_detach(struct rtems_bsdnet_ifconfig *config, int attaching)
Network driver attach and detach function.
Definition: lpc-ethernet.c:1827
Timer control block.
Definition: lpc-timer.h:133
DEFAULT_INITIAL_EXTENSION Support.
uint32_t lpc32xx_magic_zero_size[]
Size of magic zero area.
uint32_t lpc32xx_magic_zero_begin[]
Begin of magic zero area.
uint32_t lpc32xx_magic_zero_end[]
End of magic zero area.
Register base addresses.
typedef __attribute__
Disable IRQ Interrupts.
Definition: cmsis_gcc.h:69
void * bsp_idle_thread(uintptr_t ignored)
Optimized idle task.
Definition: bspidle.c:26
void bsp_restart(const void *addr)
Restarts the bsp with "addr" address.
Definition: restart.c:25