24 #ifndef LIBCPU_SHARED_ARM_CP15_H 25 #define LIBCPU_SHARED_ARM_CP15_H 37 #ifndef ARM_CP15_TEXT_SECTION 38 #define ARM_CP15_TEXT_SECTION 41 #define ARM_CP15_CACHE_PREPARE_MVA(mva) \ 42 ((const void *) (((uint32_t) (mva)) & ~0x1fU)) 44 #define ARM_CP15_TLB_PREPARE_MVA(mva) \ 45 ((const void *) (((uint32_t) (mva)) & ~0x3fU)) 67 #define ARM_MMU_SECT_BASE_SHIFT 20 68 #define ARM_MMU_SECT_BASE_MASK (0xfffU << ARM_MMU_SECT_BASE_SHIFT) 69 #define ARM_MMU_SECT_NS (1U << 19) 70 #define ARM_MMU_SECT_NG (1U << 17) 71 #define ARM_MMU_SECT_S (1U << 16) 72 #define ARM_MMU_SECT_AP_2 (1U << 15) 73 #define ARM_MMU_SECT_TEX_2 (1U << 14) 74 #define ARM_MMU_SECT_TEX_1 (1U << 13) 75 #define ARM_MMU_SECT_TEX_0 (1U << 12) 76 #define ARM_MMU_SECT_TEX_SHIFT 12 77 #define ARM_MMU_SECT_TEX_MASK (0x3U << ARM_MMU_SECT_TEX_SHIFT) 78 #define ARM_MMU_SECT_AP_1 (1U << 11) 79 #define ARM_MMU_SECT_AP_0 (1U << 10) 80 #define ARM_MMU_SECT_AP_SHIFT 10 81 #define ARM_MMU_SECT_AP_MASK (0x23U << ARM_MMU_SECT_AP_SHIFT) 82 #define ARM_MMU_SECT_DOMAIN_SHIFT 5 83 #define ARM_MMU_SECT_DOMAIN_MASK (0xfU << ARM_MMU_SECT_DOMAIN_SHIFT) 84 #define ARM_MMU_SECT_XN (1U << 4) 85 #define ARM_MMU_SECT_C (1U << 3) 86 #define ARM_MMU_SECT_B (1U << 2) 87 #define ARM_MMU_SECT_PXN (1U << 0) 88 #define ARM_MMU_SECT_DEFAULT 0x2U 89 #define ARM_MMU_SECT_GET_INDEX(mva) \ 90 (((uint32_t) (mva)) >> ARM_MMU_SECT_BASE_SHIFT) 91 #define ARM_MMU_SECT_MVA_ALIGN_UP(mva) \ 92 ((1U << ARM_MMU_SECT_BASE_SHIFT) \ 93 + ((((uint32_t) (mva) - 1U)) & ~((1U << ARM_MMU_SECT_BASE_SHIFT) - 1U))) 95 #define ARM_MMU_TRANSLATION_TABLE_ENTRY_SIZE 4U 96 #define ARM_MMU_TRANSLATION_TABLE_ENTRY_COUNT 4096U 98 #define ARM_MMU_DEFAULT_CLIENT_DOMAIN 15U 100 #define ARMV7_MMU_READ_ONLY \ 101 ((ARM_MMU_DEFAULT_CLIENT_DOMAIN << ARM_MMU_SECT_DOMAIN_SHIFT) \ 102 | ARM_MMU_SECT_AP_0 \ 103 | ARM_MMU_SECT_AP_2 \ 104 | ARM_MMU_SECT_DEFAULT) 106 #define ARMV7_MMU_READ_ONLY_CACHED \ 107 (ARMV7_MMU_READ_ONLY | ARM_MMU_SECT_TEX_0 | ARM_MMU_SECT_C | ARM_MMU_SECT_B) 109 #define ARMV7_MMU_READ_WRITE \ 110 ((ARM_MMU_DEFAULT_CLIENT_DOMAIN << ARM_MMU_SECT_DOMAIN_SHIFT) \ 111 | ARM_MMU_SECT_AP_0 \ 112 | ARM_MMU_SECT_DEFAULT) 115 #define ARMV7_MMU_READ_WRITE_CACHED \ 116 (ARMV7_MMU_READ_WRITE \ 117 | ARM_MMU_SECT_TEX_0 | ARM_MMU_SECT_C | ARM_MMU_SECT_B | ARM_MMU_SECT_S) 119 #define ARMV7_MMU_READ_WRITE_CACHED \ 120 (ARMV7_MMU_READ_WRITE \ 121 | ARM_MMU_SECT_TEX_0 | ARM_MMU_SECT_C | ARM_MMU_SECT_B) 124 #define ARMV7_MMU_DATA_READ_ONLY \ 125 (ARMV7_MMU_READ_ONLY | ARM_MMU_SECT_TEX_0) 127 #define ARMV7_MMU_DATA_READ_ONLY_CACHED \ 128 ARMV7_MMU_READ_ONLY_CACHED 130 #define ARMV7_MMU_DATA_READ_WRITE \ 131 (ARMV7_MMU_READ_WRITE | ARM_MMU_SECT_TEX_0) 133 #define ARMV7_MMU_DATA_READ_WRITE_CACHED \ 134 ARMV7_MMU_READ_WRITE_CACHED 136 #define ARMV7_MMU_CODE \ 137 (ARMV7_MMU_READ_ONLY | ARM_MMU_SECT_TEX_0) 139 #define ARMV7_MMU_CODE_CACHED \ 140 ARMV7_MMU_READ_ONLY_CACHED 142 #define ARMV7_MMU_DEVICE \ 143 (ARMV7_MMU_READ_WRITE | ARM_MMU_SECT_B) 153 #define ARM_CP15_CTRL_TE (1U << 30) 154 #define ARM_CP15_CTRL_AFE (1U << 29) 155 #define ARM_CP15_CTRL_TRE (1U << 28) 156 #define ARM_CP15_CTRL_NMFI (1U << 27) 157 #define ARM_CP15_CTRL_EE (1U << 25) 158 #define ARM_CP15_CTRL_VE (1U << 24) 159 #define ARM_CP15_CTRL_XP (1U << 23) 160 #define ARM_CP15_CTRL_U (1U << 22) 161 #define ARM_CP15_CTRL_FI (1U << 21) 162 #define ARM_CP15_CTRL_UWXN (1U << 20) 163 #define ARM_CP15_CTRL_WXN (1U << 19) 164 #define ARM_CP15_CTRL_HA (1U << 17) 165 #define ARM_CP15_CTRL_L4 (1U << 15) 166 #define ARM_CP15_CTRL_RR (1U << 14) 167 #define ARM_CP15_CTRL_V (1U << 13) 168 #define ARM_CP15_CTRL_I (1U << 12) 169 #define ARM_CP15_CTRL_Z (1U << 11) 170 #define ARM_CP15_CTRL_SW (1U << 10) 171 #define ARM_CP15_CTRL_R (1U << 9) 172 #define ARM_CP15_CTRL_S (1U << 8) 173 #define ARM_CP15_CTRL_B (1U << 7) 174 #define ARM_CP15_CTRL_CP15BEN (1U << 5) 175 #define ARM_CP15_CTRL_C (1U << 2) 176 #define ARM_CP15_CTRL_A (1U << 1) 177 #define ARM_CP15_CTRL_M (1U << 0) 187 #define ARM_CP15_DAC_NO_ACCESS 0x0U 188 #define ARM_CP15_DAC_CLIENT 0x1U 189 #define ARM_CP15_DAC_MANAGER 0x3U 190 #define ARM_CP15_DAC_DOMAIN(index, val) ((val) << (2 * index)) 200 #define ARM_CP15_FAULT_STATUS_MASK 0x040F 202 #define ARM_CP15_FSR_ALIGNMENT_FAULT 0x00000001 203 #define ARM_CP15_FSR_BACKGROUND_FAULT 0x0000 204 #define ARM_CP15_FSR_ACCESS_PERMISSION_FAULT 0x000D 205 #define ARM_CP15_FSR_PRECISE_EXTERNAL_ABORT_FAULT 0x0008 206 #define ARM_CP15_FSR_IMPRECISE_EXTERNAL_ABORT_FAULT 0x0406 207 #define ARM_CP15_FSR_PRECISE_PARITY_ERROR_EXCEPTION 0x0006 208 #define ARM_CP15_FSR_IMPRECISE_PARITY_ERROR_EXCEPTION 0x0408 209 #define ARM_CP15_FSR_DEBUG_EVENT 0x0002 222 #define ARM_CP15_CACHE_TYPE_FORMAT_ARMV6 0 223 #define ARM_CP15_CACHE_TYPE_FORMAT_ARMV7 4 233 #define ARM_CP15_CACHE_CSS_ID_DATA 0 234 #define ARM_CP15_CACHE_CSS_ID_INSTRUCTION 1 235 #define ARM_CP15_CACHE_CSS_LEVEL(level) ((level) << 1) 239 ARM_CP15_TEXT_SECTION
static inline uint32_t
240 arm_cp15_get_id_code(
void)
242 ARM_SWITCH_REGISTERS;
247 "mrc p15, 0, %[val], c0, c0, 0\n" 249 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
255 ARM_CP15_TEXT_SECTION
static inline uint32_t
256 arm_cp15_get_tcm_status(
void)
258 ARM_SWITCH_REGISTERS;
263 "mrc p15, 0, %[val], c0, c0, 2\n" 265 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
271 ARM_CP15_TEXT_SECTION
static inline uint32_t
272 arm_cp15_get_control(
void)
274 ARM_SWITCH_REGISTERS;
279 "mrc p15, 0, %[val], c1, c0, 0\n" 281 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
287 ARM_CP15_TEXT_SECTION
static inline void 288 arm_cp15_set_control(uint32_t val)
290 ARM_SWITCH_REGISTERS;
294 "mcr p15, 0, %[val], c1, c0, 0\n" 320 ARM_CP15_TEXT_SECTION
static inline uint32_t
321 arm_cp15_mmu_disable(uint32_t cls)
323 ARM_SWITCH_REGISTERS;
330 "mrc p15, 0, %[ctrl], c1, c0, 0\n" 331 "bic %[tmp_0], %[ctrl], #1\n" 332 "mcr p15, 0, %[tmp_0], c1, c0, 0\n" 336 "rsb %[tmp_0], %[cls], #0\n" 337 "and %[tmp_0], %[tmp_0], %[tmp_1]\n" 338 "sub %[tmp_0], %[tmp_0], %[cls], asl #3\n" 339 "add %[tmp_1], %[tmp_0], %[cls], asl #4\n" 341 "mcr p15, 0, %[tmp_0], c7, c14, 1\n" 342 "add %[tmp_0], %[tmp_0], %[cls]\n" 343 "cmp %[tmp_1], %[tmp_0]\n" 346 : [ctrl]
"=&r" (ctrl),
347 [tmp_0]
"=&r" (tmp_0),
348 [tmp_1]
"=&r" (tmp_1)
349 ARM_SWITCH_ADDITIONAL_OUTPUT
357 ARM_CP15_TEXT_SECTION
static inline uint32_t
358 *arm_cp15_get_translation_table_base(
void)
360 ARM_SWITCH_REGISTERS;
365 "mrc p15, 0, %[base], c2, c0, 0\n" 367 : [base]
"=&r" (base) ARM_SWITCH_ADDITIONAL_OUTPUT
373 ARM_CP15_TEXT_SECTION
static inline void 374 arm_cp15_set_translation_table_base(uint32_t *base)
376 ARM_SWITCH_REGISTERS;
380 "mcr p15, 0, %[base], c2, c0, 0\n" 388 ARM_CP15_TEXT_SECTION
static inline uint32_t
389 arm_cp15_get_translation_table_base_control_register(
void)
391 ARM_SWITCH_REGISTERS;
396 "mrc p15, 0, %[ttb_cr], c2, c0, 2\n" 398 : [ttb_cr]
"=&r" (ttb_cr) ARM_SWITCH_ADDITIONAL_OUTPUT
404 ARM_CP15_TEXT_SECTION
static inline void 405 arm_cp15_set_translation_table_base_control_register(uint32_t ttb_cr)
407 ARM_SWITCH_REGISTERS;
411 "mcr p15, 0, %[ttb_cr], c2, c0, 2\n" 414 : [ttb_cr]
"r" (ttb_cr)
418 ARM_CP15_TEXT_SECTION
static inline uint32_t
419 arm_cp15_get_domain_access_control(
void)
421 ARM_SWITCH_REGISTERS;
426 "mrc p15, 0, %[val], c3, c0, 0\n" 428 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
434 ARM_CP15_TEXT_SECTION
static inline void 435 arm_cp15_set_domain_access_control(uint32_t val)
437 ARM_SWITCH_REGISTERS;
441 "mcr p15, 0, %[val], c3, c0, 0\n" 448 ARM_CP15_TEXT_SECTION
static inline uint32_t
449 arm_cp15_get_data_fault_status(
void)
451 ARM_SWITCH_REGISTERS;
456 "mrc p15, 0, %[val], c5, c0, 0\n" 458 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
464 ARM_CP15_TEXT_SECTION
static inline void 465 arm_cp15_set_data_fault_status(uint32_t val)
467 ARM_SWITCH_REGISTERS;
471 "mcr p15, 0, %[val], c5, c0, 0\n" 478 ARM_CP15_TEXT_SECTION
static inline uint32_t
479 arm_cp15_get_instruction_fault_status(
void)
481 ARM_SWITCH_REGISTERS;
486 "mrc p15, 0, %[val], c5, c0, 1\n" 488 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
494 ARM_CP15_TEXT_SECTION
static inline void 495 arm_cp15_set_instruction_fault_status(uint32_t val)
497 ARM_SWITCH_REGISTERS;
501 "mcr p15, 0, %[val], c5, c0, 1\n" 508 ARM_CP15_TEXT_SECTION
static inline void 509 *arm_cp15_get_fault_address(
void)
511 ARM_SWITCH_REGISTERS;
516 "mrc p15, 0, %[mva], c6, c0, 0\n" 518 : [mva]
"=&r" (mva) ARM_SWITCH_ADDITIONAL_OUTPUT
524 ARM_CP15_TEXT_SECTION
static inline void 525 arm_cp15_set_fault_address(
const void *mva)
527 ARM_SWITCH_REGISTERS;
531 "mcr p15, 0, %[mva], c6, c0, 0\n" 538 ARM_CP15_TEXT_SECTION
static inline void 539 arm_cp15_tlb_invalidate(
void)
541 ARM_SWITCH_REGISTERS;
546 "mcr p15, 0, %[sbz], c8, c7, 0\n" 556 _ARM_Data_synchronization_barrier();
557 _ARM_Instruction_synchronization_barrier();
560 ARM_CP15_TEXT_SECTION
static inline void 561 arm_cp15_tlb_invalidate_entry(
const void *mva)
563 ARM_SWITCH_REGISTERS;
565 mva = ARM_CP15_TLB_PREPARE_MVA(mva);
569 "mcr p15, 0, %[mva], c8, c7, 1\n" 576 ARM_CP15_TEXT_SECTION
static inline void 577 arm_cp15_tlb_invalidate_entry_all_asids(
const void *mva)
579 ARM_SWITCH_REGISTERS;
581 mva = ARM_CP15_TLB_PREPARE_MVA(mva);
585 "mcr p15, 0, %[mva], c8, c7, 3\n" 592 ARM_CP15_TEXT_SECTION
static inline void 593 arm_cp15_tlb_instruction_invalidate(
void)
595 ARM_SWITCH_REGISTERS;
600 "mcr p15, 0, %[sbz], c8, c5, 0\n" 607 ARM_CP15_TEXT_SECTION
static inline void 608 arm_cp15_tlb_instruction_invalidate_entry(
const void *mva)
610 ARM_SWITCH_REGISTERS;
612 mva = ARM_CP15_TLB_PREPARE_MVA(mva);
616 "mcr p15, 0, %[mva], c8, c5, 1\n" 623 ARM_CP15_TEXT_SECTION
static inline void 624 arm_cp15_tlb_data_invalidate(
void)
626 ARM_SWITCH_REGISTERS;
631 "mcr p15, 0, %[sbz], c8, c6, 0\n" 638 ARM_CP15_TEXT_SECTION
static inline void 639 arm_cp15_tlb_data_invalidate_entry(
const void *mva)
641 ARM_SWITCH_REGISTERS;
643 mva = ARM_CP15_TLB_PREPARE_MVA(mva);
647 "mcr p15, 0, %[mva], c8, c6, 1\n" 654 ARM_CP15_TEXT_SECTION
static inline void 655 arm_cp15_tlb_lockdown_entry(
const void *mva)
657 uint32_t arm_switch_reg;
661 "add %[arm_switch_reg], pc, #16\n" 662 "mcr p15, 0, %[arm_switch_reg], c7, c13, 1\n" 663 "mcr p15, 0, %[mva], c8, c7, 1\n" 664 "mrc p15, 0, %[arm_switch_reg], c10, c0, 0\n" 665 "orr %[arm_switch_reg], #0x1\n" 666 "mcr p15, 0, %[arm_switch_reg], c10, c0, 0\n" 667 "ldr %[mva], [%[mva]]\n" 668 "mrc p15, 0, %[arm_switch_reg], c10, c0, 0\n" 669 "bic %[arm_switch_reg], #0x1\n" 670 "mcr p15, 0, %[arm_switch_reg], c10, c0, 0\n" 672 : [mva]
"=r" (mva), [arm_switch_reg]
"=&r" (arm_switch_reg)
686 ARM_CP15_TEXT_SECTION
static inline uint32_t
687 arm_cp15_get_cache_type(
void)
689 ARM_SWITCH_REGISTERS;
694 "mrc p15, 0, %[val], c0, c0, 1\n" 696 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
703 ARM_CP15_TEXT_SECTION
static inline int 704 arm_cp15_cache_type_get_format(uint32_t
ct)
706 return (ct >> 29) & 0x7U;
710 ARM_CP15_TEXT_SECTION
static inline uint32_t
711 arm_cp15_get_min_cache_line_size(
void)
714 uint32_t ct = arm_cp15_get_cache_type();
715 uint32_t
format = arm_cp15_cache_type_get_format(ct);
717 if (format == ARM_CP15_CACHE_TYPE_FORMAT_ARMV7) {
719 mcls = (1U << (ct & 0xf)) * 4;
720 }
else if (format == ARM_CP15_CACHE_TYPE_FORMAT_ARMV6) {
722 uint32_t mask = (1U << 12) - 1;
723 uint32_t dcls = (ct >> 12) & mask;
724 uint32_t icls = ct & mask;
726 mcls = dcls <= icls ? dcls : icls;
733 ARM_CP15_TEXT_SECTION
static inline uint32_t
734 arm_cp15_get_data_cache_line_size(
void)
737 uint32_t ct = arm_cp15_get_cache_type();
738 uint32_t format = arm_cp15_cache_type_get_format(ct);
740 if (format == ARM_CP15_CACHE_TYPE_FORMAT_ARMV7) {
742 mcls = (1U << ((ct & 0xf0000) >> 16)) * 4;
743 }
else if (format == ARM_CP15_CACHE_TYPE_FORMAT_ARMV6) {
745 uint32_t mask = (1U << 12) - 1;
746 mcls = (ct >> 12) & mask;
753 ARM_CP15_TEXT_SECTION
static inline uint32_t
754 arm_cp15_get_instruction_cache_line_size(
void)
757 uint32_t ct = arm_cp15_get_cache_type();
758 uint32_t format = arm_cp15_cache_type_get_format(ct);
760 if (format == ARM_CP15_CACHE_TYPE_FORMAT_ARMV7) {
762 mcls = (1U << (ct & 0x0000f)) * 4;
763 }
else if (format == ARM_CP15_CACHE_TYPE_FORMAT_ARMV6) {
765 uint32_t mask = (1U << 12) - 1;
774 ARM_CP15_TEXT_SECTION
static inline uint32_t
775 arm_cp15_get_cache_size_id(
void)
777 ARM_SWITCH_REGISTERS;
782 "mrc p15, 1, %[val], c0, c0, 0\n" 784 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
790 ARM_CP15_TEXT_SECTION
static inline uint32_t
791 arm_ccsidr_get_line_power(uint32_t ccsidr)
793 return (ccsidr & 0x7) + 4;
796 ARM_CP15_TEXT_SECTION
static inline uint32_t
797 arm_ccsidr_get_associativity(uint32_t ccsidr)
799 return ((ccsidr >> 3) & 0x3ff) + 1;
802 ARM_CP15_TEXT_SECTION
static inline uint32_t
803 arm_ccsidr_get_num_sets(uint32_t ccsidr)
805 return ((ccsidr >> 13) & 0x7fff) + 1;
810 ARM_CP15_TEXT_SECTION
static inline uint32_t
811 arm_cp15_get_cache_level_id(
void)
813 ARM_SWITCH_REGISTERS;
818 "mrc p15, 1, %[val], c0, c0, 1\n" 820 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
826 ARM_CP15_TEXT_SECTION
static inline uint32_t
827 arm_clidr_get_level_of_coherency(uint32_t clidr)
829 return (clidr >> 24) & 0x7;
832 ARM_CP15_TEXT_SECTION
static inline uint32_t
833 arm_clidr_get_cache_type(uint32_t clidr, uint32_t level)
835 return (clidr >> (3 * level)) & 0x7;
840 ARM_CP15_TEXT_SECTION
static inline uint32_t
841 arm_cp15_get_cache_size_selection(
void)
843 ARM_SWITCH_REGISTERS;
848 "mrc p15, 2, %[val], c0, c0, 0\n" 850 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
856 ARM_CP15_TEXT_SECTION
static inline void 857 arm_cp15_set_cache_size_selection(uint32_t val)
859 ARM_SWITCH_REGISTERS;
863 "mcr p15, 2, %[val], c0, c0, 0\n" 871 ARM_CP15_TEXT_SECTION
static inline uint32_t
872 arm_cp15_get_cache_size_id_for_level(uint32_t level_and_inst_dat)
878 arm_cp15_set_cache_size_selection(level_and_inst_dat);
879 _ARM_Instruction_synchronization_barrier();
880 ccsidr = arm_cp15_get_cache_size_id();
886 ARM_CP15_TEXT_SECTION
static inline void 887 arm_cp15_cache_invalidate(
void)
889 ARM_SWITCH_REGISTERS;
894 "mcr p15, 0, %[sbz], c7, c7, 0\n" 904 ARM_CP15_TEXT_SECTION
static inline void 905 arm_cp15_instruction_cache_inner_shareable_invalidate_all(
void)
907 ARM_SWITCH_REGISTERS;
912 "mcr p15, 0, %[sbz], c7, c1, 0\n" 922 ARM_CP15_TEXT_SECTION
static inline void 923 arm_cp15_branch_predictor_inner_shareable_invalidate_all(
void)
925 ARM_SWITCH_REGISTERS;
930 "mcr p15, 0, %[sbz], c7, c1, 6\n" 940 ARM_CP15_TEXT_SECTION
static inline void 941 arm_cp15_branch_predictor_invalidate_all(
void)
943 ARM_SWITCH_REGISTERS;
948 "mcr p15, 0, %[sbz], c7, c5, 6\n" 957 ARM_CP15_TEXT_SECTION
static inline void 958 arm_cp15_flush_prefetch_buffer(
void)
960 ARM_SWITCH_REGISTERS;
965 "mcr p15, 0, %[sbz], c7, c5, 4\n" 973 ARM_CP15_TEXT_SECTION
static inline void 974 arm_cp15_instruction_cache_invalidate(
void)
976 ARM_SWITCH_REGISTERS;
981 "mcr p15, 0, %[sbz], c7, c5, 0\n" 989 ARM_CP15_TEXT_SECTION
static inline void 990 arm_cp15_instruction_cache_invalidate_line(
const void *mva)
992 ARM_SWITCH_REGISTERS;
994 mva = ARM_CP15_CACHE_PREPARE_MVA(mva);
998 "mcr p15, 0, %[mva], c7, c5, 1\n" 1006 ARM_CP15_TEXT_SECTION
static inline void 1007 arm_cp15_instruction_cache_invalidate_line_by_set_and_way(uint32_t set_and_way)
1009 ARM_SWITCH_REGISTERS;
1013 "mcr p15, 0, %[set_and_way], c7, c5, 2\n" 1016 : [set_and_way]
"r" (set_and_way)
1021 ARM_CP15_TEXT_SECTION
static inline void 1022 arm_cp15_instruction_cache_prefetch_line(
const void *mva)
1024 ARM_SWITCH_REGISTERS;
1026 mva = ARM_CP15_CACHE_PREPARE_MVA(mva);
1030 "mcr p15, 0, %[mva], c7, c13, 1\n" 1037 ARM_CP15_TEXT_SECTION
static inline void 1038 arm_cp15_data_cache_invalidate(
void)
1040 ARM_SWITCH_REGISTERS;
1045 "mcr p15, 0, %[sbz], c7, c6, 0\n" 1053 ARM_CP15_TEXT_SECTION
static inline void 1054 arm_cp15_data_cache_invalidate_line(
const void *mva)
1056 ARM_SWITCH_REGISTERS;
1058 mva = ARM_CP15_CACHE_PREPARE_MVA(mva);
1062 "mcr p15, 0, %[mva], c7, c6, 1\n" 1070 ARM_CP15_TEXT_SECTION
static inline void 1071 arm_cp15_data_cache_invalidate_line_by_set_and_way(uint32_t set_and_way)
1073 ARM_SWITCH_REGISTERS;
1077 "mcr p15, 0, %[set_and_way], c7, c6, 2\n" 1080 : [set_and_way]
"r" (set_and_way)
1085 ARM_CP15_TEXT_SECTION
static inline void 1086 arm_cp15_cache_invalidate_level(uint32_t level, uint32_t inst_data_fl)
1089 uint32_t line_power;
1090 uint32_t associativity;
1094 ccsidr = arm_cp15_get_cache_size_id_for_level((level << 1) | inst_data_fl);
1096 line_power = arm_ccsidr_get_line_power(ccsidr);
1097 associativity = arm_ccsidr_get_associativity(ccsidr);
1098 way_shift = __builtin_clz(associativity - 1);
1100 for (way = 0; way < associativity; ++way) {
1101 uint32_t num_sets = arm_ccsidr_get_num_sets(ccsidr);
1104 for (
set = 0;
set < num_sets; ++
set) {
1105 uint32_t set_way = (way << way_shift)
1106 | (
set << line_power)
1109 arm_cp15_data_cache_invalidate_line_by_set_and_way(set_way);
1114 ARM_CP15_TEXT_SECTION
static inline void 1115 arm_cp15_data_cache_invalidate_all_levels(
void)
1117 uint32_t clidr = arm_cp15_get_cache_level_id();
1118 uint32_t loc = arm_clidr_get_level_of_coherency(clidr);
1121 for (level = 0; level < loc; ++level) {
1122 uint32_t ctype = arm_clidr_get_cache_type(clidr, level);
1125 if (((ctype & (0x6)) == 2) || (ctype == 4)) {
1126 arm_cp15_cache_invalidate_level(level, 0);
1131 ARM_CP15_TEXT_SECTION
static inline void 1132 arm_cp15_data_cache_clean_line(
const void *mva)
1134 ARM_SWITCH_REGISTERS;
1136 mva = ARM_CP15_CACHE_PREPARE_MVA(mva);
1140 "mcr p15, 0, %[mva], c7, c10, 1\n" 1148 ARM_CP15_TEXT_SECTION
static inline void 1149 arm_cp15_data_cache_clean_line_by_set_and_way(uint32_t set_and_way)
1151 ARM_SWITCH_REGISTERS;
1155 "mcr p15, 0, %[set_and_way], c7, c10, 2\n" 1158 : [set_and_way]
"r" (set_and_way)
1163 ARM_CP15_TEXT_SECTION
static inline void 1164 arm_cp15_data_cache_clean_level(uint32_t level)
1167 uint32_t line_power;
1168 uint32_t associativity;
1172 ccsidr = arm_cp15_get_cache_size_id_for_level(level << 1);
1174 line_power = arm_ccsidr_get_line_power(ccsidr);
1175 associativity = arm_ccsidr_get_associativity(ccsidr);
1176 way_shift = __builtin_clz(associativity - 1);
1178 for (way = 0; way < associativity; ++way) {
1179 uint32_t num_sets = arm_ccsidr_get_num_sets(ccsidr);
1182 for (
set = 0;
set < num_sets; ++
set) {
1183 uint32_t set_way = (way << way_shift)
1184 | (
set << line_power)
1187 arm_cp15_data_cache_clean_line_by_set_and_way(set_way);
1192 ARM_CP15_TEXT_SECTION
static inline void 1193 arm_cp15_data_cache_clean_all_levels(
void)
1195 uint32_t clidr = arm_cp15_get_cache_level_id();
1196 uint32_t loc = arm_clidr_get_level_of_coherency(clidr);
1199 for (level = 0; level < loc; ++level) {
1200 uint32_t ctype = arm_clidr_get_cache_type(clidr, level);
1203 if (((ctype & (0x6)) == 2) || (ctype == 4)) {
1204 arm_cp15_data_cache_clean_level(level);
1209 ARM_CP15_TEXT_SECTION
static inline void 1210 arm_cp15_data_cache_test_and_clean(
void)
1212 ARM_SWITCH_REGISTERS;
1217 "mrc p15, 0, r15, c7, c10, 3\n" 1230 ARM_CP15_TEXT_SECTION
static inline void 1231 arm_cp15_data_cache_clean_and_invalidate(
void)
1233 ARM_SWITCH_REGISTERS;
1239 "mcr p15, 0, %[sbz], c7, c14, 0\n" 1247 ARM_CP15_TEXT_SECTION
static inline void 1248 arm_cp15_data_cache_clean_and_invalidate_line(
const void *mva)
1250 ARM_SWITCH_REGISTERS;
1252 mva = ARM_CP15_CACHE_PREPARE_MVA(mva);
1256 "mcr p15, 0, %[mva], c7, c14, 1\n" 1264 ARM_CP15_TEXT_SECTION
static inline void 1265 arm_cp15_data_cache_clean_and_invalidate_line_by_set_and_way(uint32_t set_and_way)
1267 ARM_SWITCH_REGISTERS;
1271 "mcr p15, 0, %[set_and_way], c7, c14, 2\n" 1274 : [set_and_way]
"r" (set_and_way)
1279 ARM_CP15_TEXT_SECTION
static inline void 1280 arm_cp15_data_cache_test_and_clean_and_invalidate(
void)
1282 ARM_SWITCH_REGISTERS;
1287 "mrc p15, 0, r15, c7, c14, 3\n" 1298 ARM_CP15_TEXT_SECTION
static inline void 1299 arm_cp15_drain_write_buffer(
void)
1301 ARM_SWITCH_REGISTERS;
1306 "mcr p15, 0, %[sbz], c7, c10, 4\n" 1314 ARM_CP15_TEXT_SECTION
static inline void 1315 arm_cp15_wait_for_interrupt(
void)
1317 ARM_SWITCH_REGISTERS;
1322 "mcr p15, 0, %[sbz], c7, c0, 4\n" 1330 ARM_CP15_TEXT_SECTION
static inline uint32_t
1331 arm_cp15_get_multiprocessor_affinity(
void)
1333 ARM_SWITCH_REGISTERS;
1338 "mrc p15, 0, %[mpidr], c0, c0, 5\n" 1340 : [mpidr]
"=&r" (mpidr) ARM_SWITCH_ADDITIONAL_OUTPUT
1343 return mpidr & 0xff;
1346 ARM_CP15_TEXT_SECTION
static inline uint32_t
1347 arm_cortex_a9_get_multiprocessor_cpu_id(
void)
1349 return arm_cp15_get_multiprocessor_affinity() & 0xff;
1352 #define ARM_CORTEX_A9_ACTL_FW (1U << 0) 1353 #define ARM_CORTEX_A9_ACTL_L2_PREFETCH_HINT_ENABLE (1U << 1) 1354 #define ARM_CORTEX_A9_ACTL_L1_PREFETCH_ENABLE (1U << 2) 1355 #define ARM_CORTEX_A9_ACTL_WRITE_FULL_LINE_OF_ZEROS_MODE (1U << 3) 1356 #define ARM_CORTEX_A9_ACTL_SMP (1U << 6) 1357 #define ARM_CORTEX_A9_ACTL_EXCL (1U << 7) 1358 #define ARM_CORTEX_A9_ACTL_ALLOC_IN_ONE_WAY (1U << 8) 1359 #define ARM_CORTEX_A9_ACTL_PARITY_ON (1U << 9) 1361 ARM_CP15_TEXT_SECTION
static inline uint32_t
1362 arm_cp15_get_auxiliary_control(
void)
1364 ARM_SWITCH_REGISTERS;
1369 "mrc p15, 0, %[val], c1, c0, 1\n" 1371 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
1377 ARM_CP15_TEXT_SECTION
static inline void 1378 arm_cp15_set_auxiliary_control(uint32_t val)
1380 ARM_SWITCH_REGISTERS;
1384 "mcr p15, 0, %[val], c1, c0, 1\n" 1393 ARM_CP15_TEXT_SECTION
static inline uint32_t
1394 arm_cp15_get_processor_feature_1(
void)
1396 ARM_SWITCH_REGISTERS;
1401 "mrc p15, 0, %[val], c0, c1, 1\n" 1403 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
1411 ARM_CP15_TEXT_SECTION
static inline void 1412 *arm_cp15_get_vector_base_address(
void)
1414 ARM_SWITCH_REGISTERS;
1419 "mrc p15, 0, %[base], c12, c0, 0\n" 1421 : [base]
"=&r" (base) ARM_SWITCH_ADDITIONAL_OUTPUT
1427 ARM_CP15_TEXT_SECTION
static inline void 1428 arm_cp15_set_vector_base_address(
void *base)
1430 ARM_SWITCH_REGISTERS;
1434 "mcr p15, 0, %[base], c12, c0, 0\n" 1441 ARM_CP15_TEXT_SECTION
static inline void 1442 *arm_cp15_get_hyp_vector_base_address(
void)
1444 ARM_SWITCH_REGISTERS;
1449 "mrc p15, 4, %[base], c12, c0, 0\n" 1451 : [base]
"=&r" (base) ARM_SWITCH_ADDITIONAL_OUTPUT
1457 ARM_CP15_TEXT_SECTION
static inline void 1458 arm_cp15_set_hyp_vector_base_address(
void *base)
1460 ARM_SWITCH_REGISTERS;
1464 "mcr p15, 4, %[base], c12, c0, 0\n" 1472 ARM_CP15_TEXT_SECTION
static inline uint32_t
1473 arm_cp15_get_performance_monitors_cycle_count(
void)
1475 ARM_SWITCH_REGISTERS;
1480 "mrc p15, 0, %[val], c9, c13, 0\n" 1482 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
1489 ARM_CP15_TEXT_SECTION
static inline void 1490 arm_cp15_set_performance_monitors_cycle_count(uint32_t val)
1492 ARM_SWITCH_REGISTERS;
1496 "mcr p15, 0, %[val], c9, c13, 0\n" 1504 ARM_CP15_TEXT_SECTION
static inline uint32_t
1505 arm_cp15_get_performance_monitors_common_event_id_0(
void)
1507 ARM_SWITCH_REGISTERS;
1512 "mrc p15, 0, %[val], c9, c12, 6\n" 1514 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
1521 ARM_CP15_TEXT_SECTION
static inline uint32_t
1522 arm_cp15_get_performance_monitors_common_event_id_1(
void)
1524 ARM_SWITCH_REGISTERS;
1529 "mrc p15, 0, %[val], c9, c12, 7\n" 1531 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
1537 #define ARM_CP15_PMCLRSET_CYCLE_COUNTER 0x80000000 1540 ARM_CP15_TEXT_SECTION
static inline uint32_t
1541 arm_cp15_get_performance_monitors_count_enable_clear(
void)
1543 ARM_SWITCH_REGISTERS;
1548 "mrc p15, 0, %[val], c9, c12, 2\n" 1550 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
1557 ARM_CP15_TEXT_SECTION
static inline void 1558 arm_cp15_set_performance_monitors_count_enable_clear(uint32_t val)
1560 ARM_SWITCH_REGISTERS;
1564 "mcr p15, 0, %[val], c9, c12, 2\n" 1572 ARM_CP15_TEXT_SECTION
static inline uint32_t
1573 arm_cp15_get_performance_monitors_count_enable_set(
void)
1575 ARM_SWITCH_REGISTERS;
1580 "mrc p15, 0, %[val], c9, c12, 1\n" 1582 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
1589 ARM_CP15_TEXT_SECTION
static inline void 1590 arm_cp15_set_performance_monitors_count_enable_set(uint32_t val)
1592 ARM_SWITCH_REGISTERS;
1596 "mcr p15, 0, %[val], c9, c12, 1\n" 1603 #define ARM_CP15_PMCR_IMP(x) ((x) << 24) 1604 #define ARM_CP15_PMCR_IDCODE(x) ((x) << 16) 1605 #define ARM_CP15_PMCR_N(x) ((x) << 11) 1606 #define ARM_CP15_PMCR_DP (1U << 5) 1607 #define ARM_CP15_PMCR_X (1U << 4) 1608 #define ARM_CP15_PMCR_D (1U << 3) 1609 #define ARM_CP15_PMCR_C (1U << 2) 1610 #define ARM_CP15_PMCR_P (1U << 1) 1611 #define ARM_CP15_PMCR_E (1U << 0) 1614 ARM_CP15_TEXT_SECTION
static inline uint32_t
1615 arm_cp15_get_performance_monitors_control(
void)
1617 ARM_SWITCH_REGISTERS;
1622 "mrc p15, 0, %[val], c9, c12, 0\n" 1624 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
1631 ARM_CP15_TEXT_SECTION
static inline void 1632 arm_cp15_set_performance_monitors_control(uint32_t val)
1634 ARM_SWITCH_REGISTERS;
1638 "mcr p15, 0, %[val], c9, c12, 0\n" 1646 ARM_CP15_TEXT_SECTION
static inline uint32_t
1647 arm_cp15_get_performance_monitors_interrupt_enable_clear(
void)
1649 ARM_SWITCH_REGISTERS;
1654 "mrc p15, 0, %[val], c9, c14, 2\n" 1656 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
1663 ARM_CP15_TEXT_SECTION
static inline void 1664 arm_cp15_set_performance_monitors_interrupt_enable_clear(uint32_t val)
1666 ARM_SWITCH_REGISTERS;
1670 "mcr p15, 0, %[val], c9, c14, 2\n" 1678 ARM_CP15_TEXT_SECTION
static inline uint32_t
1679 arm_cp15_get_performance_monitors_interrupt_enable_set(
void)
1681 ARM_SWITCH_REGISTERS;
1686 "mrc p15, 0, %[val], c9, c14, 1\n" 1688 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
1695 ARM_CP15_TEXT_SECTION
static inline void 1696 arm_cp15_set_performance_monitors_interrupt_enable_set(uint32_t val)
1698 ARM_SWITCH_REGISTERS;
1702 "mcr p15, 0, %[val], c9, c14, 1\n" 1710 ARM_CP15_TEXT_SECTION
static inline uint32_t
1711 arm_cp15_get_performance_monitors_overflow_flag_status(
void)
1713 ARM_SWITCH_REGISTERS;
1718 "mrc p15, 0, %[val], c9, c12, 3\n" 1720 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
1727 ARM_CP15_TEXT_SECTION
static inline void 1728 arm_cp15_set_performance_monitors_overflow_flag_status(uint32_t val)
1730 ARM_SWITCH_REGISTERS;
1734 "mcr p15, 0, %[val], c9, c12, 3\n" 1742 ARM_CP15_TEXT_SECTION
static inline uint32_t
1743 arm_cp15_get_performance_monitors_overflow_flag_status_set(
void)
1745 ARM_SWITCH_REGISTERS;
1750 "mrc p15, 0, %[val], c9, c14, 3\n" 1752 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
1759 ARM_CP15_TEXT_SECTION
static inline void 1760 arm_cp15_set_performance_monitors_overflow_flag_status_set(uint32_t val)
1762 ARM_SWITCH_REGISTERS;
1766 "mcr p15, 0, %[val], c9, c14, 3\n" 1774 ARM_CP15_TEXT_SECTION
static inline uint32_t
1775 arm_cp15_get_performance_monitors_event_counter_selection(
void)
1777 ARM_SWITCH_REGISTERS;
1782 "mrc p15, 0, %[val], c9, c12, 5\n" 1784 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
1791 ARM_CP15_TEXT_SECTION
static inline void 1792 arm_cp15_set_performance_monitors_event_counter_selection(uint32_t val)
1794 ARM_SWITCH_REGISTERS;
1798 "mcr p15, 0, %[val], c9, c12, 5\n" 1806 ARM_CP15_TEXT_SECTION
static inline void 1807 arm_cp15_set_performance_monitors_software_increment(uint32_t val)
1809 ARM_SWITCH_REGISTERS;
1813 "mcr p15, 0, %[val], c9, c12, 4\n" 1821 ARM_CP15_TEXT_SECTION
static inline uint32_t
1822 arm_cp15_get_performance_monitors_user_enable(
void)
1824 ARM_SWITCH_REGISTERS;
1829 "mrc p15, 0, %[val], c9, c14, 0\n" 1831 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
1838 ARM_CP15_TEXT_SECTION
static inline void 1839 arm_cp15_set_performance_monitors_user_enable(uint32_t val)
1841 ARM_SWITCH_REGISTERS;
1845 "mcr p15, 0, %[val], c9, c14, 0\n" 1853 ARM_CP15_TEXT_SECTION
static inline uint32_t
1854 arm_cp15_get_performance_monitors_event_count(
void)
1856 ARM_SWITCH_REGISTERS;
1861 "mrc p15, 0, %[val], c9, c13, 2\n" 1863 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
1870 ARM_CP15_TEXT_SECTION
static inline void 1871 arm_cp15_set_performance_monitors_event_count(uint32_t val)
1873 ARM_SWITCH_REGISTERS;
1877 "mcr p15, 0, %[val], c9, c13, 2\n" 1885 ARM_CP15_TEXT_SECTION
static inline uint32_t
1886 arm_cp15_get_performance_monitors_event_type_select(
void)
1888 ARM_SWITCH_REGISTERS;
1893 "mrc p15, 0, %[val], c9, c13, 1\n" 1895 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
1902 ARM_CP15_TEXT_SECTION
static inline void 1903 arm_cp15_set_performance_monitors_event_type_select(uint32_t val)
1905 ARM_SWITCH_REGISTERS;
1909 "mcr p15, 0, %[val], c9, c13, 1\n" 1917 ARM_CP15_TEXT_SECTION
static inline uint32_t
1918 arm_cp15_get_counter_frequency(
void)
1920 ARM_SWITCH_REGISTERS;
1925 "mrc p15, 0, %[val], c14, c0, 0\n" 1927 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
1934 ARM_CP15_TEXT_SECTION
static inline void 1935 arm_cp15_set_counter_frequency(uint32_t val)
1937 ARM_SWITCH_REGISTERS;
1941 "mcr p15, 0, %[val], c14, c0, 0\n" 1949 ARM_CP15_TEXT_SECTION
static inline uint64_t
1950 arm_cp15_get_counter_physical_count(
void)
1952 ARM_SWITCH_REGISTERS;
1957 "mrrc p15, 0, %Q[val], %R[val], c14\n" 1959 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
1966 ARM_CP15_TEXT_SECTION
static inline uint32_t
1967 arm_cp15_get_counter_non_secure_pl1_control(
void)
1969 ARM_SWITCH_REGISTERS;
1974 "mrc p15, 0, %[val], c14, c1, 0\n" 1976 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
1983 ARM_CP15_TEXT_SECTION
static inline void 1984 arm_cp15_set_counter_non_secure_pl1_control(uint32_t val)
1986 ARM_SWITCH_REGISTERS;
1990 "mcr p15, 0, %[val], c14, c1, 0\n" 1998 ARM_CP15_TEXT_SECTION
static inline uint32_t
1999 arm_cp15_get_counter_pl1_physical_timer_value(
void)
2001 ARM_SWITCH_REGISTERS;
2006 "mrc p15, 0, %[val], c14, c2, 0\n" 2008 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
2015 ARM_CP15_TEXT_SECTION
static inline void 2016 arm_cp15_set_counter_pl1_physical_timer_value(uint32_t val)
2018 ARM_SWITCH_REGISTERS;
2022 "mcr p15, 0, %[val], c14, c2, 0\n" 2030 ARM_CP15_TEXT_SECTION
static inline uint32_t
2031 arm_cp15_get_counter_pl1_physical_timer_control(
void)
2033 ARM_SWITCH_REGISTERS;
2038 "mrc p15, 0, %[val], c14, c2, 1\n" 2040 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
2047 ARM_CP15_TEXT_SECTION
static inline void 2048 arm_cp15_set_counter_pl1_physical_timer_control(uint32_t val)
2050 ARM_SWITCH_REGISTERS;
2054 "mcr p15, 0, %[val], c14, c2, 1\n" 2062 ARM_CP15_TEXT_SECTION
static inline uint32_t
2063 arm_cp15_get_counter_pl1_virtual_timer_value(
void)
2065 ARM_SWITCH_REGISTERS;
2070 "mrc p15, 0, %[val], c14, c3, 0\n" 2072 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
2079 ARM_CP15_TEXT_SECTION
static inline void 2080 arm_cp15_set_counter_pl1_virtual_timer_value(uint32_t val)
2082 ARM_SWITCH_REGISTERS;
2086 "mcr p15, 0, %[val], c14, c3, 0\n" 2094 ARM_CP15_TEXT_SECTION
static inline uint32_t
2095 arm_cp15_get_counter_pl1_virtual_timer_control(
void)
2097 ARM_SWITCH_REGISTERS;
2102 "mrc p15, 0, %[val], c14, c3, 1\n" 2104 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
2111 ARM_CP15_TEXT_SECTION
static inline void 2112 arm_cp15_set_counter_pl1_virtual_timer_control(uint32_t val)
2114 ARM_SWITCH_REGISTERS;
2118 "mcr p15, 0, %[val], c14, c3, 1\n" 2126 ARM_CP15_TEXT_SECTION
static inline uint64_t
2127 arm_cp15_get_counter_virtual_count(
void)
2129 ARM_SWITCH_REGISTERS;
2134 "mrrc p15, 1, %Q[val], %R[val], c14\n" 2136 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
2143 ARM_CP15_TEXT_SECTION
static inline uint64_t
2144 arm_cp15_get_counter_pl1_physical_compare_value(
void)
2146 ARM_SWITCH_REGISTERS;
2151 "mrrc p15, 2, %Q[val], %R[val], c14\n" 2153 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
2160 ARM_CP15_TEXT_SECTION
static inline void 2161 arm_cp15_set_counter_pl1_physical_compare_value(uint64_t val)
2163 ARM_SWITCH_REGISTERS;
2167 "mcrr p15, 2, %Q[val], %R[val], c14\n" 2175 ARM_CP15_TEXT_SECTION
static inline uint64_t
2176 arm_cp15_get_counter_pl1_virtual_compare_value(
void)
2178 ARM_SWITCH_REGISTERS;
2183 "mrrc p15, 3, %Q[val], %R[val], c14\n" 2185 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
2192 ARM_CP15_TEXT_SECTION
static inline void 2193 arm_cp15_set_counter_pl1_virtual_compare_value(uint64_t val)
2195 ARM_SWITCH_REGISTERS;
2199 "mcrr p15, 3, %Q[val], %R[val], c14\n" 2207 ARM_CP15_TEXT_SECTION
static inline uint64_t
2208 arm_cp15_get_counter_virtual_offset(
void)
2210 ARM_SWITCH_REGISTERS;
2215 "mrrc p15, 4, %Q[val], %R[val], c14\n" 2217 : [val]
"=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
2224 ARM_CP15_TEXT_SECTION
static inline void 2225 arm_cp15_set_counter_virtual_offset(uint64_t val)
2227 ARM_SWITCH_REGISTERS;
2231 "mcrr p15, 4, %Q[val], %R[val], c14\n" 2246 uint32_t section_flags
2249 void arm_cp15_set_exception_handler(
2250 Arm_symbolic_exception_name exception,
2251 void (*handler)(
void)
#define rtems_interrupt_local_enable(_isr_cookie)
This macro restores the previous interrupt level on the current processor.
Definition: intr.h:148
uint32_t arm_cp15_set_translation_table_entries(const void *begin, const void *end, uint32_t section_flags)
Sets the section_flags for the address range [begin, end).
Definition: arm-cp15-set-ttb-entries.c:82
register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__("g6")
The pointer to the current per-CPU control is available via register g6.
unsigned ct
Definition: tlb.h:224
ISR_Level rtems_interrupt_level
Interrupt level type.
Definition: intr.h:42
#define rtems_interrupt_local_disable(_isr_cookie)
This macro disables the interrupts on the current processor.
Definition: intr.h:138