RTEMS  5.0.0
alt_mpu_registers.h
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37 
38 #ifndef __ALT_MPUSCU_H__
39 #define __ALT_MPUSCU_H__
40 
41 
42 #ifdef __cplusplus
43 extern "C"
44 {
45 #endif /* __cplusplus */
46 
47 
48 /************************************************************************************************************/
49 /* alt_mpuscu.h */
50 /* */
51 /* Definitions for the ARM Snoop Control Unit, which contains the Snoop Control Unit, the Watchdog */
52 /* Timer, the Private Timer, the Global Timer, the Interrupt Controller, and the Interrupt Distributor. */
53 /* */
54 /************************************************************************************************************/
55 
56 #ifndef ALT_HPS_ADDR
57 #define ALT_HPS_ADDR 0x00
58 #endif
59 
60 
61 /* ALT_MPUSCU_OFST is defined as a offset from ALT_HPS_ADDR in the SoCAL file hps.h */
62 /* and is the address of the base of the Snoop Control Unit (SCU) */
63 #define GLOBALTMR_BASE (ALT_MPUSCU_OFST + GLOBALTMR_MODULE_BASE_OFFSET)
64 #define CPU_WDTGPT_TMR_BASE (ALT_MPUSCU_OFST + WDOG_TIMER_MODULE_BASE_OFFSET)
65 #define CPU_PRIVATE_TMR_BASE (ALT_MPUSCU_OFST + CPU_PRIV_TIMER_MODULE_BASE_OFFSET)
66 #define CPU_INT_CTRL_BASE (ALT_MPUSCU_OFST + INT_CONTROLLER_MODULE_BASE_OFFSET)
67 #define CPU_INT_DIST_BASE (ALT_MPUSCU_OFST + INT_DISTRIBUTOR_MODULE_BASE_OFFSET)
68 
69 
70  /* offsets */
71  /* Global Timer offsets */
72 #define GLOBALTMR_MODULE_BASE_OFFSET 0x00000200
73 #define GLOBALTMR_CNTR_LO_REG_OFFSET 0x00000000
74 #define GLOBALTMR_CNTR_HI_REG_OFFSET 0x00000004
75 #define GLOBALTMR_CTRL_REG_OFFSET 0x00000008
76 #define GLOBALTMR_INT_STAT_REG_OFFSET 0x0000000C
77 #define GLOBALTMR_COMP_LO_REG_OFFSET 0x00000010
78 #define GLOBALTMR_COMP_HI_REG_OFFSET 0x00000014
79 #define GLOBALTMR_AUTOINC_REG_OFFSET 0x00000018
80 
81 /* Global Timer bitmasks */
82 #define GLOBALTMR_ENABLE_BIT 0x00000001
83 #define GLOBALTMR_COMP_ENABLE_BIT 0x00000002
84 #define GLOBALTMR_INT_ENABLE_BIT 0x00000004
85 #define GLOBALTMR_AUTOINC_ENABLE_BIT 0x00000008
86 #define GLOBALTMR_PS_MASK 0x0000FF00
87 #define GLOBALTMR_PS_SHIFT 8
88 #define GLOBALTMR_INT_STATUS_BIT 0x00000001
89 
90 /* Global timer constants */
91 #define GLOBALTMR_MAX 0xFFFFFFFF
92 #define GLOBALTMR_PS_MAX 0x000000FF
93 
94 
95 /* Private timer offsets */
96 #define CPU_PRIV_TIMER_MODULE_BASE_OFFSET 0x00000600
97 #define CPU_PRIV_TMR_LOAD_REG_OFFSET 0x00000000
98 #define CPU_PRIV_TMR_CNTR_REG_OFFSET 0x00000004
99 #define CPU_PRIV_TMR_CTRL_REG_OFFSET 0x00000008
100 #define CPU_PRIV_TMR_INT_STATUS_REG_OFFSET 0x0000000C
101 
102 /* Private timer bitmasks */
103 #define CPU_PRIV_TMR_ENABLE 0x00000001
104 #define CPU_PRIV_TMR_AUTO_RELOAD 0x00000002
105 #define CPU_PRIV_TMR_INT_EN 0x00000004
106 #define CPU_PRIV_TMR_PS_MASK 0x0000FF00
107 #define CPU_PRIV_TMR_PS_SHIFT 8
108 #define CPU_PRIV_TMR_INT_STATUS 0x00000001
109 
110 /* Private timer constants */
111 #define CPU_PRIV_TMR_MAX 0xFFFFFFFF
112 #define CPU_PRIV_TMR_PS_MAX 0x000000FF
113 
114 
115 
116  /* Watchdog timer offsets */
117 #define WDOG_TIMER_MODULE_BASE_OFFSET 0x00000620
118 #define WDOG_LOAD_REG_OFFSET 0x00000000
119 #define WDOG_CNTR_REG_OFFSET 0x00000004
120 #define WDOG_CTRL_REG_OFFSET 0x00000008
121 #define WDOG_INTSTAT_REG_OFFSET 0x0000000C
122 #define WDOG_RSTSTAT_REG_OFFSET 0x00000010
123 #define WDOG_DISABLE_REG_OFFSET 0x00000014
124 
125  /* Watchdog timer bitmasks : */
126  /* Control Register bitmasks */
127 #define WDOG_TMR_ENABLE 0x00000001
128 #define WDOG_AUTO_RELOAD 0x00000002
129 #define WDOG_INT_EN 0x00000004
130 #define WDOG_WDT_MODE 0x00000008
131 #define WDOG_PS_MASK 0x0000FF00
132 #define WDOG_PS_SHIFT 8
133  /* Interrupt Status Register bitmasks */
134 #define WDOG_INT_STAT_BIT 0x00000001
135  /* Reset Status Register bitmasks */
136 #define WDOG_RST_STAT_BIT 0x00000001
137 
138  /* Watchdog timer constants */
139 #define WDOG_TMR_MAX UINT32_MAX
140 #define WDOG_PS_MAX UINT8_MAX
141 #define WDOG_DISABLE_VAL0 0x12345678
142 #define WDOG_DISABLE_VAL1 0x87654321
143 
144 
145 
146  /* Interrupt Manager offsets */
147 /* <Add definitions here> */
148 #define INT_CONTROLLER_MODULE_BASE_OFFSET 0x00000100
149 #define INT_DISTRIBUTOR_MODULE_BASE_OFFSET 0x00001000
150 #define INT_DIST_TYPE_REG 0x00000004
151 
152 
153 /* Upper bound of the MPUSCU address space */
154 #define MPUSCU_MAX 0x00001FFF
155 
156 
157 
158 #ifdef __cplusplus
159 }
160 #endif /* __cplusplus */
161 
162 #endif /* __ALT_MPUSCU_H__ */
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