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#define | ALT_HPS_ADDR 0x00 |
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#define | GLOBALTMR_BASE (ALT_MPUSCU_OFST + GLOBALTMR_MODULE_BASE_OFFSET) |
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#define | CPU_WDTGPT_TMR_BASE (ALT_MPUSCU_OFST + WDOG_TIMER_MODULE_BASE_OFFSET) |
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#define | CPU_PRIVATE_TMR_BASE (ALT_MPUSCU_OFST + CPU_PRIV_TIMER_MODULE_BASE_OFFSET) |
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#define | CPU_INT_CTRL_BASE (ALT_MPUSCU_OFST + INT_CONTROLLER_MODULE_BASE_OFFSET) |
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#define | CPU_INT_DIST_BASE (ALT_MPUSCU_OFST + INT_DISTRIBUTOR_MODULE_BASE_OFFSET) |
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#define | GLOBALTMR_MODULE_BASE_OFFSET 0x00000200 |
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#define | GLOBALTMR_CNTR_LO_REG_OFFSET 0x00000000 |
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#define | GLOBALTMR_CNTR_HI_REG_OFFSET 0x00000004 |
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#define | GLOBALTMR_CTRL_REG_OFFSET 0x00000008 |
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#define | GLOBALTMR_INT_STAT_REG_OFFSET 0x0000000C |
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#define | GLOBALTMR_COMP_LO_REG_OFFSET 0x00000010 |
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#define | GLOBALTMR_COMP_HI_REG_OFFSET 0x00000014 |
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#define | GLOBALTMR_AUTOINC_REG_OFFSET 0x00000018 |
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#define | GLOBALTMR_ENABLE_BIT 0x00000001 |
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#define | GLOBALTMR_COMP_ENABLE_BIT 0x00000002 |
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#define | GLOBALTMR_INT_ENABLE_BIT 0x00000004 |
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#define | GLOBALTMR_AUTOINC_ENABLE_BIT 0x00000008 |
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#define | GLOBALTMR_PS_MASK 0x0000FF00 |
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#define | GLOBALTMR_PS_SHIFT 8 |
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#define | GLOBALTMR_INT_STATUS_BIT 0x00000001 |
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#define | GLOBALTMR_MAX 0xFFFFFFFF |
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#define | GLOBALTMR_PS_MAX 0x000000FF |
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#define | CPU_PRIV_TIMER_MODULE_BASE_OFFSET 0x00000600 |
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#define | CPU_PRIV_TMR_LOAD_REG_OFFSET 0x00000000 |
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#define | CPU_PRIV_TMR_CNTR_REG_OFFSET 0x00000004 |
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#define | CPU_PRIV_TMR_CTRL_REG_OFFSET 0x00000008 |
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#define | CPU_PRIV_TMR_INT_STATUS_REG_OFFSET 0x0000000C |
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#define | CPU_PRIV_TMR_ENABLE 0x00000001 |
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#define | CPU_PRIV_TMR_AUTO_RELOAD 0x00000002 |
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#define | CPU_PRIV_TMR_INT_EN 0x00000004 |
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#define | CPU_PRIV_TMR_PS_MASK 0x0000FF00 |
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#define | CPU_PRIV_TMR_PS_SHIFT 8 |
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#define | CPU_PRIV_TMR_INT_STATUS 0x00000001 |
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#define | CPU_PRIV_TMR_MAX 0xFFFFFFFF |
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#define | CPU_PRIV_TMR_PS_MAX 0x000000FF |
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#define | WDOG_TIMER_MODULE_BASE_OFFSET 0x00000620 |
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#define | WDOG_LOAD_REG_OFFSET 0x00000000 |
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#define | WDOG_CNTR_REG_OFFSET 0x00000004 |
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#define | WDOG_CTRL_REG_OFFSET 0x00000008 |
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#define | WDOG_INTSTAT_REG_OFFSET 0x0000000C |
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#define | WDOG_RSTSTAT_REG_OFFSET 0x00000010 |
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#define | WDOG_DISABLE_REG_OFFSET 0x00000014 |
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#define | WDOG_TMR_ENABLE 0x00000001 |
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#define | WDOG_AUTO_RELOAD 0x00000002 |
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#define | WDOG_INT_EN 0x00000004 |
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#define | WDOG_WDT_MODE 0x00000008 |
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#define | WDOG_PS_MASK 0x0000FF00 |
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#define | WDOG_PS_SHIFT 8 |
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#define | WDOG_INT_STAT_BIT 0x00000001 |
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#define | WDOG_RST_STAT_BIT 0x00000001 |
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#define | WDOG_TMR_MAX UINT32_MAX |
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#define | WDOG_PS_MAX UINT8_MAX |
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#define | WDOG_DISABLE_VAL0 0x12345678 |
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#define | WDOG_DISABLE_VAL1 0x87654321 |
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#define | INT_CONTROLLER_MODULE_BASE_OFFSET 0x00000100 |
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#define | INT_DISTRIBUTOR_MODULE_BASE_OFFSET 0x00001000 |
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#define | INT_DIST_TYPE_REG 0x00000004 |
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#define | MPUSCU_MAX 0x00001FFF |
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