RTEMS  5.0.0
alt_l3.h
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36 
37 /* Altera - ALT_L3 */
38 
39 #ifndef __ALTERA_ALT_L3_H__
40 #define __ALTERA_ALT_L3_H__
41 
42 #ifdef __cplusplus
43 extern "C"
44 {
45 #endif /* __cplusplus */
46 
47 /*
48  * Component : L3 (NIC-301) GPV Registers - ALT_L3
49  * L3 (NIC-301) GPV Registers
50  *
51  * Registers to control L3 interconnect settings
52  *
53  */
54 /*
55  * Register : Remap - remap
56  *
57  * The L3 interconnect has separate address maps for the various L3 Masters.
58  * Generally, the addresses are the same for most masters. However, the sparse
59  * interconnect of the L3 switch causes some masters to have holes in their memory
60  * maps. The remap bits are not mutually exclusive. Each bit can be set
61  * independently and in combinations. Priority for the bits is determined by the
62  * bit offset: lower offset bits take precedence over higher offset bits.
63  *
64  * Register Layout
65  *
66  * Bits | Access | Reset | Description
67  * :-------|:-------|:------|:---------------------------------
68  * [0] | W | 0x0 | MPU at 0x0
69  * [1] | W | 0x0 | Non-MPU at 0x0
70  * [2] | ??? | 0x0 | *UNDEFINED*
71  * [3] | W | 0x0 | HPS2FPGA AXI Bridge Visibility
72  * [4] | W | 0x0 | LWHPS2FPGA AXI Bridge Visibility
73  * [31:5] | ??? | 0x0 | *UNDEFINED*
74  *
75  */
76 /*
77  * Field : MPU at 0x0 - mpuzero
78  *
79  * Controls whether address 0x0 for the MPU L3 master is mapped to the Boot ROM or
80  * On-chip RAM. This field only has an effect on the MPU L3 master.
81  *
82  * Field Enumeration Values:
83  *
84  * Enum | Value | Description
85  * :-------------------------------|:------|:-------------------------------------------------
86  * ALT_L3_REMAP_MPUZERO_E_BOOTROM | 0x0 | Maps the Boot ROM to address 0x0 for the MPU L3
87  * : | | master. Note that the Boot ROM is also always
88  * : | | mapped to address 0xfffd_0000 for the MPU L3
89  * : | | master independent of this field's value.
90  * ALT_L3_REMAP_MPUZERO_E_OCRAM | 0x1 | Maps the On-chip RAM to address 0x0 for the MPU
91  * : | | L3 master. Note that the On-chip RAM is also
92  * : | | always mapped to address 0xffff_0000 for the MPU
93  * : | | L3 master independent of this field's value.
94  *
95  * Field Access Macros:
96  *
97  */
98 /*
99  * Enumerated value for register field ALT_L3_REMAP_MPUZERO
100  *
101  * Maps the Boot ROM to address 0x0 for the MPU L3 master. Note that the Boot ROM
102  * is also always mapped to address 0xfffd_0000 for the MPU L3 master independent
103  * of this field's value.
104  */
105 #define ALT_L3_REMAP_MPUZERO_E_BOOTROM 0x0
106 /*
107  * Enumerated value for register field ALT_L3_REMAP_MPUZERO
108  *
109  * Maps the On-chip RAM to address 0x0 for the MPU L3 master. Note that the On-chip
110  * RAM is also always mapped to address 0xffff_0000 for the MPU L3 master
111  * independent of this field's value.
112  */
113 #define ALT_L3_REMAP_MPUZERO_E_OCRAM 0x1
114 
115 /* The Least Significant Bit (LSB) position of the ALT_L3_REMAP_MPUZERO register field. */
116 #define ALT_L3_REMAP_MPUZERO_LSB 0
117 /* The Most Significant Bit (MSB) position of the ALT_L3_REMAP_MPUZERO register field. */
118 #define ALT_L3_REMAP_MPUZERO_MSB 0
119 /* The width in bits of the ALT_L3_REMAP_MPUZERO register field. */
120 #define ALT_L3_REMAP_MPUZERO_WIDTH 1
121 /* The mask used to set the ALT_L3_REMAP_MPUZERO register field value. */
122 #define ALT_L3_REMAP_MPUZERO_SET_MSK 0x00000001
123 /* The mask used to clear the ALT_L3_REMAP_MPUZERO register field value. */
124 #define ALT_L3_REMAP_MPUZERO_CLR_MSK 0xfffffffe
125 /* The reset value of the ALT_L3_REMAP_MPUZERO register field. */
126 #define ALT_L3_REMAP_MPUZERO_RESET 0x0
127 /* Extracts the ALT_L3_REMAP_MPUZERO field value from a register. */
128 #define ALT_L3_REMAP_MPUZERO_GET(value) (((value) & 0x00000001) >> 0)
129 /* Produces a ALT_L3_REMAP_MPUZERO register field value suitable for setting the register. */
130 #define ALT_L3_REMAP_MPUZERO_SET(value) (((value) << 0) & 0x00000001)
131 
132 /*
133  * Field : Non-MPU at 0x0 - nonmpuzero
134  *
135  * Controls whether address 0x0 for the non-MPU L3 masters is mapped to the SDRAM
136  * or On-chip RAM. This field only has an effect on the non-MPU L3 masters. The
137  * non-MPU L3 masters are the DMA controllers (standalone and those built-in to
138  * peripherals), the FPGA2HPS AXI Bridge, and the DAP.
139  *
140  * Field Enumeration Values:
141  *
142  * Enum | Value | Description
143  * :--------------------------------|:------|:-------------------------------------------------
144  * ALT_L3_REMAP_NONMPUZERO_E_SDRAM | 0x0 | Maps the SDRAM to address 0x0 for the non-MPU L3
145  * : | | masters.
146  * ALT_L3_REMAP_NONMPUZERO_E_OCRAM | 0x1 | Maps the On-chip RAM to address 0x0 for the non-
147  * : | | MPU L3 masters. Note that the On-chip RAM is
148  * : | | also always mapped to address 0xffff_0000 for
149  * : | | the non-MPU L3 masters independent of this
150  * : | | field's value.
151  *
152  * Field Access Macros:
153  *
154  */
155 /*
156  * Enumerated value for register field ALT_L3_REMAP_NONMPUZERO
157  *
158  * Maps the SDRAM to address 0x0 for the non-MPU L3 masters.
159  */
160 #define ALT_L3_REMAP_NONMPUZERO_E_SDRAM 0x0
161 /*
162  * Enumerated value for register field ALT_L3_REMAP_NONMPUZERO
163  *
164  * Maps the On-chip RAM to address 0x0 for the non-MPU L3 masters. Note that the
165  * On-chip RAM is also always mapped to address 0xffff_0000 for the non-MPU L3
166  * masters independent of this field's value.
167  */
168 #define ALT_L3_REMAP_NONMPUZERO_E_OCRAM 0x1
169 
170 /* The Least Significant Bit (LSB) position of the ALT_L3_REMAP_NONMPUZERO register field. */
171 #define ALT_L3_REMAP_NONMPUZERO_LSB 1
172 /* The Most Significant Bit (MSB) position of the ALT_L3_REMAP_NONMPUZERO register field. */
173 #define ALT_L3_REMAP_NONMPUZERO_MSB 1
174 /* The width in bits of the ALT_L3_REMAP_NONMPUZERO register field. */
175 #define ALT_L3_REMAP_NONMPUZERO_WIDTH 1
176 /* The mask used to set the ALT_L3_REMAP_NONMPUZERO register field value. */
177 #define ALT_L3_REMAP_NONMPUZERO_SET_MSK 0x00000002
178 /* The mask used to clear the ALT_L3_REMAP_NONMPUZERO register field value. */
179 #define ALT_L3_REMAP_NONMPUZERO_CLR_MSK 0xfffffffd
180 /* The reset value of the ALT_L3_REMAP_NONMPUZERO register field. */
181 #define ALT_L3_REMAP_NONMPUZERO_RESET 0x0
182 /* Extracts the ALT_L3_REMAP_NONMPUZERO field value from a register. */
183 #define ALT_L3_REMAP_NONMPUZERO_GET(value) (((value) & 0x00000002) >> 1)
184 /* Produces a ALT_L3_REMAP_NONMPUZERO register field value suitable for setting the register. */
185 #define ALT_L3_REMAP_NONMPUZERO_SET(value) (((value) << 1) & 0x00000002)
186 
187 /*
188  * Field : HPS2FPGA AXI Bridge Visibility - hps2fpga
189  *
190  * Controls whether the HPS2FPGA AXI Bridge is visible to L3 masters or not.
191  *
192  * Field Enumeration Values:
193  *
194  * Enum | Value | Description
195  * :-----------------------------|:------|:------------------------------------------------
196  * ALT_L3_REMAP_H2F_E_INVISIBLE | 0x0 | The HPS2FPGA AXI Bridge is not visible to L3
197  * : | | masters. Accesses to the associated address
198  * : | | range return an AXI decode error to the master.
199  * ALT_L3_REMAP_H2F_E_VISIBLE | 0x1 | The HPS2FPGA AXI Bridge is visible to L3
200  * : | | masters.
201  *
202  * Field Access Macros:
203  *
204  */
205 /*
206  * Enumerated value for register field ALT_L3_REMAP_H2F
207  *
208  * The HPS2FPGA AXI Bridge is not visible to L3 masters. Accesses to the associated
209  * address range return an AXI decode error to the master.
210  */
211 #define ALT_L3_REMAP_H2F_E_INVISIBLE 0x0
212 /*
213  * Enumerated value for register field ALT_L3_REMAP_H2F
214  *
215  * The HPS2FPGA AXI Bridge is visible to L3 masters.
216  */
217 #define ALT_L3_REMAP_H2F_E_VISIBLE 0x1
218 
219 /* The Least Significant Bit (LSB) position of the ALT_L3_REMAP_H2F register field. */
220 #define ALT_L3_REMAP_H2F_LSB 3
221 /* The Most Significant Bit (MSB) position of the ALT_L3_REMAP_H2F register field. */
222 #define ALT_L3_REMAP_H2F_MSB 3
223 /* The width in bits of the ALT_L3_REMAP_H2F register field. */
224 #define ALT_L3_REMAP_H2F_WIDTH 1
225 /* The mask used to set the ALT_L3_REMAP_H2F register field value. */
226 #define ALT_L3_REMAP_H2F_SET_MSK 0x00000008
227 /* The mask used to clear the ALT_L3_REMAP_H2F register field value. */
228 #define ALT_L3_REMAP_H2F_CLR_MSK 0xfffffff7
229 /* The reset value of the ALT_L3_REMAP_H2F register field. */
230 #define ALT_L3_REMAP_H2F_RESET 0x0
231 /* Extracts the ALT_L3_REMAP_H2F field value from a register. */
232 #define ALT_L3_REMAP_H2F_GET(value) (((value) & 0x00000008) >> 3)
233 /* Produces a ALT_L3_REMAP_H2F register field value suitable for setting the register. */
234 #define ALT_L3_REMAP_H2F_SET(value) (((value) << 3) & 0x00000008)
235 
236 /*
237  * Field : LWHPS2FPGA AXI Bridge Visibility - lwhps2fpga
238  *
239  * Controls whether the Lightweight HPS2FPGA AXI Bridge is visible to L3 masters or
240  * not.
241  *
242  * Field Enumeration Values:
243  *
244  * Enum | Value | Description
245  * :-------------------------------|:------|:------------------------------------------------
246  * ALT_L3_REMAP_LWH2F_E_INVISIBLE | 0x0 | The LWHPS2FPGA AXI Bridge is not visible to L3
247  * : | | masters. Accesses to the associated address
248  * : | | range return an AXI decode error to the master.
249  * ALT_L3_REMAP_LWH2F_E_VISIBLE | 0x1 | The LWHPS2FPGA AXI Bridge is visible to L3
250  * : | | masters.
251  *
252  * Field Access Macros:
253  *
254  */
255 /*
256  * Enumerated value for register field ALT_L3_REMAP_LWH2F
257  *
258  * The LWHPS2FPGA AXI Bridge is not visible to L3 masters. Accesses to the
259  * associated address range return an AXI decode error to the master.
260  */
261 #define ALT_L3_REMAP_LWH2F_E_INVISIBLE 0x0
262 /*
263  * Enumerated value for register field ALT_L3_REMAP_LWH2F
264  *
265  * The LWHPS2FPGA AXI Bridge is visible to L3 masters.
266  */
267 #define ALT_L3_REMAP_LWH2F_E_VISIBLE 0x1
268 
269 /* The Least Significant Bit (LSB) position of the ALT_L3_REMAP_LWH2F register field. */
270 #define ALT_L3_REMAP_LWH2F_LSB 4
271 /* The Most Significant Bit (MSB) position of the ALT_L3_REMAP_LWH2F register field. */
272 #define ALT_L3_REMAP_LWH2F_MSB 4
273 /* The width in bits of the ALT_L3_REMAP_LWH2F register field. */
274 #define ALT_L3_REMAP_LWH2F_WIDTH 1
275 /* The mask used to set the ALT_L3_REMAP_LWH2F register field value. */
276 #define ALT_L3_REMAP_LWH2F_SET_MSK 0x00000010
277 /* The mask used to clear the ALT_L3_REMAP_LWH2F register field value. */
278 #define ALT_L3_REMAP_LWH2F_CLR_MSK 0xffffffef
279 /* The reset value of the ALT_L3_REMAP_LWH2F register field. */
280 #define ALT_L3_REMAP_LWH2F_RESET 0x0
281 /* Extracts the ALT_L3_REMAP_LWH2F field value from a register. */
282 #define ALT_L3_REMAP_LWH2F_GET(value) (((value) & 0x00000010) >> 4)
283 /* Produces a ALT_L3_REMAP_LWH2F register field value suitable for setting the register. */
284 #define ALT_L3_REMAP_LWH2F_SET(value) (((value) << 4) & 0x00000010)
285 
286 #ifndef __ASSEMBLY__
287 /*
288  * WARNING: The C register and register group struct declarations are provided for
289  * convenience and illustrative purposes. They should, however, be used with
290  * caution as the C language standard provides no guarantees about the alignment or
291  * atomicity of device memory accesses. The recommended practice for writing
292  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
293  * alt_write_word() functions.
294  *
295  * The struct declaration for register ALT_L3_REMAP.
296  */
298 {
299  uint32_t mpuzero : 1; /* MPU at 0x0 */
300  uint32_t nonmpuzero : 1; /* Non-MPU at 0x0 */
301  uint32_t : 1; /* *UNDEFINED* */
302  uint32_t hps2fpga : 1; /* HPS2FPGA AXI Bridge Visibility */
303  uint32_t lwhps2fpga : 1; /* LWHPS2FPGA AXI Bridge Visibility */
304  uint32_t : 27; /* *UNDEFINED* */
305 };
306 
307 /* The typedef declaration for register ALT_L3_REMAP. */
308 typedef volatile struct ALT_L3_REMAP_s ALT_L3_REMAP_t;
309 #endif /* __ASSEMBLY__ */
310 
311 /* The byte offset of the ALT_L3_REMAP register from the beginning of the component. */
312 #define ALT_L3_REMAP_OFST 0x0
313 
314 /*
315  * Register Group : Security Register Group - ALT_L3_SECGRP
316  * Security Register Group
317  *
318  * Registers that control slave security.
319  *
320  */
321 /*
322  * Register : L4 Main Peripherals Security - l4main
323  *
324  * Controls security settings for L4 Main peripherals.
325  *
326  * Register Layout
327  *
328  * Bits | Access | Reset | Description
329  * :-------|:-------|:------|:------------------------
330  * [0] | W | 0x0 | SPI Slave 0 Security
331  * [1] | W | 0x0 | SPI Slave 1 Security
332  * [2] | W | 0x0 | DMA Secure Security
333  * [3] | W | 0x0 | DMA Non-secure Security
334  * [31:4] | ??? | 0x0 | *UNDEFINED*
335  *
336  */
337 /*
338  * Field : SPI Slave 0 Security - spis0
339  *
340  * Controls whether secure or non-secure masters can access the SPI Slave 0 slave.
341  *
342  * Field Enumeration Values:
343  *
344  * Enum | Value | Description
345  * :------------------------------------|:------|:----------------------------------------------
346  * ALT_L3_SEC_L4MAIN_SPIS0_E_SECURE | 0x0 | The slave can only be accessed by a secure
347  * : | | master.
348  * ALT_L3_SEC_L4MAIN_SPIS0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
349  * : | | non-secure masters.
350  *
351  * Field Access Macros:
352  *
353  */
354 /*
355  * Enumerated value for register field ALT_L3_SEC_L4MAIN_SPIS0
356  *
357  * The slave can only be accessed by a secure master.
358  */
359 #define ALT_L3_SEC_L4MAIN_SPIS0_E_SECURE 0x0
360 /*
361  * Enumerated value for register field ALT_L3_SEC_L4MAIN_SPIS0
362  *
363  * The slave can only be accessed by a secure or non-secure masters.
364  */
365 #define ALT_L3_SEC_L4MAIN_SPIS0_E_NONSECURE 0x1
366 
367 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MAIN_SPIS0 register field. */
368 #define ALT_L3_SEC_L4MAIN_SPIS0_LSB 0
369 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MAIN_SPIS0 register field. */
370 #define ALT_L3_SEC_L4MAIN_SPIS0_MSB 0
371 /* The width in bits of the ALT_L3_SEC_L4MAIN_SPIS0 register field. */
372 #define ALT_L3_SEC_L4MAIN_SPIS0_WIDTH 1
373 /* The mask used to set the ALT_L3_SEC_L4MAIN_SPIS0 register field value. */
374 #define ALT_L3_SEC_L4MAIN_SPIS0_SET_MSK 0x00000001
375 /* The mask used to clear the ALT_L3_SEC_L4MAIN_SPIS0 register field value. */
376 #define ALT_L3_SEC_L4MAIN_SPIS0_CLR_MSK 0xfffffffe
377 /* The reset value of the ALT_L3_SEC_L4MAIN_SPIS0 register field. */
378 #define ALT_L3_SEC_L4MAIN_SPIS0_RESET 0x0
379 /* Extracts the ALT_L3_SEC_L4MAIN_SPIS0 field value from a register. */
380 #define ALT_L3_SEC_L4MAIN_SPIS0_GET(value) (((value) & 0x00000001) >> 0)
381 /* Produces a ALT_L3_SEC_L4MAIN_SPIS0 register field value suitable for setting the register. */
382 #define ALT_L3_SEC_L4MAIN_SPIS0_SET(value) (((value) << 0) & 0x00000001)
383 
384 /*
385  * Field : SPI Slave 1 Security - spis1
386  *
387  * Controls whether secure or non-secure masters can access the SPI Slave 1 slave.
388  *
389  * Field Enumeration Values:
390  *
391  * Enum | Value | Description
392  * :------------------------------------|:------|:----------------------------------------------
393  * ALT_L3_SEC_L4MAIN_SPIS1_E_SECURE | 0x0 | The slave can only be accessed by a secure
394  * : | | master.
395  * ALT_L3_SEC_L4MAIN_SPIS1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
396  * : | | non-secure masters.
397  *
398  * Field Access Macros:
399  *
400  */
401 /*
402  * Enumerated value for register field ALT_L3_SEC_L4MAIN_SPIS1
403  *
404  * The slave can only be accessed by a secure master.
405  */
406 #define ALT_L3_SEC_L4MAIN_SPIS1_E_SECURE 0x0
407 /*
408  * Enumerated value for register field ALT_L3_SEC_L4MAIN_SPIS1
409  *
410  * The slave can only be accessed by a secure or non-secure masters.
411  */
412 #define ALT_L3_SEC_L4MAIN_SPIS1_E_NONSECURE 0x1
413 
414 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MAIN_SPIS1 register field. */
415 #define ALT_L3_SEC_L4MAIN_SPIS1_LSB 1
416 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MAIN_SPIS1 register field. */
417 #define ALT_L3_SEC_L4MAIN_SPIS1_MSB 1
418 /* The width in bits of the ALT_L3_SEC_L4MAIN_SPIS1 register field. */
419 #define ALT_L3_SEC_L4MAIN_SPIS1_WIDTH 1
420 /* The mask used to set the ALT_L3_SEC_L4MAIN_SPIS1 register field value. */
421 #define ALT_L3_SEC_L4MAIN_SPIS1_SET_MSK 0x00000002
422 /* The mask used to clear the ALT_L3_SEC_L4MAIN_SPIS1 register field value. */
423 #define ALT_L3_SEC_L4MAIN_SPIS1_CLR_MSK 0xfffffffd
424 /* The reset value of the ALT_L3_SEC_L4MAIN_SPIS1 register field. */
425 #define ALT_L3_SEC_L4MAIN_SPIS1_RESET 0x0
426 /* Extracts the ALT_L3_SEC_L4MAIN_SPIS1 field value from a register. */
427 #define ALT_L3_SEC_L4MAIN_SPIS1_GET(value) (((value) & 0x00000002) >> 1)
428 /* Produces a ALT_L3_SEC_L4MAIN_SPIS1 register field value suitable for setting the register. */
429 #define ALT_L3_SEC_L4MAIN_SPIS1_SET(value) (((value) << 1) & 0x00000002)
430 
431 /*
432  * Field : DMA Secure Security - dmasecure
433  *
434  * Controls whether secure or non-secure masters can access the DMA Secure slave.
435  *
436  * Field Enumeration Values:
437  *
438  * Enum | Value | Description
439  * :----------------------------------------|:------|:----------------------------------------------
440  * ALT_L3_SEC_L4MAIN_DMASECURE_E_SECURE | 0x0 | The slave can only be accessed by a secure
441  * : | | master.
442  * ALT_L3_SEC_L4MAIN_DMASECURE_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
443  * : | | non-secure masters.
444  *
445  * Field Access Macros:
446  *
447  */
448 /*
449  * Enumerated value for register field ALT_L3_SEC_L4MAIN_DMASECURE
450  *
451  * The slave can only be accessed by a secure master.
452  */
453 #define ALT_L3_SEC_L4MAIN_DMASECURE_E_SECURE 0x0
454 /*
455  * Enumerated value for register field ALT_L3_SEC_L4MAIN_DMASECURE
456  *
457  * The slave can only be accessed by a secure or non-secure masters.
458  */
459 #define ALT_L3_SEC_L4MAIN_DMASECURE_E_NONSECURE 0x1
460 
461 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MAIN_DMASECURE register field. */
462 #define ALT_L3_SEC_L4MAIN_DMASECURE_LSB 2
463 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MAIN_DMASECURE register field. */
464 #define ALT_L3_SEC_L4MAIN_DMASECURE_MSB 2
465 /* The width in bits of the ALT_L3_SEC_L4MAIN_DMASECURE register field. */
466 #define ALT_L3_SEC_L4MAIN_DMASECURE_WIDTH 1
467 /* The mask used to set the ALT_L3_SEC_L4MAIN_DMASECURE register field value. */
468 #define ALT_L3_SEC_L4MAIN_DMASECURE_SET_MSK 0x00000004
469 /* The mask used to clear the ALT_L3_SEC_L4MAIN_DMASECURE register field value. */
470 #define ALT_L3_SEC_L4MAIN_DMASECURE_CLR_MSK 0xfffffffb
471 /* The reset value of the ALT_L3_SEC_L4MAIN_DMASECURE register field. */
472 #define ALT_L3_SEC_L4MAIN_DMASECURE_RESET 0x0
473 /* Extracts the ALT_L3_SEC_L4MAIN_DMASECURE field value from a register. */
474 #define ALT_L3_SEC_L4MAIN_DMASECURE_GET(value) (((value) & 0x00000004) >> 2)
475 /* Produces a ALT_L3_SEC_L4MAIN_DMASECURE register field value suitable for setting the register. */
476 #define ALT_L3_SEC_L4MAIN_DMASECURE_SET(value) (((value) << 2) & 0x00000004)
477 
478 /*
479  * Field : DMA Non-secure Security - dmanonsecure
480  *
481  * Controls whether secure or non-secure masters can access the DMA Non-secure
482  * slave.
483  *
484  * Field Enumeration Values:
485  *
486  * Enum | Value | Description
487  * :-------------------------------------------|:------|:----------------------------------------------
488  * ALT_L3_SEC_L4MAIN_DMANONSECURE_E_SECURE | 0x0 | The slave can only be accessed by a secure
489  * : | | master.
490  * ALT_L3_SEC_L4MAIN_DMANONSECURE_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
491  * : | | non-secure masters.
492  *
493  * Field Access Macros:
494  *
495  */
496 /*
497  * Enumerated value for register field ALT_L3_SEC_L4MAIN_DMANONSECURE
498  *
499  * The slave can only be accessed by a secure master.
500  */
501 #define ALT_L3_SEC_L4MAIN_DMANONSECURE_E_SECURE 0x0
502 /*
503  * Enumerated value for register field ALT_L3_SEC_L4MAIN_DMANONSECURE
504  *
505  * The slave can only be accessed by a secure or non-secure masters.
506  */
507 #define ALT_L3_SEC_L4MAIN_DMANONSECURE_E_NONSECURE 0x1
508 
509 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MAIN_DMANONSECURE register field. */
510 #define ALT_L3_SEC_L4MAIN_DMANONSECURE_LSB 3
511 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MAIN_DMANONSECURE register field. */
512 #define ALT_L3_SEC_L4MAIN_DMANONSECURE_MSB 3
513 /* The width in bits of the ALT_L3_SEC_L4MAIN_DMANONSECURE register field. */
514 #define ALT_L3_SEC_L4MAIN_DMANONSECURE_WIDTH 1
515 /* The mask used to set the ALT_L3_SEC_L4MAIN_DMANONSECURE register field value. */
516 #define ALT_L3_SEC_L4MAIN_DMANONSECURE_SET_MSK 0x00000008
517 /* The mask used to clear the ALT_L3_SEC_L4MAIN_DMANONSECURE register field value. */
518 #define ALT_L3_SEC_L4MAIN_DMANONSECURE_CLR_MSK 0xfffffff7
519 /* The reset value of the ALT_L3_SEC_L4MAIN_DMANONSECURE register field. */
520 #define ALT_L3_SEC_L4MAIN_DMANONSECURE_RESET 0x0
521 /* Extracts the ALT_L3_SEC_L4MAIN_DMANONSECURE field value from a register. */
522 #define ALT_L3_SEC_L4MAIN_DMANONSECURE_GET(value) (((value) & 0x00000008) >> 3)
523 /* Produces a ALT_L3_SEC_L4MAIN_DMANONSECURE register field value suitable for setting the register. */
524 #define ALT_L3_SEC_L4MAIN_DMANONSECURE_SET(value) (((value) << 3) & 0x00000008)
525 
526 #ifndef __ASSEMBLY__
527 /*
528  * WARNING: The C register and register group struct declarations are provided for
529  * convenience and illustrative purposes. They should, however, be used with
530  * caution as the C language standard provides no guarantees about the alignment or
531  * atomicity of device memory accesses. The recommended practice for writing
532  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
533  * alt_write_word() functions.
534  *
535  * The struct declaration for register ALT_L3_SEC_L4MAIN.
536  */
538 {
539  uint32_t spis0 : 1; /* SPI Slave 0 Security */
540  uint32_t spis1 : 1; /* SPI Slave 1 Security */
541  uint32_t dmasecure : 1; /* DMA Secure Security */
542  uint32_t dmanonsecure : 1; /* DMA Non-secure Security */
543  uint32_t : 28; /* *UNDEFINED* */
544 };
545 
546 /* The typedef declaration for register ALT_L3_SEC_L4MAIN. */
547 typedef volatile struct ALT_L3_SEC_L4MAIN_s ALT_L3_SEC_L4MAIN_t;
548 #endif /* __ASSEMBLY__ */
549 
550 /* The byte offset of the ALT_L3_SEC_L4MAIN register from the beginning of the component. */
551 #define ALT_L3_SEC_L4MAIN_OFST 0x0
552 
553 /*
554  * Register : L4 SP Peripherals Security - l4sp
555  *
556  * Controls security settings for L4 SP peripherals.
557  *
558  * Register Layout
559  *
560  * Bits | Access | Reset | Description
561  * :--------|:-------|:------|:-------------------------
562  * [0] | W | 0x0 | SDRAM Registers Security
563  * [1] | W | 0x0 | SP Timer 0 Security
564  * [2] | W | 0x0 | I2C0 Security
565  * [3] | W | 0x0 | I2C1 Security
566  * [4] | W | 0x0 | I2C2 (EMAC 0) Security
567  * [5] | W | 0x0 | I2C3 (EMAC 1) Security
568  * [6] | W | 0x0 | UART 0 Security
569  * [7] | W | 0x0 | UART 1 Security
570  * [8] | W | 0x0 | CAN 0 Security
571  * [9] | W | 0x0 | CAN 1 Security
572  * [10] | W | 0x0 | SP Timer 1 Security
573  * [31:11] | ??? | 0x0 | *UNDEFINED*
574  *
575  */
576 /*
577  * Field : SDRAM Registers Security - sdrregs
578  *
579  * Controls whether secure or non-secure masters can access the SDRAM Registers
580  * slave.
581  *
582  * Field Enumeration Values:
583  *
584  * Enum | Value | Description
585  * :------------------------------------|:------|:----------------------------------------------
586  * ALT_L3_SEC_L4SP_SDRREGS_E_SECURE | 0x0 | The slave can only be accessed by a secure
587  * : | | master.
588  * ALT_L3_SEC_L4SP_SDRREGS_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
589  * : | | non-secure masters.
590  *
591  * Field Access Macros:
592  *
593  */
594 /*
595  * Enumerated value for register field ALT_L3_SEC_L4SP_SDRREGS
596  *
597  * The slave can only be accessed by a secure master.
598  */
599 #define ALT_L3_SEC_L4SP_SDRREGS_E_SECURE 0x0
600 /*
601  * Enumerated value for register field ALT_L3_SEC_L4SP_SDRREGS
602  *
603  * The slave can only be accessed by a secure or non-secure masters.
604  */
605 #define ALT_L3_SEC_L4SP_SDRREGS_E_NONSECURE 0x1
606 
607 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_SDRREGS register field. */
608 #define ALT_L3_SEC_L4SP_SDRREGS_LSB 0
609 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_SDRREGS register field. */
610 #define ALT_L3_SEC_L4SP_SDRREGS_MSB 0
611 /* The width in bits of the ALT_L3_SEC_L4SP_SDRREGS register field. */
612 #define ALT_L3_SEC_L4SP_SDRREGS_WIDTH 1
613 /* The mask used to set the ALT_L3_SEC_L4SP_SDRREGS register field value. */
614 #define ALT_L3_SEC_L4SP_SDRREGS_SET_MSK 0x00000001
615 /* The mask used to clear the ALT_L3_SEC_L4SP_SDRREGS register field value. */
616 #define ALT_L3_SEC_L4SP_SDRREGS_CLR_MSK 0xfffffffe
617 /* The reset value of the ALT_L3_SEC_L4SP_SDRREGS register field. */
618 #define ALT_L3_SEC_L4SP_SDRREGS_RESET 0x0
619 /* Extracts the ALT_L3_SEC_L4SP_SDRREGS field value from a register. */
620 #define ALT_L3_SEC_L4SP_SDRREGS_GET(value) (((value) & 0x00000001) >> 0)
621 /* Produces a ALT_L3_SEC_L4SP_SDRREGS register field value suitable for setting the register. */
622 #define ALT_L3_SEC_L4SP_SDRREGS_SET(value) (((value) << 0) & 0x00000001)
623 
624 /*
625  * Field : SP Timer 0 Security - sptimer0
626  *
627  * Controls whether secure or non-secure masters can access the SP Timer 0 slave.
628  *
629  * Field Enumeration Values:
630  *
631  * Enum | Value | Description
632  * :-----------------------------------|:------|:----------------------------------------------
633  * ALT_L3_SEC_L4SP_SPTMR0_E_SECURE | 0x0 | The slave can only be accessed by a secure
634  * : | | master.
635  * ALT_L3_SEC_L4SP_SPTMR0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
636  * : | | non-secure masters.
637  *
638  * Field Access Macros:
639  *
640  */
641 /*
642  * Enumerated value for register field ALT_L3_SEC_L4SP_SPTMR0
643  *
644  * The slave can only be accessed by a secure master.
645  */
646 #define ALT_L3_SEC_L4SP_SPTMR0_E_SECURE 0x0
647 /*
648  * Enumerated value for register field ALT_L3_SEC_L4SP_SPTMR0
649  *
650  * The slave can only be accessed by a secure or non-secure masters.
651  */
652 #define ALT_L3_SEC_L4SP_SPTMR0_E_NONSECURE 0x1
653 
654 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_SPTMR0 register field. */
655 #define ALT_L3_SEC_L4SP_SPTMR0_LSB 1
656 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_SPTMR0 register field. */
657 #define ALT_L3_SEC_L4SP_SPTMR0_MSB 1
658 /* The width in bits of the ALT_L3_SEC_L4SP_SPTMR0 register field. */
659 #define ALT_L3_SEC_L4SP_SPTMR0_WIDTH 1
660 /* The mask used to set the ALT_L3_SEC_L4SP_SPTMR0 register field value. */
661 #define ALT_L3_SEC_L4SP_SPTMR0_SET_MSK 0x00000002
662 /* The mask used to clear the ALT_L3_SEC_L4SP_SPTMR0 register field value. */
663 #define ALT_L3_SEC_L4SP_SPTMR0_CLR_MSK 0xfffffffd
664 /* The reset value of the ALT_L3_SEC_L4SP_SPTMR0 register field. */
665 #define ALT_L3_SEC_L4SP_SPTMR0_RESET 0x0
666 /* Extracts the ALT_L3_SEC_L4SP_SPTMR0 field value from a register. */
667 #define ALT_L3_SEC_L4SP_SPTMR0_GET(value) (((value) & 0x00000002) >> 1)
668 /* Produces a ALT_L3_SEC_L4SP_SPTMR0 register field value suitable for setting the register. */
669 #define ALT_L3_SEC_L4SP_SPTMR0_SET(value) (((value) << 1) & 0x00000002)
670 
671 /*
672  * Field : I2C0 Security - i2c0
673  *
674  * Controls whether secure or non-secure masters can access the I2C0 slave.
675  *
676  * Field Enumeration Values:
677  *
678  * Enum | Value | Description
679  * :---------------------------------|:------|:----------------------------------------------
680  * ALT_L3_SEC_L4SP_I2C0_E_SECURE | 0x0 | The slave can only be accessed by a secure
681  * : | | master.
682  * ALT_L3_SEC_L4SP_I2C0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
683  * : | | non-secure masters.
684  *
685  * Field Access Macros:
686  *
687  */
688 /*
689  * Enumerated value for register field ALT_L3_SEC_L4SP_I2C0
690  *
691  * The slave can only be accessed by a secure master.
692  */
693 #define ALT_L3_SEC_L4SP_I2C0_E_SECURE 0x0
694 /*
695  * Enumerated value for register field ALT_L3_SEC_L4SP_I2C0
696  *
697  * The slave can only be accessed by a secure or non-secure masters.
698  */
699 #define ALT_L3_SEC_L4SP_I2C0_E_NONSECURE 0x1
700 
701 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_I2C0 register field. */
702 #define ALT_L3_SEC_L4SP_I2C0_LSB 2
703 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_I2C0 register field. */
704 #define ALT_L3_SEC_L4SP_I2C0_MSB 2
705 /* The width in bits of the ALT_L3_SEC_L4SP_I2C0 register field. */
706 #define ALT_L3_SEC_L4SP_I2C0_WIDTH 1
707 /* The mask used to set the ALT_L3_SEC_L4SP_I2C0 register field value. */
708 #define ALT_L3_SEC_L4SP_I2C0_SET_MSK 0x00000004
709 /* The mask used to clear the ALT_L3_SEC_L4SP_I2C0 register field value. */
710 #define ALT_L3_SEC_L4SP_I2C0_CLR_MSK 0xfffffffb
711 /* The reset value of the ALT_L3_SEC_L4SP_I2C0 register field. */
712 #define ALT_L3_SEC_L4SP_I2C0_RESET 0x0
713 /* Extracts the ALT_L3_SEC_L4SP_I2C0 field value from a register. */
714 #define ALT_L3_SEC_L4SP_I2C0_GET(value) (((value) & 0x00000004) >> 2)
715 /* Produces a ALT_L3_SEC_L4SP_I2C0 register field value suitable for setting the register. */
716 #define ALT_L3_SEC_L4SP_I2C0_SET(value) (((value) << 2) & 0x00000004)
717 
718 /*
719  * Field : I2C1 Security - i2c1
720  *
721  * Controls whether secure or non-secure masters can access the I2C1 slave.
722  *
723  * Field Enumeration Values:
724  *
725  * Enum | Value | Description
726  * :---------------------------------|:------|:----------------------------------------------
727  * ALT_L3_SEC_L4SP_I2C1_E_SECURE | 0x0 | The slave can only be accessed by a secure
728  * : | | master.
729  * ALT_L3_SEC_L4SP_I2C1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
730  * : | | non-secure masters.
731  *
732  * Field Access Macros:
733  *
734  */
735 /*
736  * Enumerated value for register field ALT_L3_SEC_L4SP_I2C1
737  *
738  * The slave can only be accessed by a secure master.
739  */
740 #define ALT_L3_SEC_L4SP_I2C1_E_SECURE 0x0
741 /*
742  * Enumerated value for register field ALT_L3_SEC_L4SP_I2C1
743  *
744  * The slave can only be accessed by a secure or non-secure masters.
745  */
746 #define ALT_L3_SEC_L4SP_I2C1_E_NONSECURE 0x1
747 
748 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_I2C1 register field. */
749 #define ALT_L3_SEC_L4SP_I2C1_LSB 3
750 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_I2C1 register field. */
751 #define ALT_L3_SEC_L4SP_I2C1_MSB 3
752 /* The width in bits of the ALT_L3_SEC_L4SP_I2C1 register field. */
753 #define ALT_L3_SEC_L4SP_I2C1_WIDTH 1
754 /* The mask used to set the ALT_L3_SEC_L4SP_I2C1 register field value. */
755 #define ALT_L3_SEC_L4SP_I2C1_SET_MSK 0x00000008
756 /* The mask used to clear the ALT_L3_SEC_L4SP_I2C1 register field value. */
757 #define ALT_L3_SEC_L4SP_I2C1_CLR_MSK 0xfffffff7
758 /* The reset value of the ALT_L3_SEC_L4SP_I2C1 register field. */
759 #define ALT_L3_SEC_L4SP_I2C1_RESET 0x0
760 /* Extracts the ALT_L3_SEC_L4SP_I2C1 field value from a register. */
761 #define ALT_L3_SEC_L4SP_I2C1_GET(value) (((value) & 0x00000008) >> 3)
762 /* Produces a ALT_L3_SEC_L4SP_I2C1 register field value suitable for setting the register. */
763 #define ALT_L3_SEC_L4SP_I2C1_SET(value) (((value) << 3) & 0x00000008)
764 
765 /*
766  * Field : I2C2 (EMAC 0) Security - i2c2
767  *
768  * Controls whether secure or non-secure masters can access the I2C2 (EMAC 0)
769  * slave.
770  *
771  * Field Enumeration Values:
772  *
773  * Enum | Value | Description
774  * :---------------------------------|:------|:----------------------------------------------
775  * ALT_L3_SEC_L4SP_I2C2_E_SECURE | 0x0 | The slave can only be accessed by a secure
776  * : | | master.
777  * ALT_L3_SEC_L4SP_I2C2_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
778  * : | | non-secure masters.
779  *
780  * Field Access Macros:
781  *
782  */
783 /*
784  * Enumerated value for register field ALT_L3_SEC_L4SP_I2C2
785  *
786  * The slave can only be accessed by a secure master.
787  */
788 #define ALT_L3_SEC_L4SP_I2C2_E_SECURE 0x0
789 /*
790  * Enumerated value for register field ALT_L3_SEC_L4SP_I2C2
791  *
792  * The slave can only be accessed by a secure or non-secure masters.
793  */
794 #define ALT_L3_SEC_L4SP_I2C2_E_NONSECURE 0x1
795 
796 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_I2C2 register field. */
797 #define ALT_L3_SEC_L4SP_I2C2_LSB 4
798 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_I2C2 register field. */
799 #define ALT_L3_SEC_L4SP_I2C2_MSB 4
800 /* The width in bits of the ALT_L3_SEC_L4SP_I2C2 register field. */
801 #define ALT_L3_SEC_L4SP_I2C2_WIDTH 1
802 /* The mask used to set the ALT_L3_SEC_L4SP_I2C2 register field value. */
803 #define ALT_L3_SEC_L4SP_I2C2_SET_MSK 0x00000010
804 /* The mask used to clear the ALT_L3_SEC_L4SP_I2C2 register field value. */
805 #define ALT_L3_SEC_L4SP_I2C2_CLR_MSK 0xffffffef
806 /* The reset value of the ALT_L3_SEC_L4SP_I2C2 register field. */
807 #define ALT_L3_SEC_L4SP_I2C2_RESET 0x0
808 /* Extracts the ALT_L3_SEC_L4SP_I2C2 field value from a register. */
809 #define ALT_L3_SEC_L4SP_I2C2_GET(value) (((value) & 0x00000010) >> 4)
810 /* Produces a ALT_L3_SEC_L4SP_I2C2 register field value suitable for setting the register. */
811 #define ALT_L3_SEC_L4SP_I2C2_SET(value) (((value) << 4) & 0x00000010)
812 
813 /*
814  * Field : I2C3 (EMAC 1) Security - i2c3
815  *
816  * Controls whether secure or non-secure masters can access the I2C3 (EMAC 1)
817  * slave.
818  *
819  * Field Enumeration Values:
820  *
821  * Enum | Value | Description
822  * :---------------------------------|:------|:----------------------------------------------
823  * ALT_L3_SEC_L4SP_I2C3_E_SECURE | 0x0 | The slave can only be accessed by a secure
824  * : | | master.
825  * ALT_L3_SEC_L4SP_I2C3_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
826  * : | | non-secure masters.
827  *
828  * Field Access Macros:
829  *
830  */
831 /*
832  * Enumerated value for register field ALT_L3_SEC_L4SP_I2C3
833  *
834  * The slave can only be accessed by a secure master.
835  */
836 #define ALT_L3_SEC_L4SP_I2C3_E_SECURE 0x0
837 /*
838  * Enumerated value for register field ALT_L3_SEC_L4SP_I2C3
839  *
840  * The slave can only be accessed by a secure or non-secure masters.
841  */
842 #define ALT_L3_SEC_L4SP_I2C3_E_NONSECURE 0x1
843 
844 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_I2C3 register field. */
845 #define ALT_L3_SEC_L4SP_I2C3_LSB 5
846 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_I2C3 register field. */
847 #define ALT_L3_SEC_L4SP_I2C3_MSB 5
848 /* The width in bits of the ALT_L3_SEC_L4SP_I2C3 register field. */
849 #define ALT_L3_SEC_L4SP_I2C3_WIDTH 1
850 /* The mask used to set the ALT_L3_SEC_L4SP_I2C3 register field value. */
851 #define ALT_L3_SEC_L4SP_I2C3_SET_MSK 0x00000020
852 /* The mask used to clear the ALT_L3_SEC_L4SP_I2C3 register field value. */
853 #define ALT_L3_SEC_L4SP_I2C3_CLR_MSK 0xffffffdf
854 /* The reset value of the ALT_L3_SEC_L4SP_I2C3 register field. */
855 #define ALT_L3_SEC_L4SP_I2C3_RESET 0x0
856 /* Extracts the ALT_L3_SEC_L4SP_I2C3 field value from a register. */
857 #define ALT_L3_SEC_L4SP_I2C3_GET(value) (((value) & 0x00000020) >> 5)
858 /* Produces a ALT_L3_SEC_L4SP_I2C3 register field value suitable for setting the register. */
859 #define ALT_L3_SEC_L4SP_I2C3_SET(value) (((value) << 5) & 0x00000020)
860 
861 /*
862  * Field : UART 0 Security - uart0
863  *
864  * Controls whether secure or non-secure masters can access the UART 0 slave.
865  *
866  * Field Enumeration Values:
867  *
868  * Enum | Value | Description
869  * :----------------------------------|:------|:----------------------------------------------
870  * ALT_L3_SEC_L4SP_UART0_E_SECURE | 0x0 | The slave can only be accessed by a secure
871  * : | | master.
872  * ALT_L3_SEC_L4SP_UART0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
873  * : | | non-secure masters.
874  *
875  * Field Access Macros:
876  *
877  */
878 /*
879  * Enumerated value for register field ALT_L3_SEC_L4SP_UART0
880  *
881  * The slave can only be accessed by a secure master.
882  */
883 #define ALT_L3_SEC_L4SP_UART0_E_SECURE 0x0
884 /*
885  * Enumerated value for register field ALT_L3_SEC_L4SP_UART0
886  *
887  * The slave can only be accessed by a secure or non-secure masters.
888  */
889 #define ALT_L3_SEC_L4SP_UART0_E_NONSECURE 0x1
890 
891 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_UART0 register field. */
892 #define ALT_L3_SEC_L4SP_UART0_LSB 6
893 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_UART0 register field. */
894 #define ALT_L3_SEC_L4SP_UART0_MSB 6
895 /* The width in bits of the ALT_L3_SEC_L4SP_UART0 register field. */
896 #define ALT_L3_SEC_L4SP_UART0_WIDTH 1
897 /* The mask used to set the ALT_L3_SEC_L4SP_UART0 register field value. */
898 #define ALT_L3_SEC_L4SP_UART0_SET_MSK 0x00000040
899 /* The mask used to clear the ALT_L3_SEC_L4SP_UART0 register field value. */
900 #define ALT_L3_SEC_L4SP_UART0_CLR_MSK 0xffffffbf
901 /* The reset value of the ALT_L3_SEC_L4SP_UART0 register field. */
902 #define ALT_L3_SEC_L4SP_UART0_RESET 0x0
903 /* Extracts the ALT_L3_SEC_L4SP_UART0 field value from a register. */
904 #define ALT_L3_SEC_L4SP_UART0_GET(value) (((value) & 0x00000040) >> 6)
905 /* Produces a ALT_L3_SEC_L4SP_UART0 register field value suitable for setting the register. */
906 #define ALT_L3_SEC_L4SP_UART0_SET(value) (((value) << 6) & 0x00000040)
907 
908 /*
909  * Field : UART 1 Security - uart1
910  *
911  * Controls whether secure or non-secure masters can access the UART 1 slave.
912  *
913  * Field Enumeration Values:
914  *
915  * Enum | Value | Description
916  * :----------------------------------|:------|:----------------------------------------------
917  * ALT_L3_SEC_L4SP_UART1_E_SECURE | 0x0 | The slave can only be accessed by a secure
918  * : | | master.
919  * ALT_L3_SEC_L4SP_UART1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
920  * : | | non-secure masters.
921  *
922  * Field Access Macros:
923  *
924  */
925 /*
926  * Enumerated value for register field ALT_L3_SEC_L4SP_UART1
927  *
928  * The slave can only be accessed by a secure master.
929  */
930 #define ALT_L3_SEC_L4SP_UART1_E_SECURE 0x0
931 /*
932  * Enumerated value for register field ALT_L3_SEC_L4SP_UART1
933  *
934  * The slave can only be accessed by a secure or non-secure masters.
935  */
936 #define ALT_L3_SEC_L4SP_UART1_E_NONSECURE 0x1
937 
938 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_UART1 register field. */
939 #define ALT_L3_SEC_L4SP_UART1_LSB 7
940 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_UART1 register field. */
941 #define ALT_L3_SEC_L4SP_UART1_MSB 7
942 /* The width in bits of the ALT_L3_SEC_L4SP_UART1 register field. */
943 #define ALT_L3_SEC_L4SP_UART1_WIDTH 1
944 /* The mask used to set the ALT_L3_SEC_L4SP_UART1 register field value. */
945 #define ALT_L3_SEC_L4SP_UART1_SET_MSK 0x00000080
946 /* The mask used to clear the ALT_L3_SEC_L4SP_UART1 register field value. */
947 #define ALT_L3_SEC_L4SP_UART1_CLR_MSK 0xffffff7f
948 /* The reset value of the ALT_L3_SEC_L4SP_UART1 register field. */
949 #define ALT_L3_SEC_L4SP_UART1_RESET 0x0
950 /* Extracts the ALT_L3_SEC_L4SP_UART1 field value from a register. */
951 #define ALT_L3_SEC_L4SP_UART1_GET(value) (((value) & 0x00000080) >> 7)
952 /* Produces a ALT_L3_SEC_L4SP_UART1 register field value suitable for setting the register. */
953 #define ALT_L3_SEC_L4SP_UART1_SET(value) (((value) << 7) & 0x00000080)
954 
955 /*
956  * Field : CAN 0 Security - can0
957  *
958  * Controls whether secure or non-secure masters can access the CAN 0 slave.
959  *
960  * Field Enumeration Values:
961  *
962  * Enum | Value | Description
963  * :---------------------------------|:------|:----------------------------------------------
964  * ALT_L3_SEC_L4SP_CAN0_E_SECURE | 0x0 | The slave can only be accessed by a secure
965  * : | | master.
966  * ALT_L3_SEC_L4SP_CAN0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
967  * : | | non-secure masters.
968  *
969  * Field Access Macros:
970  *
971  */
972 /*
973  * Enumerated value for register field ALT_L3_SEC_L4SP_CAN0
974  *
975  * The slave can only be accessed by a secure master.
976  */
977 #define ALT_L3_SEC_L4SP_CAN0_E_SECURE 0x0
978 /*
979  * Enumerated value for register field ALT_L3_SEC_L4SP_CAN0
980  *
981  * The slave can only be accessed by a secure or non-secure masters.
982  */
983 #define ALT_L3_SEC_L4SP_CAN0_E_NONSECURE 0x1
984 
985 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_CAN0 register field. */
986 #define ALT_L3_SEC_L4SP_CAN0_LSB 8
987 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_CAN0 register field. */
988 #define ALT_L3_SEC_L4SP_CAN0_MSB 8
989 /* The width in bits of the ALT_L3_SEC_L4SP_CAN0 register field. */
990 #define ALT_L3_SEC_L4SP_CAN0_WIDTH 1
991 /* The mask used to set the ALT_L3_SEC_L4SP_CAN0 register field value. */
992 #define ALT_L3_SEC_L4SP_CAN0_SET_MSK 0x00000100
993 /* The mask used to clear the ALT_L3_SEC_L4SP_CAN0 register field value. */
994 #define ALT_L3_SEC_L4SP_CAN0_CLR_MSK 0xfffffeff
995 /* The reset value of the ALT_L3_SEC_L4SP_CAN0 register field. */
996 #define ALT_L3_SEC_L4SP_CAN0_RESET 0x0
997 /* Extracts the ALT_L3_SEC_L4SP_CAN0 field value from a register. */
998 #define ALT_L3_SEC_L4SP_CAN0_GET(value) (((value) & 0x00000100) >> 8)
999 /* Produces a ALT_L3_SEC_L4SP_CAN0 register field value suitable for setting the register. */
1000 #define ALT_L3_SEC_L4SP_CAN0_SET(value) (((value) << 8) & 0x00000100)
1001 
1002 /*
1003  * Field : CAN 1 Security - can1
1004  *
1005  * Controls whether secure or non-secure masters can access the CAN 1 slave.
1006  *
1007  * Field Enumeration Values:
1008  *
1009  * Enum | Value | Description
1010  * :---------------------------------|:------|:----------------------------------------------
1011  * ALT_L3_SEC_L4SP_CAN1_E_SECURE | 0x0 | The slave can only be accessed by a secure
1012  * : | | master.
1013  * ALT_L3_SEC_L4SP_CAN1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1014  * : | | non-secure masters.
1015  *
1016  * Field Access Macros:
1017  *
1018  */
1019 /*
1020  * Enumerated value for register field ALT_L3_SEC_L4SP_CAN1
1021  *
1022  * The slave can only be accessed by a secure master.
1023  */
1024 #define ALT_L3_SEC_L4SP_CAN1_E_SECURE 0x0
1025 /*
1026  * Enumerated value for register field ALT_L3_SEC_L4SP_CAN1
1027  *
1028  * The slave can only be accessed by a secure or non-secure masters.
1029  */
1030 #define ALT_L3_SEC_L4SP_CAN1_E_NONSECURE 0x1
1031 
1032 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_CAN1 register field. */
1033 #define ALT_L3_SEC_L4SP_CAN1_LSB 9
1034 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_CAN1 register field. */
1035 #define ALT_L3_SEC_L4SP_CAN1_MSB 9
1036 /* The width in bits of the ALT_L3_SEC_L4SP_CAN1 register field. */
1037 #define ALT_L3_SEC_L4SP_CAN1_WIDTH 1
1038 /* The mask used to set the ALT_L3_SEC_L4SP_CAN1 register field value. */
1039 #define ALT_L3_SEC_L4SP_CAN1_SET_MSK 0x00000200
1040 /* The mask used to clear the ALT_L3_SEC_L4SP_CAN1 register field value. */
1041 #define ALT_L3_SEC_L4SP_CAN1_CLR_MSK 0xfffffdff
1042 /* The reset value of the ALT_L3_SEC_L4SP_CAN1 register field. */
1043 #define ALT_L3_SEC_L4SP_CAN1_RESET 0x0
1044 /* Extracts the ALT_L3_SEC_L4SP_CAN1 field value from a register. */
1045 #define ALT_L3_SEC_L4SP_CAN1_GET(value) (((value) & 0x00000200) >> 9)
1046 /* Produces a ALT_L3_SEC_L4SP_CAN1 register field value suitable for setting the register. */
1047 #define ALT_L3_SEC_L4SP_CAN1_SET(value) (((value) << 9) & 0x00000200)
1048 
1049 /*
1050  * Field : SP Timer 1 Security - sptimer1
1051  *
1052  * Controls whether secure or non-secure masters can access the SP Timer 1 slave.
1053  *
1054  * Field Enumeration Values:
1055  *
1056  * Enum | Value | Description
1057  * :-----------------------------------|:------|:----------------------------------------------
1058  * ALT_L3_SEC_L4SP_SPTMR1_E_SECURE | 0x0 | The slave can only be accessed by a secure
1059  * : | | master.
1060  * ALT_L3_SEC_L4SP_SPTMR1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1061  * : | | non-secure masters.
1062  *
1063  * Field Access Macros:
1064  *
1065  */
1066 /*
1067  * Enumerated value for register field ALT_L3_SEC_L4SP_SPTMR1
1068  *
1069  * The slave can only be accessed by a secure master.
1070  */
1071 #define ALT_L3_SEC_L4SP_SPTMR1_E_SECURE 0x0
1072 /*
1073  * Enumerated value for register field ALT_L3_SEC_L4SP_SPTMR1
1074  *
1075  * The slave can only be accessed by a secure or non-secure masters.
1076  */
1077 #define ALT_L3_SEC_L4SP_SPTMR1_E_NONSECURE 0x1
1078 
1079 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_SPTMR1 register field. */
1080 #define ALT_L3_SEC_L4SP_SPTMR1_LSB 10
1081 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_SPTMR1 register field. */
1082 #define ALT_L3_SEC_L4SP_SPTMR1_MSB 10
1083 /* The width in bits of the ALT_L3_SEC_L4SP_SPTMR1 register field. */
1084 #define ALT_L3_SEC_L4SP_SPTMR1_WIDTH 1
1085 /* The mask used to set the ALT_L3_SEC_L4SP_SPTMR1 register field value. */
1086 #define ALT_L3_SEC_L4SP_SPTMR1_SET_MSK 0x00000400
1087 /* The mask used to clear the ALT_L3_SEC_L4SP_SPTMR1 register field value. */
1088 #define ALT_L3_SEC_L4SP_SPTMR1_CLR_MSK 0xfffffbff
1089 /* The reset value of the ALT_L3_SEC_L4SP_SPTMR1 register field. */
1090 #define ALT_L3_SEC_L4SP_SPTMR1_RESET 0x0
1091 /* Extracts the ALT_L3_SEC_L4SP_SPTMR1 field value from a register. */
1092 #define ALT_L3_SEC_L4SP_SPTMR1_GET(value) (((value) & 0x00000400) >> 10)
1093 /* Produces a ALT_L3_SEC_L4SP_SPTMR1 register field value suitable for setting the register. */
1094 #define ALT_L3_SEC_L4SP_SPTMR1_SET(value) (((value) << 10) & 0x00000400)
1095 
1096 #ifndef __ASSEMBLY__
1097 /*
1098  * WARNING: The C register and register group struct declarations are provided for
1099  * convenience and illustrative purposes. They should, however, be used with
1100  * caution as the C language standard provides no guarantees about the alignment or
1101  * atomicity of device memory accesses. The recommended practice for writing
1102  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1103  * alt_write_word() functions.
1104  *
1105  * The struct declaration for register ALT_L3_SEC_L4SP.
1106  */
1108 {
1109  uint32_t sdrregs : 1; /* SDRAM Registers Security */
1110  uint32_t sptimer0 : 1; /* SP Timer 0 Security */
1111  uint32_t i2c0 : 1; /* I2C0 Security */
1112  uint32_t i2c1 : 1; /* I2C1 Security */
1113  uint32_t i2c2 : 1; /* I2C2 (EMAC 0) Security */
1114  uint32_t i2c3 : 1; /* I2C3 (EMAC 1) Security */
1115  uint32_t uart0 : 1; /* UART 0 Security */
1116  uint32_t uart1 : 1; /* UART 1 Security */
1117  uint32_t can0 : 1; /* CAN 0 Security */
1118  uint32_t can1 : 1; /* CAN 1 Security */
1119  uint32_t sptimer1 : 1; /* SP Timer 1 Security */
1120  uint32_t : 21; /* *UNDEFINED* */
1121 };
1122 
1123 /* The typedef declaration for register ALT_L3_SEC_L4SP. */
1124 typedef volatile struct ALT_L3_SEC_L4SP_s ALT_L3_SEC_L4SP_t;
1125 #endif /* __ASSEMBLY__ */
1126 
1127 /* The byte offset of the ALT_L3_SEC_L4SP register from the beginning of the component. */
1128 #define ALT_L3_SEC_L4SP_OFST 0x4
1129 
1130 /*
1131  * Register : L4 MP Peripherals Security - l4mp
1132  *
1133  * Controls security settings for L4 MP peripherals.
1134  *
1135  * Register Layout
1136  *
1137  * Bits | Access | Reset | Description
1138  * :--------|:-------|:------|:-------------------------------
1139  * [0] | W | 0x0 | FPGA Manager Register Security
1140  * [1] | W | 0x0 | DAP Security
1141  * [2] | W | 0x0 | QSPI Registers Security
1142  * [3] | W | 0x0 | SDMMC Security
1143  * [4] | W | 0x0 | EMAC 0 Security
1144  * [5] | W | 0x0 | EMAC 1 Security
1145  * [6] | W | 0x0 | ACP ID Mapper Security
1146  * [7] | W | 0x0 | GPIO 0 Security
1147  * [8] | W | 0x0 | GPIO 1 Security
1148  * [9] | W | 0x0 | GPIO 2 Security
1149  * [31:10] | ??? | 0x0 | *UNDEFINED*
1150  *
1151  */
1152 /*
1153  * Field : FPGA Manager Register Security - fpgamgrregs
1154  *
1155  * Controls whether secure or non-secure masters can access the FPGA Manager
1156  * Register slave.
1157  *
1158  * Field Enumeration Values:
1159  *
1160  * Enum | Value | Description
1161  * :------------------------------------|:------|:----------------------------------------------
1162  * ALT_L3_SEC_L4MP_FPGAMGR_E_SECURE | 0x0 | The slave can only be accessed by a secure
1163  * : | | master.
1164  * ALT_L3_SEC_L4MP_FPGAMGR_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1165  * : | | non-secure masters.
1166  *
1167  * Field Access Macros:
1168  *
1169  */
1170 /*
1171  * Enumerated value for register field ALT_L3_SEC_L4MP_FPGAMGR
1172  *
1173  * The slave can only be accessed by a secure master.
1174  */
1175 #define ALT_L3_SEC_L4MP_FPGAMGR_E_SECURE 0x0
1176 /*
1177  * Enumerated value for register field ALT_L3_SEC_L4MP_FPGAMGR
1178  *
1179  * The slave can only be accessed by a secure or non-secure masters.
1180  */
1181 #define ALT_L3_SEC_L4MP_FPGAMGR_E_NONSECURE 0x1
1182 
1183 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_FPGAMGR register field. */
1184 #define ALT_L3_SEC_L4MP_FPGAMGR_LSB 0
1185 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_FPGAMGR register field. */
1186 #define ALT_L3_SEC_L4MP_FPGAMGR_MSB 0
1187 /* The width in bits of the ALT_L3_SEC_L4MP_FPGAMGR register field. */
1188 #define ALT_L3_SEC_L4MP_FPGAMGR_WIDTH 1
1189 /* The mask used to set the ALT_L3_SEC_L4MP_FPGAMGR register field value. */
1190 #define ALT_L3_SEC_L4MP_FPGAMGR_SET_MSK 0x00000001
1191 /* The mask used to clear the ALT_L3_SEC_L4MP_FPGAMGR register field value. */
1192 #define ALT_L3_SEC_L4MP_FPGAMGR_CLR_MSK 0xfffffffe
1193 /* The reset value of the ALT_L3_SEC_L4MP_FPGAMGR register field. */
1194 #define ALT_L3_SEC_L4MP_FPGAMGR_RESET 0x0
1195 /* Extracts the ALT_L3_SEC_L4MP_FPGAMGR field value from a register. */
1196 #define ALT_L3_SEC_L4MP_FPGAMGR_GET(value) (((value) & 0x00000001) >> 0)
1197 /* Produces a ALT_L3_SEC_L4MP_FPGAMGR register field value suitable for setting the register. */
1198 #define ALT_L3_SEC_L4MP_FPGAMGR_SET(value) (((value) << 0) & 0x00000001)
1199 
1200 /*
1201  * Field : DAP Security - dap
1202  *
1203  * Controls whether secure or non-secure masters can access the DAP slave.
1204  *
1205  * Field Enumeration Values:
1206  *
1207  * Enum | Value | Description
1208  * :--------------------------------|:------|:----------------------------------------------
1209  * ALT_L3_SEC_L4MP_DAP_E_SECURE | 0x0 | The slave can only be accessed by a secure
1210  * : | | master.
1211  * ALT_L3_SEC_L4MP_DAP_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1212  * : | | non-secure masters.
1213  *
1214  * Field Access Macros:
1215  *
1216  */
1217 /*
1218  * Enumerated value for register field ALT_L3_SEC_L4MP_DAP
1219  *
1220  * The slave can only be accessed by a secure master.
1221  */
1222 #define ALT_L3_SEC_L4MP_DAP_E_SECURE 0x0
1223 /*
1224  * Enumerated value for register field ALT_L3_SEC_L4MP_DAP
1225  *
1226  * The slave can only be accessed by a secure or non-secure masters.
1227  */
1228 #define ALT_L3_SEC_L4MP_DAP_E_NONSECURE 0x1
1229 
1230 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_DAP register field. */
1231 #define ALT_L3_SEC_L4MP_DAP_LSB 1
1232 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_DAP register field. */
1233 #define ALT_L3_SEC_L4MP_DAP_MSB 1
1234 /* The width in bits of the ALT_L3_SEC_L4MP_DAP register field. */
1235 #define ALT_L3_SEC_L4MP_DAP_WIDTH 1
1236 /* The mask used to set the ALT_L3_SEC_L4MP_DAP register field value. */
1237 #define ALT_L3_SEC_L4MP_DAP_SET_MSK 0x00000002
1238 /* The mask used to clear the ALT_L3_SEC_L4MP_DAP register field value. */
1239 #define ALT_L3_SEC_L4MP_DAP_CLR_MSK 0xfffffffd
1240 /* The reset value of the ALT_L3_SEC_L4MP_DAP register field. */
1241 #define ALT_L3_SEC_L4MP_DAP_RESET 0x0
1242 /* Extracts the ALT_L3_SEC_L4MP_DAP field value from a register. */
1243 #define ALT_L3_SEC_L4MP_DAP_GET(value) (((value) & 0x00000002) >> 1)
1244 /* Produces a ALT_L3_SEC_L4MP_DAP register field value suitable for setting the register. */
1245 #define ALT_L3_SEC_L4MP_DAP_SET(value) (((value) << 1) & 0x00000002)
1246 
1247 /*
1248  * Field : QSPI Registers Security - qspiregs
1249  *
1250  * Controls whether secure or non-secure masters can access the QSPI Registers
1251  * slave.
1252  *
1253  * Field Enumeration Values:
1254  *
1255  * Enum | Value | Description
1256  * :---------------------------------|:------|:----------------------------------------------
1257  * ALT_L3_SEC_L4MP_QSPI_E_SECURE | 0x0 | The slave can only be accessed by a secure
1258  * : | | master.
1259  * ALT_L3_SEC_L4MP_QSPI_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1260  * : | | non-secure masters.
1261  *
1262  * Field Access Macros:
1263  *
1264  */
1265 /*
1266  * Enumerated value for register field ALT_L3_SEC_L4MP_QSPI
1267  *
1268  * The slave can only be accessed by a secure master.
1269  */
1270 #define ALT_L3_SEC_L4MP_QSPI_E_SECURE 0x0
1271 /*
1272  * Enumerated value for register field ALT_L3_SEC_L4MP_QSPI
1273  *
1274  * The slave can only be accessed by a secure or non-secure masters.
1275  */
1276 #define ALT_L3_SEC_L4MP_QSPI_E_NONSECURE 0x1
1277 
1278 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_QSPI register field. */
1279 #define ALT_L3_SEC_L4MP_QSPI_LSB 2
1280 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_QSPI register field. */
1281 #define ALT_L3_SEC_L4MP_QSPI_MSB 2
1282 /* The width in bits of the ALT_L3_SEC_L4MP_QSPI register field. */
1283 #define ALT_L3_SEC_L4MP_QSPI_WIDTH 1
1284 /* The mask used to set the ALT_L3_SEC_L4MP_QSPI register field value. */
1285 #define ALT_L3_SEC_L4MP_QSPI_SET_MSK 0x00000004
1286 /* The mask used to clear the ALT_L3_SEC_L4MP_QSPI register field value. */
1287 #define ALT_L3_SEC_L4MP_QSPI_CLR_MSK 0xfffffffb
1288 /* The reset value of the ALT_L3_SEC_L4MP_QSPI register field. */
1289 #define ALT_L3_SEC_L4MP_QSPI_RESET 0x0
1290 /* Extracts the ALT_L3_SEC_L4MP_QSPI field value from a register. */
1291 #define ALT_L3_SEC_L4MP_QSPI_GET(value) (((value) & 0x00000004) >> 2)
1292 /* Produces a ALT_L3_SEC_L4MP_QSPI register field value suitable for setting the register. */
1293 #define ALT_L3_SEC_L4MP_QSPI_SET(value) (((value) << 2) & 0x00000004)
1294 
1295 /*
1296  * Field : SDMMC Security - sdmmc
1297  *
1298  * Controls whether secure or non-secure masters can access the SDMMC slave.
1299  *
1300  * Field Enumeration Values:
1301  *
1302  * Enum | Value | Description
1303  * :----------------------------------|:------|:----------------------------------------------
1304  * ALT_L3_SEC_L4MP_SDMMC_E_SECURE | 0x0 | The slave can only be accessed by a secure
1305  * : | | master.
1306  * ALT_L3_SEC_L4MP_SDMMC_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1307  * : | | non-secure masters.
1308  *
1309  * Field Access Macros:
1310  *
1311  */
1312 /*
1313  * Enumerated value for register field ALT_L3_SEC_L4MP_SDMMC
1314  *
1315  * The slave can only be accessed by a secure master.
1316  */
1317 #define ALT_L3_SEC_L4MP_SDMMC_E_SECURE 0x0
1318 /*
1319  * Enumerated value for register field ALT_L3_SEC_L4MP_SDMMC
1320  *
1321  * The slave can only be accessed by a secure or non-secure masters.
1322  */
1323 #define ALT_L3_SEC_L4MP_SDMMC_E_NONSECURE 0x1
1324 
1325 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_SDMMC register field. */
1326 #define ALT_L3_SEC_L4MP_SDMMC_LSB 3
1327 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_SDMMC register field. */
1328 #define ALT_L3_SEC_L4MP_SDMMC_MSB 3
1329 /* The width in bits of the ALT_L3_SEC_L4MP_SDMMC register field. */
1330 #define ALT_L3_SEC_L4MP_SDMMC_WIDTH 1
1331 /* The mask used to set the ALT_L3_SEC_L4MP_SDMMC register field value. */
1332 #define ALT_L3_SEC_L4MP_SDMMC_SET_MSK 0x00000008
1333 /* The mask used to clear the ALT_L3_SEC_L4MP_SDMMC register field value. */
1334 #define ALT_L3_SEC_L4MP_SDMMC_CLR_MSK 0xfffffff7
1335 /* The reset value of the ALT_L3_SEC_L4MP_SDMMC register field. */
1336 #define ALT_L3_SEC_L4MP_SDMMC_RESET 0x0
1337 /* Extracts the ALT_L3_SEC_L4MP_SDMMC field value from a register. */
1338 #define ALT_L3_SEC_L4MP_SDMMC_GET(value) (((value) & 0x00000008) >> 3)
1339 /* Produces a ALT_L3_SEC_L4MP_SDMMC register field value suitable for setting the register. */
1340 #define ALT_L3_SEC_L4MP_SDMMC_SET(value) (((value) << 3) & 0x00000008)
1341 
1342 /*
1343  * Field : EMAC 0 Security - emac0
1344  *
1345  * Controls whether secure or non-secure masters can access the EMAC 0 slave.
1346  *
1347  * Field Enumeration Values:
1348  *
1349  * Enum | Value | Description
1350  * :----------------------------------|:------|:----------------------------------------------
1351  * ALT_L3_SEC_L4MP_EMAC0_E_SECURE | 0x0 | The slave can only be accessed by a secure
1352  * : | | master.
1353  * ALT_L3_SEC_L4MP_EMAC0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1354  * : | | non-secure masters.
1355  *
1356  * Field Access Macros:
1357  *
1358  */
1359 /*
1360  * Enumerated value for register field ALT_L3_SEC_L4MP_EMAC0
1361  *
1362  * The slave can only be accessed by a secure master.
1363  */
1364 #define ALT_L3_SEC_L4MP_EMAC0_E_SECURE 0x0
1365 /*
1366  * Enumerated value for register field ALT_L3_SEC_L4MP_EMAC0
1367  *
1368  * The slave can only be accessed by a secure or non-secure masters.
1369  */
1370 #define ALT_L3_SEC_L4MP_EMAC0_E_NONSECURE 0x1
1371 
1372 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_EMAC0 register field. */
1373 #define ALT_L3_SEC_L4MP_EMAC0_LSB 4
1374 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_EMAC0 register field. */
1375 #define ALT_L3_SEC_L4MP_EMAC0_MSB 4
1376 /* The width in bits of the ALT_L3_SEC_L4MP_EMAC0 register field. */
1377 #define ALT_L3_SEC_L4MP_EMAC0_WIDTH 1
1378 /* The mask used to set the ALT_L3_SEC_L4MP_EMAC0 register field value. */
1379 #define ALT_L3_SEC_L4MP_EMAC0_SET_MSK 0x00000010
1380 /* The mask used to clear the ALT_L3_SEC_L4MP_EMAC0 register field value. */
1381 #define ALT_L3_SEC_L4MP_EMAC0_CLR_MSK 0xffffffef
1382 /* The reset value of the ALT_L3_SEC_L4MP_EMAC0 register field. */
1383 #define ALT_L3_SEC_L4MP_EMAC0_RESET 0x0
1384 /* Extracts the ALT_L3_SEC_L4MP_EMAC0 field value from a register. */
1385 #define ALT_L3_SEC_L4MP_EMAC0_GET(value) (((value) & 0x00000010) >> 4)
1386 /* Produces a ALT_L3_SEC_L4MP_EMAC0 register field value suitable for setting the register. */
1387 #define ALT_L3_SEC_L4MP_EMAC0_SET(value) (((value) << 4) & 0x00000010)
1388 
1389 /*
1390  * Field : EMAC 1 Security - emac1
1391  *
1392  * Controls whether secure or non-secure masters can access the EMAC 1 slave.
1393  *
1394  * Field Enumeration Values:
1395  *
1396  * Enum | Value | Description
1397  * :----------------------------------|:------|:----------------------------------------------
1398  * ALT_L3_SEC_L4MP_EMAC1_E_SECURE | 0x0 | The slave can only be accessed by a secure
1399  * : | | master.
1400  * ALT_L3_SEC_L4MP_EMAC1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1401  * : | | non-secure masters.
1402  *
1403  * Field Access Macros:
1404  *
1405  */
1406 /*
1407  * Enumerated value for register field ALT_L3_SEC_L4MP_EMAC1
1408  *
1409  * The slave can only be accessed by a secure master.
1410  */
1411 #define ALT_L3_SEC_L4MP_EMAC1_E_SECURE 0x0
1412 /*
1413  * Enumerated value for register field ALT_L3_SEC_L4MP_EMAC1
1414  *
1415  * The slave can only be accessed by a secure or non-secure masters.
1416  */
1417 #define ALT_L3_SEC_L4MP_EMAC1_E_NONSECURE 0x1
1418 
1419 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_EMAC1 register field. */
1420 #define ALT_L3_SEC_L4MP_EMAC1_LSB 5
1421 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_EMAC1 register field. */
1422 #define ALT_L3_SEC_L4MP_EMAC1_MSB 5
1423 /* The width in bits of the ALT_L3_SEC_L4MP_EMAC1 register field. */
1424 #define ALT_L3_SEC_L4MP_EMAC1_WIDTH 1
1425 /* The mask used to set the ALT_L3_SEC_L4MP_EMAC1 register field value. */
1426 #define ALT_L3_SEC_L4MP_EMAC1_SET_MSK 0x00000020
1427 /* The mask used to clear the ALT_L3_SEC_L4MP_EMAC1 register field value. */
1428 #define ALT_L3_SEC_L4MP_EMAC1_CLR_MSK 0xffffffdf
1429 /* The reset value of the ALT_L3_SEC_L4MP_EMAC1 register field. */
1430 #define ALT_L3_SEC_L4MP_EMAC1_RESET 0x0
1431 /* Extracts the ALT_L3_SEC_L4MP_EMAC1 field value from a register. */
1432 #define ALT_L3_SEC_L4MP_EMAC1_GET(value) (((value) & 0x00000020) >> 5)
1433 /* Produces a ALT_L3_SEC_L4MP_EMAC1 register field value suitable for setting the register. */
1434 #define ALT_L3_SEC_L4MP_EMAC1_SET(value) (((value) << 5) & 0x00000020)
1435 
1436 /*
1437  * Field : ACP ID Mapper Security - acpidmap
1438  *
1439  * Controls whether secure or non-secure masters can access the ACP ID Mapper
1440  * slave.
1441  *
1442  * Field Enumeration Values:
1443  *
1444  * Enum | Value | Description
1445  * :-------------------------------------|:------|:----------------------------------------------
1446  * ALT_L3_SEC_L4MP_ACPIDMAP_E_SECURE | 0x0 | The slave can only be accessed by a secure
1447  * : | | master.
1448  * ALT_L3_SEC_L4MP_ACPIDMAP_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1449  * : | | non-secure masters.
1450  *
1451  * Field Access Macros:
1452  *
1453  */
1454 /*
1455  * Enumerated value for register field ALT_L3_SEC_L4MP_ACPIDMAP
1456  *
1457  * The slave can only be accessed by a secure master.
1458  */
1459 #define ALT_L3_SEC_L4MP_ACPIDMAP_E_SECURE 0x0
1460 /*
1461  * Enumerated value for register field ALT_L3_SEC_L4MP_ACPIDMAP
1462  *
1463  * The slave can only be accessed by a secure or non-secure masters.
1464  */
1465 #define ALT_L3_SEC_L4MP_ACPIDMAP_E_NONSECURE 0x1
1466 
1467 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_ACPIDMAP register field. */
1468 #define ALT_L3_SEC_L4MP_ACPIDMAP_LSB 6
1469 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_ACPIDMAP register field. */
1470 #define ALT_L3_SEC_L4MP_ACPIDMAP_MSB 6
1471 /* The width in bits of the ALT_L3_SEC_L4MP_ACPIDMAP register field. */
1472 #define ALT_L3_SEC_L4MP_ACPIDMAP_WIDTH 1
1473 /* The mask used to set the ALT_L3_SEC_L4MP_ACPIDMAP register field value. */
1474 #define ALT_L3_SEC_L4MP_ACPIDMAP_SET_MSK 0x00000040
1475 /* The mask used to clear the ALT_L3_SEC_L4MP_ACPIDMAP register field value. */
1476 #define ALT_L3_SEC_L4MP_ACPIDMAP_CLR_MSK 0xffffffbf
1477 /* The reset value of the ALT_L3_SEC_L4MP_ACPIDMAP register field. */
1478 #define ALT_L3_SEC_L4MP_ACPIDMAP_RESET 0x0
1479 /* Extracts the ALT_L3_SEC_L4MP_ACPIDMAP field value from a register. */
1480 #define ALT_L3_SEC_L4MP_ACPIDMAP_GET(value) (((value) & 0x00000040) >> 6)
1481 /* Produces a ALT_L3_SEC_L4MP_ACPIDMAP register field value suitable for setting the register. */
1482 #define ALT_L3_SEC_L4MP_ACPIDMAP_SET(value) (((value) << 6) & 0x00000040)
1483 
1484 /*
1485  * Field : GPIO 0 Security - gpio0
1486  *
1487  * Controls whether secure or non-secure masters can access the GPIO 0 slave.
1488  *
1489  * Field Enumeration Values:
1490  *
1491  * Enum | Value | Description
1492  * :----------------------------------|:------|:----------------------------------------------
1493  * ALT_L3_SEC_L4MP_GPIO0_E_SECURE | 0x0 | The slave can only be accessed by a secure
1494  * : | | master.
1495  * ALT_L3_SEC_L4MP_GPIO0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1496  * : | | non-secure masters.
1497  *
1498  * Field Access Macros:
1499  *
1500  */
1501 /*
1502  * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO0
1503  *
1504  * The slave can only be accessed by a secure master.
1505  */
1506 #define ALT_L3_SEC_L4MP_GPIO0_E_SECURE 0x0
1507 /*
1508  * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO0
1509  *
1510  * The slave can only be accessed by a secure or non-secure masters.
1511  */
1512 #define ALT_L3_SEC_L4MP_GPIO0_E_NONSECURE 0x1
1513 
1514 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_GPIO0 register field. */
1515 #define ALT_L3_SEC_L4MP_GPIO0_LSB 7
1516 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_GPIO0 register field. */
1517 #define ALT_L3_SEC_L4MP_GPIO0_MSB 7
1518 /* The width in bits of the ALT_L3_SEC_L4MP_GPIO0 register field. */
1519 #define ALT_L3_SEC_L4MP_GPIO0_WIDTH 1
1520 /* The mask used to set the ALT_L3_SEC_L4MP_GPIO0 register field value. */
1521 #define ALT_L3_SEC_L4MP_GPIO0_SET_MSK 0x00000080
1522 /* The mask used to clear the ALT_L3_SEC_L4MP_GPIO0 register field value. */
1523 #define ALT_L3_SEC_L4MP_GPIO0_CLR_MSK 0xffffff7f
1524 /* The reset value of the ALT_L3_SEC_L4MP_GPIO0 register field. */
1525 #define ALT_L3_SEC_L4MP_GPIO0_RESET 0x0
1526 /* Extracts the ALT_L3_SEC_L4MP_GPIO0 field value from a register. */
1527 #define ALT_L3_SEC_L4MP_GPIO0_GET(value) (((value) & 0x00000080) >> 7)
1528 /* Produces a ALT_L3_SEC_L4MP_GPIO0 register field value suitable for setting the register. */
1529 #define ALT_L3_SEC_L4MP_GPIO0_SET(value) (((value) << 7) & 0x00000080)
1530 
1531 /*
1532  * Field : GPIO 1 Security - gpio1
1533  *
1534  * Controls whether secure or non-secure masters can access the GPIO 1 slave.
1535  *
1536  * Field Enumeration Values:
1537  *
1538  * Enum | Value | Description
1539  * :----------------------------------|:------|:----------------------------------------------
1540  * ALT_L3_SEC_L4MP_GPIO1_E_SECURE | 0x0 | The slave can only be accessed by a secure
1541  * : | | master.
1542  * ALT_L3_SEC_L4MP_GPIO1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1543  * : | | non-secure masters.
1544  *
1545  * Field Access Macros:
1546  *
1547  */
1548 /*
1549  * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO1
1550  *
1551  * The slave can only be accessed by a secure master.
1552  */
1553 #define ALT_L3_SEC_L4MP_GPIO1_E_SECURE 0x0
1554 /*
1555  * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO1
1556  *
1557  * The slave can only be accessed by a secure or non-secure masters.
1558  */
1559 #define ALT_L3_SEC_L4MP_GPIO1_E_NONSECURE 0x1
1560 
1561 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_GPIO1 register field. */
1562 #define ALT_L3_SEC_L4MP_GPIO1_LSB 8
1563 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_GPIO1 register field. */
1564 #define ALT_L3_SEC_L4MP_GPIO1_MSB 8
1565 /* The width in bits of the ALT_L3_SEC_L4MP_GPIO1 register field. */
1566 #define ALT_L3_SEC_L4MP_GPIO1_WIDTH 1
1567 /* The mask used to set the ALT_L3_SEC_L4MP_GPIO1 register field value. */
1568 #define ALT_L3_SEC_L4MP_GPIO1_SET_MSK 0x00000100
1569 /* The mask used to clear the ALT_L3_SEC_L4MP_GPIO1 register field value. */
1570 #define ALT_L3_SEC_L4MP_GPIO1_CLR_MSK 0xfffffeff
1571 /* The reset value of the ALT_L3_SEC_L4MP_GPIO1 register field. */
1572 #define ALT_L3_SEC_L4MP_GPIO1_RESET 0x0
1573 /* Extracts the ALT_L3_SEC_L4MP_GPIO1 field value from a register. */
1574 #define ALT_L3_SEC_L4MP_GPIO1_GET(value) (((value) & 0x00000100) >> 8)
1575 /* Produces a ALT_L3_SEC_L4MP_GPIO1 register field value suitable for setting the register. */
1576 #define ALT_L3_SEC_L4MP_GPIO1_SET(value) (((value) << 8) & 0x00000100)
1577 
1578 /*
1579  * Field : GPIO 2 Security - gpio2
1580  *
1581  * Controls whether secure or non-secure masters can access the GPIO 2 slave.
1582  *
1583  * Field Enumeration Values:
1584  *
1585  * Enum | Value | Description
1586  * :----------------------------------|:------|:----------------------------------------------
1587  * ALT_L3_SEC_L4MP_GPIO2_E_SECURE | 0x0 | The slave can only be accessed by a secure
1588  * : | | master.
1589  * ALT_L3_SEC_L4MP_GPIO2_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1590  * : | | non-secure masters.
1591  *
1592  * Field Access Macros:
1593  *
1594  */
1595 /*
1596  * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO2
1597  *
1598  * The slave can only be accessed by a secure master.
1599  */
1600 #define ALT_L3_SEC_L4MP_GPIO2_E_SECURE 0x0
1601 /*
1602  * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO2
1603  *
1604  * The slave can only be accessed by a secure or non-secure masters.
1605  */
1606 #define ALT_L3_SEC_L4MP_GPIO2_E_NONSECURE 0x1
1607 
1608 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_GPIO2 register field. */
1609 #define ALT_L3_SEC_L4MP_GPIO2_LSB 9
1610 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_GPIO2 register field. */
1611 #define ALT_L3_SEC_L4MP_GPIO2_MSB 9
1612 /* The width in bits of the ALT_L3_SEC_L4MP_GPIO2 register field. */
1613 #define ALT_L3_SEC_L4MP_GPIO2_WIDTH 1
1614 /* The mask used to set the ALT_L3_SEC_L4MP_GPIO2 register field value. */
1615 #define ALT_L3_SEC_L4MP_GPIO2_SET_MSK 0x00000200
1616 /* The mask used to clear the ALT_L3_SEC_L4MP_GPIO2 register field value. */
1617 #define ALT_L3_SEC_L4MP_GPIO2_CLR_MSK 0xfffffdff
1618 /* The reset value of the ALT_L3_SEC_L4MP_GPIO2 register field. */
1619 #define ALT_L3_SEC_L4MP_GPIO2_RESET 0x0
1620 /* Extracts the ALT_L3_SEC_L4MP_GPIO2 field value from a register. */
1621 #define ALT_L3_SEC_L4MP_GPIO2_GET(value) (((value) & 0x00000200) >> 9)
1622 /* Produces a ALT_L3_SEC_L4MP_GPIO2 register field value suitable for setting the register. */
1623 #define ALT_L3_SEC_L4MP_GPIO2_SET(value) (((value) << 9) & 0x00000200)
1624 
1625 #ifndef __ASSEMBLY__
1626 /*
1627  * WARNING: The C register and register group struct declarations are provided for
1628  * convenience and illustrative purposes. They should, however, be used with
1629  * caution as the C language standard provides no guarantees about the alignment or
1630  * atomicity of device memory accesses. The recommended practice for writing
1631  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1632  * alt_write_word() functions.
1633  *
1634  * The struct declaration for register ALT_L3_SEC_L4MP.
1635  */
1637 {
1638  uint32_t fpgamgrregs : 1; /* FPGA Manager Register Security */
1639  uint32_t dap : 1; /* DAP Security */
1640  uint32_t qspiregs : 1; /* QSPI Registers Security */
1641  uint32_t sdmmc : 1; /* SDMMC Security */
1642  uint32_t emac0 : 1; /* EMAC 0 Security */
1643  uint32_t emac1 : 1; /* EMAC 1 Security */
1644  uint32_t acpidmap : 1; /* ACP ID Mapper Security */
1645  uint32_t gpio0 : 1; /* GPIO 0 Security */
1646  uint32_t gpio1 : 1; /* GPIO 1 Security */
1647  uint32_t gpio2 : 1; /* GPIO 2 Security */
1648  uint32_t : 22; /* *UNDEFINED* */
1649 };
1650 
1651 /* The typedef declaration for register ALT_L3_SEC_L4MP. */
1652 typedef volatile struct ALT_L3_SEC_L4MP_s ALT_L3_SEC_L4MP_t;
1653 #endif /* __ASSEMBLY__ */
1654 
1655 /* The byte offset of the ALT_L3_SEC_L4MP register from the beginning of the component. */
1656 #define ALT_L3_SEC_L4MP_OFST 0x8
1657 
1658 /*
1659  * Register : L4 OSC1 Peripherals Security - l4osc1
1660  *
1661  * Controls security settings for L4 OSC1 peripherals.
1662  *
1663  * Register Layout
1664  *
1665  * Bits | Access | Reset | Description
1666  * :-------|:-------|:------|:-----------------------------
1667  * [0] | W | 0x0 | L4 Watchdog Timer 0 Security
1668  * [1] | W | 0x0 | L4 Watchdog Timer 0 Security
1669  * [2] | W | 0x0 | Clock Manager Security
1670  * [3] | W | 0x0 | Reset Manager Security
1671  * [4] | W | 0x0 | System Manager Security
1672  * [5] | W | 0x0 | OSC1 Timer 0 Security
1673  * [6] | W | 0x0 | OSC1 Timer 1 Security
1674  * [31:7] | ??? | 0x0 | *UNDEFINED*
1675  *
1676  */
1677 /*
1678  * Field : L4 Watchdog Timer 0 Security - l4wd0
1679  *
1680  * Controls whether secure or non-secure masters can access the L4 Watchdog Timer 0
1681  * slave.
1682  *
1683  * Field Enumeration Values:
1684  *
1685  * Enum | Value | Description
1686  * :------------------------------------|:------|:----------------------------------------------
1687  * ALT_L3_SEC_L4OSC1_L4WD0_E_SECURE | 0x0 | The slave can only be accessed by a secure
1688  * : | | master.
1689  * ALT_L3_SEC_L4OSC1_L4WD0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1690  * : | | non-secure masters.
1691  *
1692  * Field Access Macros:
1693  *
1694  */
1695 /*
1696  * Enumerated value for register field ALT_L3_SEC_L4OSC1_L4WD0
1697  *
1698  * The slave can only be accessed by a secure master.
1699  */
1700 #define ALT_L3_SEC_L4OSC1_L4WD0_E_SECURE 0x0
1701 /*
1702  * Enumerated value for register field ALT_L3_SEC_L4OSC1_L4WD0
1703  *
1704  * The slave can only be accessed by a secure or non-secure masters.
1705  */
1706 #define ALT_L3_SEC_L4OSC1_L4WD0_E_NONSECURE 0x1
1707 
1708 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_L4WD0 register field. */
1709 #define ALT_L3_SEC_L4OSC1_L4WD0_LSB 0
1710 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_L4WD0 register field. */
1711 #define ALT_L3_SEC_L4OSC1_L4WD0_MSB 0
1712 /* The width in bits of the ALT_L3_SEC_L4OSC1_L4WD0 register field. */
1713 #define ALT_L3_SEC_L4OSC1_L4WD0_WIDTH 1
1714 /* The mask used to set the ALT_L3_SEC_L4OSC1_L4WD0 register field value. */
1715 #define ALT_L3_SEC_L4OSC1_L4WD0_SET_MSK 0x00000001
1716 /* The mask used to clear the ALT_L3_SEC_L4OSC1_L4WD0 register field value. */
1717 #define ALT_L3_SEC_L4OSC1_L4WD0_CLR_MSK 0xfffffffe
1718 /* The reset value of the ALT_L3_SEC_L4OSC1_L4WD0 register field. */
1719 #define ALT_L3_SEC_L4OSC1_L4WD0_RESET 0x0
1720 /* Extracts the ALT_L3_SEC_L4OSC1_L4WD0 field value from a register. */
1721 #define ALT_L3_SEC_L4OSC1_L4WD0_GET(value) (((value) & 0x00000001) >> 0)
1722 /* Produces a ALT_L3_SEC_L4OSC1_L4WD0 register field value suitable for setting the register. */
1723 #define ALT_L3_SEC_L4OSC1_L4WD0_SET(value) (((value) << 0) & 0x00000001)
1724 
1725 /*
1726  * Field : L4 Watchdog Timer 0 Security - l4wd1
1727  *
1728  * Controls whether secure or non-secure masters can access the L4 Watchdog Timer 0
1729  * slave.
1730  *
1731  * Field Enumeration Values:
1732  *
1733  * Enum | Value | Description
1734  * :------------------------------------|:------|:----------------------------------------------
1735  * ALT_L3_SEC_L4OSC1_L4WD1_E_SECURE | 0x0 | The slave can only be accessed by a secure
1736  * : | | master.
1737  * ALT_L3_SEC_L4OSC1_L4WD1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1738  * : | | non-secure masters.
1739  *
1740  * Field Access Macros:
1741  *
1742  */
1743 /*
1744  * Enumerated value for register field ALT_L3_SEC_L4OSC1_L4WD1
1745  *
1746  * The slave can only be accessed by a secure master.
1747  */
1748 #define ALT_L3_SEC_L4OSC1_L4WD1_E_SECURE 0x0
1749 /*
1750  * Enumerated value for register field ALT_L3_SEC_L4OSC1_L4WD1
1751  *
1752  * The slave can only be accessed by a secure or non-secure masters.
1753  */
1754 #define ALT_L3_SEC_L4OSC1_L4WD1_E_NONSECURE 0x1
1755 
1756 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_L4WD1 register field. */
1757 #define ALT_L3_SEC_L4OSC1_L4WD1_LSB 1
1758 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_L4WD1 register field. */
1759 #define ALT_L3_SEC_L4OSC1_L4WD1_MSB 1
1760 /* The width in bits of the ALT_L3_SEC_L4OSC1_L4WD1 register field. */
1761 #define ALT_L3_SEC_L4OSC1_L4WD1_WIDTH 1
1762 /* The mask used to set the ALT_L3_SEC_L4OSC1_L4WD1 register field value. */
1763 #define ALT_L3_SEC_L4OSC1_L4WD1_SET_MSK 0x00000002
1764 /* The mask used to clear the ALT_L3_SEC_L4OSC1_L4WD1 register field value. */
1765 #define ALT_L3_SEC_L4OSC1_L4WD1_CLR_MSK 0xfffffffd
1766 /* The reset value of the ALT_L3_SEC_L4OSC1_L4WD1 register field. */
1767 #define ALT_L3_SEC_L4OSC1_L4WD1_RESET 0x0
1768 /* Extracts the ALT_L3_SEC_L4OSC1_L4WD1 field value from a register. */
1769 #define ALT_L3_SEC_L4OSC1_L4WD1_GET(value) (((value) & 0x00000002) >> 1)
1770 /* Produces a ALT_L3_SEC_L4OSC1_L4WD1 register field value suitable for setting the register. */
1771 #define ALT_L3_SEC_L4OSC1_L4WD1_SET(value) (((value) << 1) & 0x00000002)
1772 
1773 /*
1774  * Field : Clock Manager Security - clkmgr
1775  *
1776  * Controls whether secure or non-secure masters can access the Clock Manager
1777  * slave.
1778  *
1779  * Field Enumeration Values:
1780  *
1781  * Enum | Value | Description
1782  * :-------------------------------------|:------|:----------------------------------------------
1783  * ALT_L3_SEC_L4OSC1_CLKMGR_E_SECURE | 0x0 | The slave can only be accessed by a secure
1784  * : | | master.
1785  * ALT_L3_SEC_L4OSC1_CLKMGR_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1786  * : | | non-secure masters.
1787  *
1788  * Field Access Macros:
1789  *
1790  */
1791 /*
1792  * Enumerated value for register field ALT_L3_SEC_L4OSC1_CLKMGR
1793  *
1794  * The slave can only be accessed by a secure master.
1795  */
1796 #define ALT_L3_SEC_L4OSC1_CLKMGR_E_SECURE 0x0
1797 /*
1798  * Enumerated value for register field ALT_L3_SEC_L4OSC1_CLKMGR
1799  *
1800  * The slave can only be accessed by a secure or non-secure masters.
1801  */
1802 #define ALT_L3_SEC_L4OSC1_CLKMGR_E_NONSECURE 0x1
1803 
1804 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_CLKMGR register field. */
1805 #define ALT_L3_SEC_L4OSC1_CLKMGR_LSB 2
1806 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_CLKMGR register field. */
1807 #define ALT_L3_SEC_L4OSC1_CLKMGR_MSB 2
1808 /* The width in bits of the ALT_L3_SEC_L4OSC1_CLKMGR register field. */
1809 #define ALT_L3_SEC_L4OSC1_CLKMGR_WIDTH 1
1810 /* The mask used to set the ALT_L3_SEC_L4OSC1_CLKMGR register field value. */
1811 #define ALT_L3_SEC_L4OSC1_CLKMGR_SET_MSK 0x00000004
1812 /* The mask used to clear the ALT_L3_SEC_L4OSC1_CLKMGR register field value. */
1813 #define ALT_L3_SEC_L4OSC1_CLKMGR_CLR_MSK 0xfffffffb
1814 /* The reset value of the ALT_L3_SEC_L4OSC1_CLKMGR register field. */
1815 #define ALT_L3_SEC_L4OSC1_CLKMGR_RESET 0x0
1816 /* Extracts the ALT_L3_SEC_L4OSC1_CLKMGR field value from a register. */
1817 #define ALT_L3_SEC_L4OSC1_CLKMGR_GET(value) (((value) & 0x00000004) >> 2)
1818 /* Produces a ALT_L3_SEC_L4OSC1_CLKMGR register field value suitable for setting the register. */
1819 #define ALT_L3_SEC_L4OSC1_CLKMGR_SET(value) (((value) << 2) & 0x00000004)
1820 
1821 /*
1822  * Field : Reset Manager Security - rstmgr
1823  *
1824  * Controls whether secure or non-secure masters can access the Reset Manager
1825  * slave.
1826  *
1827  * Field Enumeration Values:
1828  *
1829  * Enum | Value | Description
1830  * :-------------------------------------|:------|:----------------------------------------------
1831  * ALT_L3_SEC_L4OSC1_RSTMGR_E_SECURE | 0x0 | The slave can only be accessed by a secure
1832  * : | | master.
1833  * ALT_L3_SEC_L4OSC1_RSTMGR_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1834  * : | | non-secure masters.
1835  *
1836  * Field Access Macros:
1837  *
1838  */
1839 /*
1840  * Enumerated value for register field ALT_L3_SEC_L4OSC1_RSTMGR
1841  *
1842  * The slave can only be accessed by a secure master.
1843  */
1844 #define ALT_L3_SEC_L4OSC1_RSTMGR_E_SECURE 0x0
1845 /*
1846  * Enumerated value for register field ALT_L3_SEC_L4OSC1_RSTMGR
1847  *
1848  * The slave can only be accessed by a secure or non-secure masters.
1849  */
1850 #define ALT_L3_SEC_L4OSC1_RSTMGR_E_NONSECURE 0x1
1851 
1852 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_RSTMGR register field. */
1853 #define ALT_L3_SEC_L4OSC1_RSTMGR_LSB 3
1854 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_RSTMGR register field. */
1855 #define ALT_L3_SEC_L4OSC1_RSTMGR_MSB 3
1856 /* The width in bits of the ALT_L3_SEC_L4OSC1_RSTMGR register field. */
1857 #define ALT_L3_SEC_L4OSC1_RSTMGR_WIDTH 1
1858 /* The mask used to set the ALT_L3_SEC_L4OSC1_RSTMGR register field value. */
1859 #define ALT_L3_SEC_L4OSC1_RSTMGR_SET_MSK 0x00000008
1860 /* The mask used to clear the ALT_L3_SEC_L4OSC1_RSTMGR register field value. */
1861 #define ALT_L3_SEC_L4OSC1_RSTMGR_CLR_MSK 0xfffffff7
1862 /* The reset value of the ALT_L3_SEC_L4OSC1_RSTMGR register field. */
1863 #define ALT_L3_SEC_L4OSC1_RSTMGR_RESET 0x0
1864 /* Extracts the ALT_L3_SEC_L4OSC1_RSTMGR field value from a register. */
1865 #define ALT_L3_SEC_L4OSC1_RSTMGR_GET(value) (((value) & 0x00000008) >> 3)
1866 /* Produces a ALT_L3_SEC_L4OSC1_RSTMGR register field value suitable for setting the register. */
1867 #define ALT_L3_SEC_L4OSC1_RSTMGR_SET(value) (((value) << 3) & 0x00000008)
1868 
1869 /*
1870  * Field : System Manager Security - sysmgr
1871  *
1872  * Controls whether secure or non-secure masters can access the System Manager
1873  * slave.
1874  *
1875  * Field Enumeration Values:
1876  *
1877  * Enum | Value | Description
1878  * :-------------------------------------|:------|:----------------------------------------------
1879  * ALT_L3_SEC_L4OSC1_SYSMGR_E_SECURE | 0x0 | The slave can only be accessed by a secure
1880  * : | | master.
1881  * ALT_L3_SEC_L4OSC1_SYSMGR_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1882  * : | | non-secure masters.
1883  *
1884  * Field Access Macros:
1885  *
1886  */
1887 /*
1888  * Enumerated value for register field ALT_L3_SEC_L4OSC1_SYSMGR
1889  *
1890  * The slave can only be accessed by a secure master.
1891  */
1892 #define ALT_L3_SEC_L4OSC1_SYSMGR_E_SECURE 0x0
1893 /*
1894  * Enumerated value for register field ALT_L3_SEC_L4OSC1_SYSMGR
1895  *
1896  * The slave can only be accessed by a secure or non-secure masters.
1897  */
1898 #define ALT_L3_SEC_L4OSC1_SYSMGR_E_NONSECURE 0x1
1899 
1900 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_SYSMGR register field. */
1901 #define ALT_L3_SEC_L4OSC1_SYSMGR_LSB 4
1902 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_SYSMGR register field. */
1903 #define ALT_L3_SEC_L4OSC1_SYSMGR_MSB 4
1904 /* The width in bits of the ALT_L3_SEC_L4OSC1_SYSMGR register field. */
1905 #define ALT_L3_SEC_L4OSC1_SYSMGR_WIDTH 1
1906 /* The mask used to set the ALT_L3_SEC_L4OSC1_SYSMGR register field value. */
1907 #define ALT_L3_SEC_L4OSC1_SYSMGR_SET_MSK 0x00000010
1908 /* The mask used to clear the ALT_L3_SEC_L4OSC1_SYSMGR register field value. */
1909 #define ALT_L3_SEC_L4OSC1_SYSMGR_CLR_MSK 0xffffffef
1910 /* The reset value of the ALT_L3_SEC_L4OSC1_SYSMGR register field. */
1911 #define ALT_L3_SEC_L4OSC1_SYSMGR_RESET 0x0
1912 /* Extracts the ALT_L3_SEC_L4OSC1_SYSMGR field value from a register. */
1913 #define ALT_L3_SEC_L4OSC1_SYSMGR_GET(value) (((value) & 0x00000010) >> 4)
1914 /* Produces a ALT_L3_SEC_L4OSC1_SYSMGR register field value suitable for setting the register. */
1915 #define ALT_L3_SEC_L4OSC1_SYSMGR_SET(value) (((value) << 4) & 0x00000010)
1916 
1917 /*
1918  * Field : OSC1 Timer 0 Security - osc1timer0
1919  *
1920  * Controls whether secure or non-secure masters can access the OSC1 Timer 0 slave.
1921  *
1922  * Field Enumeration Values:
1923  *
1924  * Enum | Value | Description
1925  * :---------------------------------------|:------|:----------------------------------------------
1926  * ALT_L3_SEC_L4OSC1_OSC1TMR0_E_SECURE | 0x0 | The slave can only be accessed by a secure
1927  * : | | master.
1928  * ALT_L3_SEC_L4OSC1_OSC1TMR0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1929  * : | | non-secure masters.
1930  *
1931  * Field Access Macros:
1932  *
1933  */
1934 /*
1935  * Enumerated value for register field ALT_L3_SEC_L4OSC1_OSC1TMR0
1936  *
1937  * The slave can only be accessed by a secure master.
1938  */
1939 #define ALT_L3_SEC_L4OSC1_OSC1TMR0_E_SECURE 0x0
1940 /*
1941  * Enumerated value for register field ALT_L3_SEC_L4OSC1_OSC1TMR0
1942  *
1943  * The slave can only be accessed by a secure or non-secure masters.
1944  */
1945 #define ALT_L3_SEC_L4OSC1_OSC1TMR0_E_NONSECURE 0x1
1946 
1947 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field. */
1948 #define ALT_L3_SEC_L4OSC1_OSC1TMR0_LSB 5
1949 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field. */
1950 #define ALT_L3_SEC_L4OSC1_OSC1TMR0_MSB 5
1951 /* The width in bits of the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field. */
1952 #define ALT_L3_SEC_L4OSC1_OSC1TMR0_WIDTH 1
1953 /* The mask used to set the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field value. */
1954 #define ALT_L3_SEC_L4OSC1_OSC1TMR0_SET_MSK 0x00000020
1955 /* The mask used to clear the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field value. */
1956 #define ALT_L3_SEC_L4OSC1_OSC1TMR0_CLR_MSK 0xffffffdf
1957 /* The reset value of the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field. */
1958 #define ALT_L3_SEC_L4OSC1_OSC1TMR0_RESET 0x0
1959 /* Extracts the ALT_L3_SEC_L4OSC1_OSC1TMR0 field value from a register. */
1960 #define ALT_L3_SEC_L4OSC1_OSC1TMR0_GET(value) (((value) & 0x00000020) >> 5)
1961 /* Produces a ALT_L3_SEC_L4OSC1_OSC1TMR0 register field value suitable for setting the register. */
1962 #define ALT_L3_SEC_L4OSC1_OSC1TMR0_SET(value) (((value) << 5) & 0x00000020)
1963 
1964 /*
1965  * Field : OSC1 Timer 1 Security - osc1timer1
1966  *
1967  * Controls whether secure or non-secure masters can access the OSC1 Timer 1 slave.
1968  *
1969  * Field Enumeration Values:
1970  *
1971  * Enum | Value | Description
1972  * :---------------------------------------|:------|:----------------------------------------------
1973  * ALT_L3_SEC_L4OSC1_OSC1TMR1_E_SECURE | 0x0 | The slave can only be accessed by a secure
1974  * : | | master.
1975  * ALT_L3_SEC_L4OSC1_OSC1TMR1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1976  * : | | non-secure masters.
1977  *
1978  * Field Access Macros:
1979  *
1980  */
1981 /*
1982  * Enumerated value for register field ALT_L3_SEC_L4OSC1_OSC1TMR1
1983  *
1984  * The slave can only be accessed by a secure master.
1985  */
1986 #define ALT_L3_SEC_L4OSC1_OSC1TMR1_E_SECURE 0x0
1987 /*
1988  * Enumerated value for register field ALT_L3_SEC_L4OSC1_OSC1TMR1
1989  *
1990  * The slave can only be accessed by a secure or non-secure masters.
1991  */
1992 #define ALT_L3_SEC_L4OSC1_OSC1TMR1_E_NONSECURE 0x1
1993 
1994 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field. */
1995 #define ALT_L3_SEC_L4OSC1_OSC1TMR1_LSB 6
1996 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field. */
1997 #define ALT_L3_SEC_L4OSC1_OSC1TMR1_MSB 6
1998 /* The width in bits of the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field. */
1999 #define ALT_L3_SEC_L4OSC1_OSC1TMR1_WIDTH 1
2000 /* The mask used to set the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field value. */
2001 #define ALT_L3_SEC_L4OSC1_OSC1TMR1_SET_MSK 0x00000040
2002 /* The mask used to clear the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field value. */
2003 #define ALT_L3_SEC_L4OSC1_OSC1TMR1_CLR_MSK 0xffffffbf
2004 /* The reset value of the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field. */
2005 #define ALT_L3_SEC_L4OSC1_OSC1TMR1_RESET 0x0
2006 /* Extracts the ALT_L3_SEC_L4OSC1_OSC1TMR1 field value from a register. */
2007 #define ALT_L3_SEC_L4OSC1_OSC1TMR1_GET(value) (((value) & 0x00000040) >> 6)
2008 /* Produces a ALT_L3_SEC_L4OSC1_OSC1TMR1 register field value suitable for setting the register. */
2009 #define ALT_L3_SEC_L4OSC1_OSC1TMR1_SET(value) (((value) << 6) & 0x00000040)
2010 
2011 #ifndef __ASSEMBLY__
2012 /*
2013  * WARNING: The C register and register group struct declarations are provided for
2014  * convenience and illustrative purposes. They should, however, be used with
2015  * caution as the C language standard provides no guarantees about the alignment or
2016  * atomicity of device memory accesses. The recommended practice for writing
2017  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2018  * alt_write_word() functions.
2019  *
2020  * The struct declaration for register ALT_L3_SEC_L4OSC1.
2021  */
2023 {
2024  uint32_t l4wd0 : 1; /* L4 Watchdog Timer 0 Security */
2025  uint32_t l4wd1 : 1; /* L4 Watchdog Timer 0 Security */
2026  uint32_t clkmgr : 1; /* Clock Manager Security */
2027  uint32_t rstmgr : 1; /* Reset Manager Security */
2028  uint32_t sysmgr : 1; /* System Manager Security */
2029  uint32_t osc1timer0 : 1; /* OSC1 Timer 0 Security */
2030  uint32_t osc1timer1 : 1; /* OSC1 Timer 1 Security */
2031  uint32_t : 25; /* *UNDEFINED* */
2032 };
2033 
2034 /* The typedef declaration for register ALT_L3_SEC_L4OSC1. */
2035 typedef volatile struct ALT_L3_SEC_L4OSC1_s ALT_L3_SEC_L4OSC1_t;
2036 #endif /* __ASSEMBLY__ */
2037 
2038 /* The byte offset of the ALT_L3_SEC_L4OSC1 register from the beginning of the component. */
2039 #define ALT_L3_SEC_L4OSC1_OFST 0xc
2040 
2041 /*
2042  * Register : L4 SPIM Peripherals Security - l4spim
2043  *
2044  * Controls security settings for L4 SPIM peripherals.
2045  *
2046  * Register Layout
2047  *
2048  * Bits | Access | Reset | Description
2049  * :-------|:-------|:------|:----------------------
2050  * [0] | W | 0x0 | SPI Master 0 Security
2051  * [1] | W | 0x0 | SPI Master 1 Security
2052  * [2] | W | 0x0 | Scan Manager Security
2053  * [31:3] | ??? | 0x0 | *UNDEFINED*
2054  *
2055  */
2056 /*
2057  * Field : SPI Master 0 Security - spim0
2058  *
2059  * Controls whether secure or non-secure masters can access the SPI Master 0 slave.
2060  *
2061  * Field Enumeration Values:
2062  *
2063  * Enum | Value | Description
2064  * :------------------------------------|:------|:----------------------------------------------
2065  * ALT_L3_SEC_L4SPIM_SPIM0_E_SECURE | 0x0 | The slave can only be accessed by a secure
2066  * : | | master.
2067  * ALT_L3_SEC_L4SPIM_SPIM0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
2068  * : | | non-secure masters.
2069  *
2070  * Field Access Macros:
2071  *
2072  */
2073 /*
2074  * Enumerated value for register field ALT_L3_SEC_L4SPIM_SPIM0
2075  *
2076  * The slave can only be accessed by a secure master.
2077  */
2078 #define ALT_L3_SEC_L4SPIM_SPIM0_E_SECURE 0x0
2079 /*
2080  * Enumerated value for register field ALT_L3_SEC_L4SPIM_SPIM0
2081  *
2082  * The slave can only be accessed by a secure or non-secure masters.
2083  */
2084 #define ALT_L3_SEC_L4SPIM_SPIM0_E_NONSECURE 0x1
2085 
2086 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SPIM_SPIM0 register field. */
2087 #define ALT_L3_SEC_L4SPIM_SPIM0_LSB 0
2088 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SPIM_SPIM0 register field. */
2089 #define ALT_L3_SEC_L4SPIM_SPIM0_MSB 0
2090 /* The width in bits of the ALT_L3_SEC_L4SPIM_SPIM0 register field. */
2091 #define ALT_L3_SEC_L4SPIM_SPIM0_WIDTH 1
2092 /* The mask used to set the ALT_L3_SEC_L4SPIM_SPIM0 register field value. */
2093 #define ALT_L3_SEC_L4SPIM_SPIM0_SET_MSK 0x00000001
2094 /* The mask used to clear the ALT_L3_SEC_L4SPIM_SPIM0 register field value. */
2095 #define ALT_L3_SEC_L4SPIM_SPIM0_CLR_MSK 0xfffffffe
2096 /* The reset value of the ALT_L3_SEC_L4SPIM_SPIM0 register field. */
2097 #define ALT_L3_SEC_L4SPIM_SPIM0_RESET 0x0
2098 /* Extracts the ALT_L3_SEC_L4SPIM_SPIM0 field value from a register. */
2099 #define ALT_L3_SEC_L4SPIM_SPIM0_GET(value) (((value) & 0x00000001) >> 0)
2100 /* Produces a ALT_L3_SEC_L4SPIM_SPIM0 register field value suitable for setting the register. */
2101 #define ALT_L3_SEC_L4SPIM_SPIM0_SET(value) (((value) << 0) & 0x00000001)
2102 
2103 /*
2104  * Field : SPI Master 1 Security - spim1
2105  *
2106  * Controls whether secure or non-secure masters can access the SPI Master 1 slave.
2107  *
2108  * Field Enumeration Values:
2109  *
2110  * Enum | Value | Description
2111  * :------------------------------------|:------|:----------------------------------------------
2112  * ALT_L3_SEC_L4SPIM_SPIM1_E_SECURE | 0x0 | The slave can only be accessed by a secure
2113  * : | | master.
2114  * ALT_L3_SEC_L4SPIM_SPIM1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
2115  * : | | non-secure masters.
2116  *
2117  * Field Access Macros:
2118  *
2119  */
2120 /*
2121  * Enumerated value for register field ALT_L3_SEC_L4SPIM_SPIM1
2122  *
2123  * The slave can only be accessed by a secure master.
2124  */
2125 #define ALT_L3_SEC_L4SPIM_SPIM1_E_SECURE 0x0
2126 /*
2127  * Enumerated value for register field ALT_L3_SEC_L4SPIM_SPIM1
2128  *
2129  * The slave can only be accessed by a secure or non-secure masters.
2130  */
2131 #define ALT_L3_SEC_L4SPIM_SPIM1_E_NONSECURE 0x1
2132 
2133 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SPIM_SPIM1 register field. */
2134 #define ALT_L3_SEC_L4SPIM_SPIM1_LSB 1
2135 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SPIM_SPIM1 register field. */
2136 #define ALT_L3_SEC_L4SPIM_SPIM1_MSB 1
2137 /* The width in bits of the ALT_L3_SEC_L4SPIM_SPIM1 register field. */
2138 #define ALT_L3_SEC_L4SPIM_SPIM1_WIDTH 1
2139 /* The mask used to set the ALT_L3_SEC_L4SPIM_SPIM1 register field value. */
2140 #define ALT_L3_SEC_L4SPIM_SPIM1_SET_MSK 0x00000002
2141 /* The mask used to clear the ALT_L3_SEC_L4SPIM_SPIM1 register field value. */
2142 #define ALT_L3_SEC_L4SPIM_SPIM1_CLR_MSK 0xfffffffd
2143 /* The reset value of the ALT_L3_SEC_L4SPIM_SPIM1 register field. */
2144 #define ALT_L3_SEC_L4SPIM_SPIM1_RESET 0x0
2145 /* Extracts the ALT_L3_SEC_L4SPIM_SPIM1 field value from a register. */
2146 #define ALT_L3_SEC_L4SPIM_SPIM1_GET(value) (((value) & 0x00000002) >> 1)
2147 /* Produces a ALT_L3_SEC_L4SPIM_SPIM1 register field value suitable for setting the register. */
2148 #define ALT_L3_SEC_L4SPIM_SPIM1_SET(value) (((value) << 1) & 0x00000002)
2149 
2150 /*
2151  * Field : Scan Manager Security - scanmgr
2152  *
2153  * Controls whether secure or non-secure masters can access the Scan Manager slave.
2154  *
2155  * Field Enumeration Values:
2156  *
2157  * Enum | Value | Description
2158  * :--------------------------------------|:------|:----------------------------------------------
2159  * ALT_L3_SEC_L4SPIM_SCANMGR_E_SECURE | 0x0 | The slave can only be accessed by a secure
2160  * : | | master.
2161  * ALT_L3_SEC_L4SPIM_SCANMGR_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
2162  * : | | non-secure masters.
2163  *
2164  * Field Access Macros:
2165  *
2166  */
2167 /*
2168  * Enumerated value for register field ALT_L3_SEC_L4SPIM_SCANMGR
2169  *
2170  * The slave can only be accessed by a secure master.
2171  */
2172 #define ALT_L3_SEC_L4SPIM_SCANMGR_E_SECURE 0x0
2173 /*
2174  * Enumerated value for register field ALT_L3_SEC_L4SPIM_SCANMGR
2175  *
2176  * The slave can only be accessed by a secure or non-secure masters.
2177  */
2178 #define ALT_L3_SEC_L4SPIM_SCANMGR_E_NONSECURE 0x1
2179 
2180 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SPIM_SCANMGR register field. */
2181 #define ALT_L3_SEC_L4SPIM_SCANMGR_LSB 2
2182 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SPIM_SCANMGR register field. */
2183 #define ALT_L3_SEC_L4SPIM_SCANMGR_MSB 2
2184 /* The width in bits of the ALT_L3_SEC_L4SPIM_SCANMGR register field. */
2185 #define ALT_L3_SEC_L4SPIM_SCANMGR_WIDTH 1
2186 /* The mask used to set the ALT_L3_SEC_L4SPIM_SCANMGR register field value. */
2187 #define ALT_L3_SEC_L4SPIM_SCANMGR_SET_MSK 0x00000004
2188 /* The mask used to clear the ALT_L3_SEC_L4SPIM_SCANMGR register field value. */
2189 #define ALT_L3_SEC_L4SPIM_SCANMGR_CLR_MSK 0xfffffffb
2190 /* The reset value of the ALT_L3_SEC_L4SPIM_SCANMGR register field. */
2191 #define ALT_L3_SEC_L4SPIM_SCANMGR_RESET 0x0
2192 /* Extracts the ALT_L3_SEC_L4SPIM_SCANMGR field value from a register. */
2193 #define ALT_L3_SEC_L4SPIM_SCANMGR_GET(value) (((value) & 0x00000004) >> 2)
2194 /* Produces a ALT_L3_SEC_L4SPIM_SCANMGR register field value suitable for setting the register. */
2195 #define ALT_L3_SEC_L4SPIM_SCANMGR_SET(value) (((value) << 2) & 0x00000004)
2196 
2197 #ifndef __ASSEMBLY__
2198 /*
2199  * WARNING: The C register and register group struct declarations are provided for
2200  * convenience and illustrative purposes. They should, however, be used with
2201  * caution as the C language standard provides no guarantees about the alignment or
2202  * atomicity of device memory accesses. The recommended practice for writing
2203  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2204  * alt_write_word() functions.
2205  *
2206  * The struct declaration for register ALT_L3_SEC_L4SPIM.
2207  */
2209 {
2210  uint32_t spim0 : 1; /* SPI Master 0 Security */
2211  uint32_t spim1 : 1; /* SPI Master 1 Security */
2212  uint32_t scanmgr : 1; /* Scan Manager Security */
2213  uint32_t : 29; /* *UNDEFINED* */
2214 };
2215 
2216 /* The typedef declaration for register ALT_L3_SEC_L4SPIM. */
2217 typedef volatile struct ALT_L3_SEC_L4SPIM_s ALT_L3_SEC_L4SPIM_t;
2218 #endif /* __ASSEMBLY__ */
2219 
2220 /* The byte offset of the ALT_L3_SEC_L4SPIM register from the beginning of the component. */
2221 #define ALT_L3_SEC_L4SPIM_OFST 0x10
2222 
2223 /*
2224  * Register : STM Peripheral Security - stm
2225  *
2226  * Controls security settings for STM peripheral.
2227  *
2228  * Register Layout
2229  *
2230  * Bits | Access | Reset | Description
2231  * :-------|:-------|:------|:-------------
2232  * [0] | W | 0x0 | STM Security
2233  * [31:1] | ??? | 0x0 | *UNDEFINED*
2234  *
2235  */
2236 /*
2237  * Field : STM Security - s
2238  *
2239  * Controls whether secure or non-secure masters can access the STM slave.
2240  *
2241  * Field Enumeration Values:
2242  *
2243  * Enum | Value | Description
2244  * :-----------------------------|:------|:----------------------------------------------
2245  * ALT_L3_SEC_STM_S_E_SECURE | 0x0 | The slave can only be accessed by a secure
2246  * : | | master.
2247  * ALT_L3_SEC_STM_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
2248  * : | | non-secure masters.
2249  *
2250  * Field Access Macros:
2251  *
2252  */
2253 /*
2254  * Enumerated value for register field ALT_L3_SEC_STM_S
2255  *
2256  * The slave can only be accessed by a secure master.
2257  */
2258 #define ALT_L3_SEC_STM_S_E_SECURE 0x0
2259 /*
2260  * Enumerated value for register field ALT_L3_SEC_STM_S
2261  *
2262  * The slave can only be accessed by a secure or non-secure masters.
2263  */
2264 #define ALT_L3_SEC_STM_S_E_NONSECURE 0x1
2265 
2266 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_STM_S register field. */
2267 #define ALT_L3_SEC_STM_S_LSB 0
2268 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_STM_S register field. */
2269 #define ALT_L3_SEC_STM_S_MSB 0
2270 /* The width in bits of the ALT_L3_SEC_STM_S register field. */
2271 #define ALT_L3_SEC_STM_S_WIDTH 1
2272 /* The mask used to set the ALT_L3_SEC_STM_S register field value. */
2273 #define ALT_L3_SEC_STM_S_SET_MSK 0x00000001
2274 /* The mask used to clear the ALT_L3_SEC_STM_S register field value. */
2275 #define ALT_L3_SEC_STM_S_CLR_MSK 0xfffffffe
2276 /* The reset value of the ALT_L3_SEC_STM_S register field. */
2277 #define ALT_L3_SEC_STM_S_RESET 0x0
2278 /* Extracts the ALT_L3_SEC_STM_S field value from a register. */
2279 #define ALT_L3_SEC_STM_S_GET(value) (((value) & 0x00000001) >> 0)
2280 /* Produces a ALT_L3_SEC_STM_S register field value suitable for setting the register. */
2281 #define ALT_L3_SEC_STM_S_SET(value) (((value) << 0) & 0x00000001)
2282 
2283 #ifndef __ASSEMBLY__
2284 /*
2285  * WARNING: The C register and register group struct declarations are provided for
2286  * convenience and illustrative purposes. They should, however, be used with
2287  * caution as the C language standard provides no guarantees about the alignment or
2288  * atomicity of device memory accesses. The recommended practice for writing
2289  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2290  * alt_write_word() functions.
2291  *
2292  * The struct declaration for register ALT_L3_SEC_STM.
2293  */
2295 {
2296  uint32_t s : 1; /* STM Security */
2297  uint32_t : 31; /* *UNDEFINED* */
2298 };
2299 
2300 /* The typedef declaration for register ALT_L3_SEC_STM. */
2301 typedef volatile struct ALT_L3_SEC_STM_s ALT_L3_SEC_STM_t;
2302 #endif /* __ASSEMBLY__ */
2303 
2304 /* The byte offset of the ALT_L3_SEC_STM register from the beginning of the component. */
2305 #define ALT_L3_SEC_STM_OFST 0x14
2306 
2307 /*
2308  * Register : LWHPS2FPGA AXI Bridge Registers Peripheral Security - lwhps2fpgaregs
2309  *
2310  * Controls security settings for LWHPS2FPGA AXI Bridge Registers peripheral.
2311  *
2312  * Register Layout
2313  *
2314  * Bits | Access | Reset | Description
2315  * :-------|:-------|:------|:-----------------------------------------
2316  * [0] | W | 0x0 | LWHPS2FPGA AXI Bridge Registers Security
2317  * [31:1] | ??? | 0x0 | *UNDEFINED*
2318  *
2319  */
2320 /*
2321  * Field : LWHPS2FPGA AXI Bridge Registers Security - s
2322  *
2323  * Controls whether secure or non-secure masters can access the LWHPS2FPGA AXI
2324  * Bridge Registers slave.
2325  *
2326  * Field Enumeration Values:
2327  *
2328  * Enum | Value | Description
2329  * :-------------------------------|:------|:----------------------------------------------
2330  * ALT_L3_SEC_LWH2F_S_E_SECURE | 0x0 | The slave can only be accessed by a secure
2331  * : | | master.
2332  * ALT_L3_SEC_LWH2F_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
2333  * : | | non-secure masters.
2334  *
2335  * Field Access Macros:
2336  *
2337  */
2338 /*
2339  * Enumerated value for register field ALT_L3_SEC_LWH2F_S
2340  *
2341  * The slave can only be accessed by a secure master.
2342  */
2343 #define ALT_L3_SEC_LWH2F_S_E_SECURE 0x0
2344 /*
2345  * Enumerated value for register field ALT_L3_SEC_LWH2F_S
2346  *
2347  * The slave can only be accessed by a secure or non-secure masters.
2348  */
2349 #define ALT_L3_SEC_LWH2F_S_E_NONSECURE 0x1
2350 
2351 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_LWH2F_S register field. */
2352 #define ALT_L3_SEC_LWH2F_S_LSB 0
2353 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_LWH2F_S register field. */
2354 #define ALT_L3_SEC_LWH2F_S_MSB 0
2355 /* The width in bits of the ALT_L3_SEC_LWH2F_S register field. */
2356 #define ALT_L3_SEC_LWH2F_S_WIDTH 1
2357 /* The mask used to set the ALT_L3_SEC_LWH2F_S register field value. */
2358 #define ALT_L3_SEC_LWH2F_S_SET_MSK 0x00000001
2359 /* The mask used to clear the ALT_L3_SEC_LWH2F_S register field value. */
2360 #define ALT_L3_SEC_LWH2F_S_CLR_MSK 0xfffffffe
2361 /* The reset value of the ALT_L3_SEC_LWH2F_S register field. */
2362 #define ALT_L3_SEC_LWH2F_S_RESET 0x0
2363 /* Extracts the ALT_L3_SEC_LWH2F_S field value from a register. */
2364 #define ALT_L3_SEC_LWH2F_S_GET(value) (((value) & 0x00000001) >> 0)
2365 /* Produces a ALT_L3_SEC_LWH2F_S register field value suitable for setting the register. */
2366 #define ALT_L3_SEC_LWH2F_S_SET(value) (((value) << 0) & 0x00000001)
2367 
2368 #ifndef __ASSEMBLY__
2369 /*
2370  * WARNING: The C register and register group struct declarations are provided for
2371  * convenience and illustrative purposes. They should, however, be used with
2372  * caution as the C language standard provides no guarantees about the alignment or
2373  * atomicity of device memory accesses. The recommended practice for writing
2374  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2375  * alt_write_word() functions.
2376  *
2377  * The struct declaration for register ALT_L3_SEC_LWH2F.
2378  */
2380 {
2381  uint32_t s : 1; /* LWHPS2FPGA AXI Bridge Registers Security */
2382  uint32_t : 31; /* *UNDEFINED* */
2383 };
2384 
2385 /* The typedef declaration for register ALT_L3_SEC_LWH2F. */
2386 typedef volatile struct ALT_L3_SEC_LWH2F_s ALT_L3_SEC_LWH2F_t;
2387 #endif /* __ASSEMBLY__ */
2388 
2389 /* The byte offset of the ALT_L3_SEC_LWH2F register from the beginning of the component. */
2390 #define ALT_L3_SEC_LWH2F_OFST 0x18
2391 
2392 /*
2393  * Register : USB1 Registers Peripheral Security - usb1
2394  *
2395  * Controls security settings for USB1 Registers peripheral.
2396  *
2397  * Register Layout
2398  *
2399  * Bits | Access | Reset | Description
2400  * :-------|:-------|:------|:------------------------
2401  * [0] | W | 0x0 | USB1 Registers Security
2402  * [31:1] | ??? | 0x0 | *UNDEFINED*
2403  *
2404  */
2405 /*
2406  * Field : USB1 Registers Security - s
2407  *
2408  * Controls whether secure or non-secure masters can access the USB1 Registers
2409  * slave.
2410  *
2411  * Field Enumeration Values:
2412  *
2413  * Enum | Value | Description
2414  * :------------------------------|:------|:----------------------------------------------
2415  * ALT_L3_SEC_USB1_S_E_SECURE | 0x0 | The slave can only be accessed by a secure
2416  * : | | master.
2417  * ALT_L3_SEC_USB1_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
2418  * : | | non-secure masters.
2419  *
2420  * Field Access Macros:
2421  *
2422  */
2423 /*
2424  * Enumerated value for register field ALT_L3_SEC_USB1_S
2425  *
2426  * The slave can only be accessed by a secure master.
2427  */
2428 #define ALT_L3_SEC_USB1_S_E_SECURE 0x0
2429 /*
2430  * Enumerated value for register field ALT_L3_SEC_USB1_S
2431  *
2432  * The slave can only be accessed by a secure or non-secure masters.
2433  */
2434 #define ALT_L3_SEC_USB1_S_E_NONSECURE 0x1
2435 
2436 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_USB1_S register field. */
2437 #define ALT_L3_SEC_USB1_S_LSB 0
2438 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_USB1_S register field. */
2439 #define ALT_L3_SEC_USB1_S_MSB 0
2440 /* The width in bits of the ALT_L3_SEC_USB1_S register field. */
2441 #define ALT_L3_SEC_USB1_S_WIDTH 1
2442 /* The mask used to set the ALT_L3_SEC_USB1_S register field value. */
2443 #define ALT_L3_SEC_USB1_S_SET_MSK 0x00000001
2444 /* The mask used to clear the ALT_L3_SEC_USB1_S register field value. */
2445 #define ALT_L3_SEC_USB1_S_CLR_MSK 0xfffffffe
2446 /* The reset value of the ALT_L3_SEC_USB1_S register field. */
2447 #define ALT_L3_SEC_USB1_S_RESET 0x0
2448 /* Extracts the ALT_L3_SEC_USB1_S field value from a register. */
2449 #define ALT_L3_SEC_USB1_S_GET(value) (((value) & 0x00000001) >> 0)
2450 /* Produces a ALT_L3_SEC_USB1_S register field value suitable for setting the register. */
2451 #define ALT_L3_SEC_USB1_S_SET(value) (((value) << 0) & 0x00000001)
2452 
2453 #ifndef __ASSEMBLY__
2454 /*
2455  * WARNING: The C register and register group struct declarations are provided for
2456  * convenience and illustrative purposes. They should, however, be used with
2457  * caution as the C language standard provides no guarantees about the alignment or
2458  * atomicity of device memory accesses. The recommended practice for writing
2459  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2460  * alt_write_word() functions.
2461  *
2462  * The struct declaration for register ALT_L3_SEC_USB1.
2463  */
2465 {
2466  uint32_t s : 1; /* USB1 Registers Security */
2467  uint32_t : 31; /* *UNDEFINED* */
2468 };
2469 
2470 /* The typedef declaration for register ALT_L3_SEC_USB1. */
2471 typedef volatile struct ALT_L3_SEC_USB1_s ALT_L3_SEC_USB1_t;
2472 #endif /* __ASSEMBLY__ */
2473 
2474 /* The byte offset of the ALT_L3_SEC_USB1 register from the beginning of the component. */
2475 #define ALT_L3_SEC_USB1_OFST 0x20
2476 
2477 /*
2478  * Register : NAND Flash Controller Data Peripheral Security - nanddata
2479  *
2480  * Controls security settings for NAND Flash Controller Data peripheral.
2481  *
2482  * Register Layout
2483  *
2484  * Bits | Access | Reset | Description
2485  * :-------|:-------|:------|:------------------------------------
2486  * [0] | W | 0x0 | NAND Flash Controller Data Security
2487  * [31:1] | ??? | 0x0 | *UNDEFINED*
2488  *
2489  */
2490 /*
2491  * Field : NAND Flash Controller Data Security - s
2492  *
2493  * Controls whether secure or non-secure masters can access the NAND Flash
2494  * Controller Data slave.
2495  *
2496  * Field Enumeration Values:
2497  *
2498  * Enum | Value | Description
2499  * :----------------------------------|:------|:----------------------------------------------
2500  * ALT_L3_SEC_NANDDATA_S_E_SECURE | 0x0 | The slave can only be accessed by a secure
2501  * : | | master.
2502  * ALT_L3_SEC_NANDDATA_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
2503  * : | | non-secure masters.
2504  *
2505  * Field Access Macros:
2506  *
2507  */
2508 /*
2509  * Enumerated value for register field ALT_L3_SEC_NANDDATA_S
2510  *
2511  * The slave can only be accessed by a secure master.
2512  */
2513 #define ALT_L3_SEC_NANDDATA_S_E_SECURE 0x0
2514 /*
2515  * Enumerated value for register field ALT_L3_SEC_NANDDATA_S
2516  *
2517  * The slave can only be accessed by a secure or non-secure masters.
2518  */
2519 #define ALT_L3_SEC_NANDDATA_S_E_NONSECURE 0x1
2520 
2521 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_NANDDATA_S register field. */
2522 #define ALT_L3_SEC_NANDDATA_S_LSB 0
2523 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_NANDDATA_S register field. */
2524 #define ALT_L3_SEC_NANDDATA_S_MSB 0
2525 /* The width in bits of the ALT_L3_SEC_NANDDATA_S register field. */
2526 #define ALT_L3_SEC_NANDDATA_S_WIDTH 1
2527 /* The mask used to set the ALT_L3_SEC_NANDDATA_S register field value. */
2528 #define ALT_L3_SEC_NANDDATA_S_SET_MSK 0x00000001
2529 /* The mask used to clear the ALT_L3_SEC_NANDDATA_S register field value. */
2530 #define ALT_L3_SEC_NANDDATA_S_CLR_MSK 0xfffffffe
2531 /* The reset value of the ALT_L3_SEC_NANDDATA_S register field. */
2532 #define ALT_L3_SEC_NANDDATA_S_RESET 0x0
2533 /* Extracts the ALT_L3_SEC_NANDDATA_S field value from a register. */
2534 #define ALT_L3_SEC_NANDDATA_S_GET(value) (((value) & 0x00000001) >> 0)
2535 /* Produces a ALT_L3_SEC_NANDDATA_S register field value suitable for setting the register. */
2536 #define ALT_L3_SEC_NANDDATA_S_SET(value) (((value) << 0) & 0x00000001)
2537 
2538 #ifndef __ASSEMBLY__
2539 /*
2540  * WARNING: The C register and register group struct declarations are provided for
2541  * convenience and illustrative purposes. They should, however, be used with
2542  * caution as the C language standard provides no guarantees about the alignment or
2543  * atomicity of device memory accesses. The recommended practice for writing
2544  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2545  * alt_write_word() functions.
2546  *
2547  * The struct declaration for register ALT_L3_SEC_NANDDATA.
2548  */
2550 {
2551  uint32_t s : 1; /* NAND Flash Controller Data Security */
2552  uint32_t : 31; /* *UNDEFINED* */
2553 };
2554 
2555 /* The typedef declaration for register ALT_L3_SEC_NANDDATA. */
2556 typedef volatile struct ALT_L3_SEC_NANDDATA_s ALT_L3_SEC_NANDDATA_t;
2557 #endif /* __ASSEMBLY__ */
2558 
2559 /* The byte offset of the ALT_L3_SEC_NANDDATA register from the beginning of the component. */
2560 #define ALT_L3_SEC_NANDDATA_OFST 0x24
2561 
2562 /*
2563  * Register : USB0 Registers Peripheral Security - usb0
2564  *
2565  * Controls security settings for USB0 Registers peripheral.
2566  *
2567  * Register Layout
2568  *
2569  * Bits | Access | Reset | Description
2570  * :-------|:-------|:------|:------------------------
2571  * [0] | W | 0x0 | USB0 Registers Security
2572  * [31:1] | ??? | 0x0 | *UNDEFINED*
2573  *
2574  */
2575 /*
2576  * Field : USB0 Registers Security - s
2577  *
2578  * Controls whether secure or non-secure masters can access the USB0 Registers
2579  * slave.
2580  *
2581  * Field Enumeration Values:
2582  *
2583  * Enum | Value | Description
2584  * :------------------------------|:------|:----------------------------------------------
2585  * ALT_L3_SEC_USB0_S_E_SECURE | 0x0 | The slave can only be accessed by a secure
2586  * : | | master.
2587  * ALT_L3_SEC_USB0_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
2588  * : | | non-secure masters.
2589  *
2590  * Field Access Macros:
2591  *
2592  */
2593 /*
2594  * Enumerated value for register field ALT_L3_SEC_USB0_S
2595  *
2596  * The slave can only be accessed by a secure master.
2597  */
2598 #define ALT_L3_SEC_USB0_S_E_SECURE 0x0
2599 /*
2600  * Enumerated value for register field ALT_L3_SEC_USB0_S
2601  *
2602  * The slave can only be accessed by a secure or non-secure masters.
2603  */
2604 #define ALT_L3_SEC_USB0_S_E_NONSECURE 0x1
2605 
2606 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_USB0_S register field. */
2607 #define ALT_L3_SEC_USB0_S_LSB 0
2608 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_USB0_S register field. */
2609 #define ALT_L3_SEC_USB0_S_MSB 0
2610 /* The width in bits of the ALT_L3_SEC_USB0_S register field. */
2611 #define ALT_L3_SEC_USB0_S_WIDTH 1
2612 /* The mask used to set the ALT_L3_SEC_USB0_S register field value. */
2613 #define ALT_L3_SEC_USB0_S_SET_MSK 0x00000001
2614 /* The mask used to clear the ALT_L3_SEC_USB0_S register field value. */
2615 #define ALT_L3_SEC_USB0_S_CLR_MSK 0xfffffffe
2616 /* The reset value of the ALT_L3_SEC_USB0_S register field. */
2617 #define ALT_L3_SEC_USB0_S_RESET 0x0
2618 /* Extracts the ALT_L3_SEC_USB0_S field value from a register. */
2619 #define ALT_L3_SEC_USB0_S_GET(value) (((value) & 0x00000001) >> 0)
2620 /* Produces a ALT_L3_SEC_USB0_S register field value suitable for setting the register. */
2621 #define ALT_L3_SEC_USB0_S_SET(value) (((value) << 0) & 0x00000001)
2622 
2623 #ifndef __ASSEMBLY__
2624 /*
2625  * WARNING: The C register and register group struct declarations are provided for
2626  * convenience and illustrative purposes. They should, however, be used with
2627  * caution as the C language standard provides no guarantees about the alignment or
2628  * atomicity of device memory accesses. The recommended practice for writing
2629  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2630  * alt_write_word() functions.
2631  *
2632  * The struct declaration for register ALT_L3_SEC_USB0.
2633  */
2635 {
2636  uint32_t s : 1; /* USB0 Registers Security */
2637  uint32_t : 31; /* *UNDEFINED* */
2638 };
2639 
2640 /* The typedef declaration for register ALT_L3_SEC_USB0. */
2641 typedef volatile struct ALT_L3_SEC_USB0_s ALT_L3_SEC_USB0_t;
2642 #endif /* __ASSEMBLY__ */
2643 
2644 /* The byte offset of the ALT_L3_SEC_USB0 register from the beginning of the component. */
2645 #define ALT_L3_SEC_USB0_OFST 0x78
2646 
2647 /*
2648  * Register : NAND Flash Controller Registers Peripheral Security - nandregs
2649  *
2650  * Controls security settings for NAND Flash Controller Registers peripheral.
2651  *
2652  * Register Layout
2653  *
2654  * Bits | Access | Reset | Description
2655  * :-------|:-------|:------|:-----------------------------------------
2656  * [0] | W | 0x0 | NAND Flash Controller Registers Security
2657  * [31:1] | ??? | 0x0 | *UNDEFINED*
2658  *
2659  */
2660 /*
2661  * Field : NAND Flash Controller Registers Security - s
2662  *
2663  * Controls whether secure or non-secure masters can access the NAND Flash
2664  * Controller Registers slave.
2665  *
2666  * Field Enumeration Values:
2667  *
2668  * Enum | Value | Description
2669  * :------------------------------|:------|:----------------------------------------------
2670  * ALT_L3_SEC_NAND_S_E_SECURE | 0x0 | The slave can only be accessed by a secure
2671  * : | | master.
2672  * ALT_L3_SEC_NAND_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
2673  * : | | non-secure masters.
2674  *
2675  * Field Access Macros:
2676  *
2677  */
2678 /*
2679  * Enumerated value for register field ALT_L3_SEC_NAND_S
2680  *
2681  * The slave can only be accessed by a secure master.
2682  */
2683 #define ALT_L3_SEC_NAND_S_E_SECURE 0x0
2684 /*
2685  * Enumerated value for register field ALT_L3_SEC_NAND_S
2686  *
2687  * The slave can only be accessed by a secure or non-secure masters.
2688  */
2689 #define ALT_L3_SEC_NAND_S_E_NONSECURE 0x1
2690 
2691 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_NAND_S register field. */
2692 #define ALT_L3_SEC_NAND_S_LSB 0
2693 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_NAND_S register field. */
2694 #define ALT_L3_SEC_NAND_S_MSB 0
2695 /* The width in bits of the ALT_L3_SEC_NAND_S register field. */
2696 #define ALT_L3_SEC_NAND_S_WIDTH 1
2697 /* The mask used to set the ALT_L3_SEC_NAND_S register field value. */
2698 #define ALT_L3_SEC_NAND_S_SET_MSK 0x00000001
2699 /* The mask used to clear the ALT_L3_SEC_NAND_S register field value. */
2700 #define ALT_L3_SEC_NAND_S_CLR_MSK 0xfffffffe
2701 /* The reset value of the ALT_L3_SEC_NAND_S register field. */
2702 #define ALT_L3_SEC_NAND_S_RESET 0x0
2703 /* Extracts the ALT_L3_SEC_NAND_S field value from a register. */
2704 #define ALT_L3_SEC_NAND_S_GET(value) (((value) & 0x00000001) >> 0)
2705 /* Produces a ALT_L3_SEC_NAND_S register field value suitable for setting the register. */
2706 #define ALT_L3_SEC_NAND_S_SET(value) (((value) << 0) & 0x00000001)
2707 
2708 #ifndef __ASSEMBLY__
2709 /*
2710  * WARNING: The C register and register group struct declarations are provided for
2711  * convenience and illustrative purposes. They should, however, be used with
2712  * caution as the C language standard provides no guarantees about the alignment or
2713  * atomicity of device memory accesses. The recommended practice for writing
2714  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2715  * alt_write_word() functions.
2716  *
2717  * The struct declaration for register ALT_L3_SEC_NAND.
2718  */
2720 {
2721  uint32_t s : 1; /* NAND Flash Controller Registers Security */
2722  uint32_t : 31; /* *UNDEFINED* */
2723 };
2724 
2725 /* The typedef declaration for register ALT_L3_SEC_NAND. */
2726 typedef volatile struct ALT_L3_SEC_NAND_s ALT_L3_SEC_NAND_t;
2727 #endif /* __ASSEMBLY__ */
2728 
2729 /* The byte offset of the ALT_L3_SEC_NAND register from the beginning of the component. */
2730 #define ALT_L3_SEC_NAND_OFST 0x7c
2731 
2732 /*
2733  * Register : QSPI Flash Controller Data Peripheral Security - qspidata
2734  *
2735  * Controls security settings for QSPI Flash Controller Data peripheral.
2736  *
2737  * Register Layout
2738  *
2739  * Bits | Access | Reset | Description
2740  * :-------|:-------|:------|:------------------------------------
2741  * [0] | W | 0x0 | QSPI Flash Controller Data Security
2742  * [31:1] | ??? | 0x0 | *UNDEFINED*
2743  *
2744  */
2745 /*
2746  * Field : QSPI Flash Controller Data Security - s
2747  *
2748  * Controls whether secure or non-secure masters can access the QSPI Flash
2749  * Controller Data slave.
2750  *
2751  * Field Enumeration Values:
2752  *
2753  * Enum | Value | Description
2754  * :----------------------------------|:------|:----------------------------------------------
2755  * ALT_L3_SEC_QSPIDATA_S_E_SECURE | 0x0 | The slave can only be accessed by a secure
2756  * : | | master.
2757  * ALT_L3_SEC_QSPIDATA_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
2758  * : | | non-secure masters.
2759  *
2760  * Field Access Macros:
2761  *
2762  */
2763 /*
2764  * Enumerated value for register field ALT_L3_SEC_QSPIDATA_S
2765  *
2766  * The slave can only be accessed by a secure master.
2767  */
2768 #define ALT_L3_SEC_QSPIDATA_S_E_SECURE 0x0
2769 /*
2770  * Enumerated value for register field ALT_L3_SEC_QSPIDATA_S
2771  *
2772  * The slave can only be accessed by a secure or non-secure masters.
2773  */
2774 #define ALT_L3_SEC_QSPIDATA_S_E_NONSECURE 0x1
2775 
2776 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_QSPIDATA_S register field. */
2777 #define ALT_L3_SEC_QSPIDATA_S_LSB 0
2778 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_QSPIDATA_S register field. */
2779 #define ALT_L3_SEC_QSPIDATA_S_MSB 0
2780 /* The width in bits of the ALT_L3_SEC_QSPIDATA_S register field. */
2781 #define ALT_L3_SEC_QSPIDATA_S_WIDTH 1
2782 /* The mask used to set the ALT_L3_SEC_QSPIDATA_S register field value. */
2783 #define ALT_L3_SEC_QSPIDATA_S_SET_MSK 0x00000001
2784 /* The mask used to clear the ALT_L3_SEC_QSPIDATA_S register field value. */
2785 #define ALT_L3_SEC_QSPIDATA_S_CLR_MSK 0xfffffffe
2786 /* The reset value of the ALT_L3_SEC_QSPIDATA_S register field. */
2787 #define ALT_L3_SEC_QSPIDATA_S_RESET 0x0
2788 /* Extracts the ALT_L3_SEC_QSPIDATA_S field value from a register. */
2789 #define ALT_L3_SEC_QSPIDATA_S_GET(value) (((value) & 0x00000001) >> 0)
2790 /* Produces a ALT_L3_SEC_QSPIDATA_S register field value suitable for setting the register. */
2791 #define ALT_L3_SEC_QSPIDATA_S_SET(value) (((value) << 0) & 0x00000001)
2792 
2793 #ifndef __ASSEMBLY__
2794 /*
2795  * WARNING: The C register and register group struct declarations are provided for
2796  * convenience and illustrative purposes. They should, however, be used with
2797  * caution as the C language standard provides no guarantees about the alignment or
2798  * atomicity of device memory accesses. The recommended practice for writing
2799  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2800  * alt_write_word() functions.
2801  *
2802  * The struct declaration for register ALT_L3_SEC_QSPIDATA.
2803  */
2805 {
2806  uint32_t s : 1; /* QSPI Flash Controller Data Security */
2807  uint32_t : 31; /* *UNDEFINED* */
2808 };
2809 
2810 /* The typedef declaration for register ALT_L3_SEC_QSPIDATA. */
2811 typedef volatile struct ALT_L3_SEC_QSPIDATA_s ALT_L3_SEC_QSPIDATA_t;
2812 #endif /* __ASSEMBLY__ */
2813 
2814 /* The byte offset of the ALT_L3_SEC_QSPIDATA register from the beginning of the component. */
2815 #define ALT_L3_SEC_QSPIDATA_OFST 0x80
2816 
2817 /*
2818  * Register : FPGA Manager Data Peripheral Security - fpgamgrdata
2819  *
2820  * Controls security settings for FPGA Manager Data peripheral.
2821  *
2822  * Register Layout
2823  *
2824  * Bits | Access | Reset | Description
2825  * :-------|:-------|:------|:---------------------------
2826  * [0] | W | 0x0 | FPGA Manager Data Security
2827  * [31:1] | ??? | 0x0 | *UNDEFINED*
2828  *
2829  */
2830 /*
2831  * Field : FPGA Manager Data Security - s
2832  *
2833  * Controls whether secure or non-secure masters can access the FPGA Manager Data
2834  * slave.
2835  *
2836  * Field Enumeration Values:
2837  *
2838  * Enum | Value | Description
2839  * :-------------------------------------|:------|:----------------------------------------------
2840  * ALT_L3_SEC_FPGAMGRDATA_S_E_SECURE | 0x0 | The slave can only be accessed by a secure
2841  * : | | master.
2842  * ALT_L3_SEC_FPGAMGRDATA_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
2843  * : | | non-secure masters.
2844  *
2845  * Field Access Macros:
2846  *
2847  */
2848 /*
2849  * Enumerated value for register field ALT_L3_SEC_FPGAMGRDATA_S
2850  *
2851  * The slave can only be accessed by a secure master.
2852  */
2853 #define ALT_L3_SEC_FPGAMGRDATA_S_E_SECURE 0x0
2854 /*
2855  * Enumerated value for register field ALT_L3_SEC_FPGAMGRDATA_S
2856  *
2857  * The slave can only be accessed by a secure or non-secure masters.
2858  */
2859 #define ALT_L3_SEC_FPGAMGRDATA_S_E_NONSECURE 0x1
2860 
2861 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_FPGAMGRDATA_S register field. */
2862 #define ALT_L3_SEC_FPGAMGRDATA_S_LSB 0
2863 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_FPGAMGRDATA_S register field. */
2864 #define ALT_L3_SEC_FPGAMGRDATA_S_MSB 0
2865 /* The width in bits of the ALT_L3_SEC_FPGAMGRDATA_S register field. */
2866 #define ALT_L3_SEC_FPGAMGRDATA_S_WIDTH 1
2867 /* The mask used to set the ALT_L3_SEC_FPGAMGRDATA_S register field value. */
2868 #define ALT_L3_SEC_FPGAMGRDATA_S_SET_MSK 0x00000001
2869 /* The mask used to clear the ALT_L3_SEC_FPGAMGRDATA_S register field value. */
2870 #define ALT_L3_SEC_FPGAMGRDATA_S_CLR_MSK 0xfffffffe
2871 /* The reset value of the ALT_L3_SEC_FPGAMGRDATA_S register field. */
2872 #define ALT_L3_SEC_FPGAMGRDATA_S_RESET 0x0
2873 /* Extracts the ALT_L3_SEC_FPGAMGRDATA_S field value from a register. */
2874 #define ALT_L3_SEC_FPGAMGRDATA_S_GET(value) (((value) & 0x00000001) >> 0)
2875 /* Produces a ALT_L3_SEC_FPGAMGRDATA_S register field value suitable for setting the register. */
2876 #define ALT_L3_SEC_FPGAMGRDATA_S_SET(value) (((value) << 0) & 0x00000001)
2877 
2878 #ifndef __ASSEMBLY__
2879 /*
2880  * WARNING: The C register and register group struct declarations are provided for
2881  * convenience and illustrative purposes. They should, however, be used with
2882  * caution as the C language standard provides no guarantees about the alignment or
2883  * atomicity of device memory accesses. The recommended practice for writing
2884  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2885  * alt_write_word() functions.
2886  *
2887  * The struct declaration for register ALT_L3_SEC_FPGAMGRDATA.
2888  */
2890 {
2891  uint32_t s : 1; /* FPGA Manager Data Security */
2892  uint32_t : 31; /* *UNDEFINED* */
2893 };
2894 
2895 /* The typedef declaration for register ALT_L3_SEC_FPGAMGRDATA. */
2896 typedef volatile struct ALT_L3_SEC_FPGAMGRDATA_s ALT_L3_SEC_FPGAMGRDATA_t;
2897 #endif /* __ASSEMBLY__ */
2898 
2899 /* The byte offset of the ALT_L3_SEC_FPGAMGRDATA register from the beginning of the component. */
2900 #define ALT_L3_SEC_FPGAMGRDATA_OFST 0x84
2901 
2902 /*
2903  * Register : HPS2FPGA AXI Bridge Registers Peripheral Security - hps2fpgaregs
2904  *
2905  * Controls security settings for HPS2FPGA AXI Bridge Registers peripheral.
2906  *
2907  * Register Layout
2908  *
2909  * Bits | Access | Reset | Description
2910  * :-------|:-------|:------|:---------------------------------------
2911  * [0] | W | 0x0 | HPS2FPGA AXI Bridge Registers Security
2912  * [31:1] | ??? | 0x0 | *UNDEFINED*
2913  *
2914  */
2915 /*
2916  * Field : HPS2FPGA AXI Bridge Registers Security - s
2917  *
2918  * Controls whether secure or non-secure masters can access the HPS2FPGA AXI Bridge
2919  * Registers slave.
2920  *
2921  * Field Enumeration Values:
2922  *
2923  * Enum | Value | Description
2924  * :-----------------------------|:------|:----------------------------------------------
2925  * ALT_L3_SEC_H2F_S_E_SECURE | 0x0 | The slave can only be accessed by a secure
2926  * : | | master.
2927  * ALT_L3_SEC_H2F_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
2928  * : | | non-secure masters.
2929  *
2930  * Field Access Macros:
2931  *
2932  */
2933 /*
2934  * Enumerated value for register field ALT_L3_SEC_H2F_S
2935  *
2936  * The slave can only be accessed by a secure master.
2937  */
2938 #define ALT_L3_SEC_H2F_S_E_SECURE 0x0
2939 /*
2940  * Enumerated value for register field ALT_L3_SEC_H2F_S
2941  *
2942  * The slave can only be accessed by a secure or non-secure masters.
2943  */
2944 #define ALT_L3_SEC_H2F_S_E_NONSECURE 0x1
2945 
2946 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_H2F_S register field. */
2947 #define ALT_L3_SEC_H2F_S_LSB 0
2948 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_H2F_S register field. */
2949 #define ALT_L3_SEC_H2F_S_MSB 0
2950 /* The width in bits of the ALT_L3_SEC_H2F_S register field. */
2951 #define ALT_L3_SEC_H2F_S_WIDTH 1
2952 /* The mask used to set the ALT_L3_SEC_H2F_S register field value. */
2953 #define ALT_L3_SEC_H2F_S_SET_MSK 0x00000001
2954 /* The mask used to clear the ALT_L3_SEC_H2F_S register field value. */
2955 #define ALT_L3_SEC_H2F_S_CLR_MSK 0xfffffffe
2956 /* The reset value of the ALT_L3_SEC_H2F_S register field. */
2957 #define ALT_L3_SEC_H2F_S_RESET 0x0
2958 /* Extracts the ALT_L3_SEC_H2F_S field value from a register. */
2959 #define ALT_L3_SEC_H2F_S_GET(value) (((value) & 0x00000001) >> 0)
2960 /* Produces a ALT_L3_SEC_H2F_S register field value suitable for setting the register. */
2961 #define ALT_L3_SEC_H2F_S_SET(value) (((value) << 0) & 0x00000001)
2962 
2963 #ifndef __ASSEMBLY__
2964 /*
2965  * WARNING: The C register and register group struct declarations are provided for
2966  * convenience and illustrative purposes. They should, however, be used with
2967  * caution as the C language standard provides no guarantees about the alignment or
2968  * atomicity of device memory accesses. The recommended practice for writing
2969  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2970  * alt_write_word() functions.
2971  *
2972  * The struct declaration for register ALT_L3_SEC_H2F.
2973  */
2975 {
2976  uint32_t s : 1; /* HPS2FPGA AXI Bridge Registers Security */
2977  uint32_t : 31; /* *UNDEFINED* */
2978 };
2979 
2980 /* The typedef declaration for register ALT_L3_SEC_H2F. */
2981 typedef volatile struct ALT_L3_SEC_H2F_s ALT_L3_SEC_H2F_t;
2982 #endif /* __ASSEMBLY__ */
2983 
2984 /* The byte offset of the ALT_L3_SEC_H2F register from the beginning of the component. */
2985 #define ALT_L3_SEC_H2F_OFST 0x88
2986 
2987 /*
2988  * Register : MPU ACP Peripheral Security - acp
2989  *
2990  * Controls security settings for MPU ACP peripheral.
2991  *
2992  * Register Layout
2993  *
2994  * Bits | Access | Reset | Description
2995  * :-------|:-------|:------|:-----------------
2996  * [0] | W | 0x0 | MPU ACP Security
2997  * [31:1] | ??? | 0x0 | *UNDEFINED*
2998  *
2999  */
3000 /*
3001  * Field : MPU ACP Security - s
3002  *
3003  * Controls whether secure or non-secure masters can access the MPU ACP slave.
3004  *
3005  * Field Enumeration Values:
3006  *
3007  * Enum | Value | Description
3008  * :-----------------------------|:------|:----------------------------------------------
3009  * ALT_L3_SEC_ACP_S_E_SECURE | 0x0 | The slave can only be accessed by a secure
3010  * : | | master.
3011  * ALT_L3_SEC_ACP_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
3012  * : | | non-secure masters.
3013  *
3014  * Field Access Macros:
3015  *
3016  */
3017 /*
3018  * Enumerated value for register field ALT_L3_SEC_ACP_S
3019  *
3020  * The slave can only be accessed by a secure master.
3021  */
3022 #define ALT_L3_SEC_ACP_S_E_SECURE 0x0
3023 /*
3024  * Enumerated value for register field ALT_L3_SEC_ACP_S
3025  *
3026  * The slave can only be accessed by a secure or non-secure masters.
3027  */
3028 #define ALT_L3_SEC_ACP_S_E_NONSECURE 0x1
3029 
3030 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_ACP_S register field. */
3031 #define ALT_L3_SEC_ACP_S_LSB 0
3032 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_ACP_S register field. */
3033 #define ALT_L3_SEC_ACP_S_MSB 0
3034 /* The width in bits of the ALT_L3_SEC_ACP_S register field. */
3035 #define ALT_L3_SEC_ACP_S_WIDTH 1
3036 /* The mask used to set the ALT_L3_SEC_ACP_S register field value. */
3037 #define ALT_L3_SEC_ACP_S_SET_MSK 0x00000001
3038 /* The mask used to clear the ALT_L3_SEC_ACP_S register field value. */
3039 #define ALT_L3_SEC_ACP_S_CLR_MSK 0xfffffffe
3040 /* The reset value of the ALT_L3_SEC_ACP_S register field. */
3041 #define ALT_L3_SEC_ACP_S_RESET 0x0
3042 /* Extracts the ALT_L3_SEC_ACP_S field value from a register. */
3043 #define ALT_L3_SEC_ACP_S_GET(value) (((value) & 0x00000001) >> 0)
3044 /* Produces a ALT_L3_SEC_ACP_S register field value suitable for setting the register. */
3045 #define ALT_L3_SEC_ACP_S_SET(value) (((value) << 0) & 0x00000001)
3046 
3047 #ifndef __ASSEMBLY__
3048 /*
3049  * WARNING: The C register and register group struct declarations are provided for
3050  * convenience and illustrative purposes. They should, however, be used with
3051  * caution as the C language standard provides no guarantees about the alignment or
3052  * atomicity of device memory accesses. The recommended practice for writing
3053  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3054  * alt_write_word() functions.
3055  *
3056  * The struct declaration for register ALT_L3_SEC_ACP.
3057  */
3059 {
3060  uint32_t s : 1; /* MPU ACP Security */
3061  uint32_t : 31; /* *UNDEFINED* */
3062 };
3063 
3064 /* The typedef declaration for register ALT_L3_SEC_ACP. */
3065 typedef volatile struct ALT_L3_SEC_ACP_s ALT_L3_SEC_ACP_t;
3066 #endif /* __ASSEMBLY__ */
3067 
3068 /* The byte offset of the ALT_L3_SEC_ACP register from the beginning of the component. */
3069 #define ALT_L3_SEC_ACP_OFST 0x8c
3070 
3071 /*
3072  * Register : ROM Peripheral Security - rom
3073  *
3074  * Controls security settings for ROM peripheral.
3075  *
3076  * Register Layout
3077  *
3078  * Bits | Access | Reset | Description
3079  * :-------|:-------|:------|:-------------
3080  * [0] | W | 0x0 | ROM Security
3081  * [31:1] | ??? | 0x0 | *UNDEFINED*
3082  *
3083  */
3084 /*
3085  * Field : ROM Security - s
3086  *
3087  * Controls whether secure or non-secure masters can access the ROM slave.
3088  *
3089  * Field Enumeration Values:
3090  *
3091  * Enum | Value | Description
3092  * :-----------------------------|:------|:----------------------------------------------
3093  * ALT_L3_SEC_ROM_S_E_SECURE | 0x0 | The slave can only be accessed by a secure
3094  * : | | master.
3095  * ALT_L3_SEC_ROM_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
3096  * : | | non-secure masters.
3097  *
3098  * Field Access Macros:
3099  *
3100  */
3101 /*
3102  * Enumerated value for register field ALT_L3_SEC_ROM_S
3103  *
3104  * The slave can only be accessed by a secure master.
3105  */
3106 #define ALT_L3_SEC_ROM_S_E_SECURE 0x0
3107 /*
3108  * Enumerated value for register field ALT_L3_SEC_ROM_S
3109  *
3110  * The slave can only be accessed by a secure or non-secure masters.
3111  */
3112 #define ALT_L3_SEC_ROM_S_E_NONSECURE 0x1
3113 
3114 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_ROM_S register field. */
3115 #define ALT_L3_SEC_ROM_S_LSB 0
3116 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_ROM_S register field. */
3117 #define ALT_L3_SEC_ROM_S_MSB 0
3118 /* The width in bits of the ALT_L3_SEC_ROM_S register field. */
3119 #define ALT_L3_SEC_ROM_S_WIDTH 1
3120 /* The mask used to set the ALT_L3_SEC_ROM_S register field value. */
3121 #define ALT_L3_SEC_ROM_S_SET_MSK 0x00000001
3122 /* The mask used to clear the ALT_L3_SEC_ROM_S register field value. */
3123 #define ALT_L3_SEC_ROM_S_CLR_MSK 0xfffffffe
3124 /* The reset value of the ALT_L3_SEC_ROM_S register field. */
3125 #define ALT_L3_SEC_ROM_S_RESET 0x0
3126 /* Extracts the ALT_L3_SEC_ROM_S field value from a register. */
3127 #define ALT_L3_SEC_ROM_S_GET(value) (((value) & 0x00000001) >> 0)
3128 /* Produces a ALT_L3_SEC_ROM_S register field value suitable for setting the register. */
3129 #define ALT_L3_SEC_ROM_S_SET(value) (((value) << 0) & 0x00000001)
3130 
3131 #ifndef __ASSEMBLY__
3132 /*
3133  * WARNING: The C register and register group struct declarations are provided for
3134  * convenience and illustrative purposes. They should, however, be used with
3135  * caution as the C language standard provides no guarantees about the alignment or
3136  * atomicity of device memory accesses. The recommended practice for writing
3137  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3138  * alt_write_word() functions.
3139  *
3140  * The struct declaration for register ALT_L3_SEC_ROM.
3141  */
3143 {
3144  uint32_t s : 1; /* ROM Security */
3145  uint32_t : 31; /* *UNDEFINED* */
3146 };
3147 
3148 /* The typedef declaration for register ALT_L3_SEC_ROM. */
3149 typedef volatile struct ALT_L3_SEC_ROM_s ALT_L3_SEC_ROM_t;
3150 #endif /* __ASSEMBLY__ */
3151 
3152 /* The byte offset of the ALT_L3_SEC_ROM register from the beginning of the component. */
3153 #define ALT_L3_SEC_ROM_OFST 0x90
3154 
3155 /*
3156  * Register : On-chip RAM Peripheral Security - ocram
3157  *
3158  * Controls security settings for On-chip RAM peripheral.
3159  *
3160  * Register Layout
3161  *
3162  * Bits | Access | Reset | Description
3163  * :-------|:-------|:------|:---------------------
3164  * [0] | W | 0x0 | On-chip RAM Security
3165  * [31:1] | ??? | 0x0 | *UNDEFINED*
3166  *
3167  */
3168 /*
3169  * Field : On-chip RAM Security - s
3170  *
3171  * Controls whether secure or non-secure masters can access the On-chip RAM slave.
3172  *
3173  * Field Enumeration Values:
3174  *
3175  * Enum | Value | Description
3176  * :-------------------------------|:------|:----------------------------------------------
3177  * ALT_L3_SEC_OCRAM_S_E_SECURE | 0x0 | The slave can only be accessed by a secure
3178  * : | | master.
3179  * ALT_L3_SEC_OCRAM_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
3180  * : | | non-secure masters.
3181  *
3182  * Field Access Macros:
3183  *
3184  */
3185 /*
3186  * Enumerated value for register field ALT_L3_SEC_OCRAM_S
3187  *
3188  * The slave can only be accessed by a secure master.
3189  */
3190 #define ALT_L3_SEC_OCRAM_S_E_SECURE 0x0
3191 /*
3192  * Enumerated value for register field ALT_L3_SEC_OCRAM_S
3193  *
3194  * The slave can only be accessed by a secure or non-secure masters.
3195  */
3196 #define ALT_L3_SEC_OCRAM_S_E_NONSECURE 0x1
3197 
3198 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_OCRAM_S register field. */
3199 #define ALT_L3_SEC_OCRAM_S_LSB 0
3200 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_OCRAM_S register field. */
3201 #define ALT_L3_SEC_OCRAM_S_MSB 0
3202 /* The width in bits of the ALT_L3_SEC_OCRAM_S register field. */
3203 #define ALT_L3_SEC_OCRAM_S_WIDTH 1
3204 /* The mask used to set the ALT_L3_SEC_OCRAM_S register field value. */
3205 #define ALT_L3_SEC_OCRAM_S_SET_MSK 0x00000001
3206 /* The mask used to clear the ALT_L3_SEC_OCRAM_S register field value. */
3207 #define ALT_L3_SEC_OCRAM_S_CLR_MSK 0xfffffffe
3208 /* The reset value of the ALT_L3_SEC_OCRAM_S register field. */
3209 #define ALT_L3_SEC_OCRAM_S_RESET 0x0
3210 /* Extracts the ALT_L3_SEC_OCRAM_S field value from a register. */
3211 #define ALT_L3_SEC_OCRAM_S_GET(value) (((value) & 0x00000001) >> 0)
3212 /* Produces a ALT_L3_SEC_OCRAM_S register field value suitable for setting the register. */
3213 #define ALT_L3_SEC_OCRAM_S_SET(value) (((value) << 0) & 0x00000001)
3214 
3215 #ifndef __ASSEMBLY__
3216 /*
3217  * WARNING: The C register and register group struct declarations are provided for
3218  * convenience and illustrative purposes. They should, however, be used with
3219  * caution as the C language standard provides no guarantees about the alignment or
3220  * atomicity of device memory accesses. The recommended practice for writing
3221  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3222  * alt_write_word() functions.
3223  *
3224  * The struct declaration for register ALT_L3_SEC_OCRAM.
3225  */
3227 {
3228  uint32_t s : 1; /* On-chip RAM Security */
3229  uint32_t : 31; /* *UNDEFINED* */
3230 };
3231 
3232 /* The typedef declaration for register ALT_L3_SEC_OCRAM. */
3233 typedef volatile struct ALT_L3_SEC_OCRAM_s ALT_L3_SEC_OCRAM_t;
3234 #endif /* __ASSEMBLY__ */
3235 
3236 /* The byte offset of the ALT_L3_SEC_OCRAM register from the beginning of the component. */
3237 #define ALT_L3_SEC_OCRAM_OFST 0x94
3238 
3239 /*
3240  * Register : SDRAM Data Peripheral Security - sdrdata
3241  *
3242  * Controls security settings for SDRAM Data peripheral.
3243  *
3244  * Register Layout
3245  *
3246  * Bits | Access | Reset | Description
3247  * :-------|:-------|:------|:--------------------
3248  * [0] | W | 0x0 | SDRAM Data Security
3249  * [31:1] | ??? | 0x0 | *UNDEFINED*
3250  *
3251  */
3252 /*
3253  * Field : SDRAM Data Security - s
3254  *
3255  * Controls whether secure or non-secure masters can access the SDRAM Data slave.
3256  *
3257  * Field Enumeration Values:
3258  *
3259  * Enum | Value | Description
3260  * :---------------------------------|:------|:----------------------------------------------
3261  * ALT_L3_SEC_SDRDATA_S_E_SECURE | 0x0 | The slave can only be accessed by a secure
3262  * : | | master.
3263  * ALT_L3_SEC_SDRDATA_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
3264  * : | | non-secure masters.
3265  *
3266  * Field Access Macros:
3267  *
3268  */
3269 /*
3270  * Enumerated value for register field ALT_L3_SEC_SDRDATA_S
3271  *
3272  * The slave can only be accessed by a secure master.
3273  */
3274 #define ALT_L3_SEC_SDRDATA_S_E_SECURE 0x0
3275 /*
3276  * Enumerated value for register field ALT_L3_SEC_SDRDATA_S
3277  *
3278  * The slave can only be accessed by a secure or non-secure masters.
3279  */
3280 #define ALT_L3_SEC_SDRDATA_S_E_NONSECURE 0x1
3281 
3282 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_SDRDATA_S register field. */
3283 #define ALT_L3_SEC_SDRDATA_S_LSB 0
3284 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_SDRDATA_S register field. */
3285 #define ALT_L3_SEC_SDRDATA_S_MSB 0
3286 /* The width in bits of the ALT_L3_SEC_SDRDATA_S register field. */
3287 #define ALT_L3_SEC_SDRDATA_S_WIDTH 1
3288 /* The mask used to set the ALT_L3_SEC_SDRDATA_S register field value. */
3289 #define ALT_L3_SEC_SDRDATA_S_SET_MSK 0x00000001
3290 /* The mask used to clear the ALT_L3_SEC_SDRDATA_S register field value. */
3291 #define ALT_L3_SEC_SDRDATA_S_CLR_MSK 0xfffffffe
3292 /* The reset value of the ALT_L3_SEC_SDRDATA_S register field. */
3293 #define ALT_L3_SEC_SDRDATA_S_RESET 0x0
3294 /* Extracts the ALT_L3_SEC_SDRDATA_S field value from a register. */
3295 #define ALT_L3_SEC_SDRDATA_S_GET(value) (((value) & 0x00000001) >> 0)
3296 /* Produces a ALT_L3_SEC_SDRDATA_S register field value suitable for setting the register. */
3297 #define ALT_L3_SEC_SDRDATA_S_SET(value) (((value) << 0) & 0x00000001)
3298 
3299 #ifndef __ASSEMBLY__
3300 /*
3301  * WARNING: The C register and register group struct declarations are provided for
3302  * convenience and illustrative purposes. They should, however, be used with
3303  * caution as the C language standard provides no guarantees about the alignment or
3304  * atomicity of device memory accesses. The recommended practice for writing
3305  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3306  * alt_write_word() functions.
3307  *
3308  * The struct declaration for register ALT_L3_SEC_SDRDATA.
3309  */
3311 {
3312  uint32_t s : 1; /* SDRAM Data Security */
3313  uint32_t : 31; /* *UNDEFINED* */
3314 };
3315 
3316 /* The typedef declaration for register ALT_L3_SEC_SDRDATA. */
3317 typedef volatile struct ALT_L3_SEC_SDRDATA_s ALT_L3_SEC_SDRDATA_t;
3318 #endif /* __ASSEMBLY__ */
3319 
3320 /* The byte offset of the ALT_L3_SEC_SDRDATA register from the beginning of the component. */
3321 #define ALT_L3_SEC_SDRDATA_OFST 0x98
3322 
3323 #ifndef __ASSEMBLY__
3324 /*
3325  * WARNING: The C register and register group struct declarations are provided for
3326  * convenience and illustrative purposes. They should, however, be used with
3327  * caution as the C language standard provides no guarantees about the alignment or
3328  * atomicity of device memory accesses. The recommended practice for writing
3329  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3330  * alt_write_word() functions.
3331  *
3332  * The struct declaration for register group ALT_L3_SECGRP.
3333  */
3335 {
3336  volatile ALT_L3_SEC_L4MAIN_t l4main; /* ALT_L3_SEC_L4MAIN */
3337  volatile ALT_L3_SEC_L4SP_t l4sp; /* ALT_L3_SEC_L4SP */
3338  volatile ALT_L3_SEC_L4MP_t l4mp; /* ALT_L3_SEC_L4MP */
3339  volatile ALT_L3_SEC_L4OSC1_t l4osc1; /* ALT_L3_SEC_L4OSC1 */
3340  volatile ALT_L3_SEC_L4SPIM_t l4spim; /* ALT_L3_SEC_L4SPIM */
3341  volatile ALT_L3_SEC_STM_t stm; /* ALT_L3_SEC_STM */
3342  volatile ALT_L3_SEC_LWH2F_t lwhps2fpgaregs; /* ALT_L3_SEC_LWH2F */
3343  volatile uint32_t _pad_0x1c_0x1f; /* *UNDEFINED* */
3344  volatile ALT_L3_SEC_USB1_t usb1; /* ALT_L3_SEC_USB1 */
3345  volatile ALT_L3_SEC_NANDDATA_t nanddata; /* ALT_L3_SEC_NANDDATA */
3346  volatile uint32_t _pad_0x28_0x77[20]; /* *UNDEFINED* */
3347  volatile ALT_L3_SEC_USB0_t usb0; /* ALT_L3_SEC_USB0 */
3348  volatile ALT_L3_SEC_NAND_t nandregs; /* ALT_L3_SEC_NAND */
3349  volatile ALT_L3_SEC_QSPIDATA_t qspidata; /* ALT_L3_SEC_QSPIDATA */
3350  volatile ALT_L3_SEC_FPGAMGRDATA_t fpgamgrdata; /* ALT_L3_SEC_FPGAMGRDATA */
3351  volatile ALT_L3_SEC_H2F_t hps2fpgaregs; /* ALT_L3_SEC_H2F */
3352  volatile ALT_L3_SEC_ACP_t acp; /* ALT_L3_SEC_ACP */
3353  volatile ALT_L3_SEC_ROM_t rom; /* ALT_L3_SEC_ROM */
3354  volatile ALT_L3_SEC_OCRAM_t ocram; /* ALT_L3_SEC_OCRAM */
3355  volatile ALT_L3_SEC_SDRDATA_t sdrdata; /* ALT_L3_SEC_SDRDATA */
3356 };
3357 
3358 /* The typedef declaration for register group ALT_L3_SECGRP. */
3359 typedef volatile struct ALT_L3_SECGRP_s ALT_L3_SECGRP_t;
3360 /* The struct declaration for the raw register contents of register group ALT_L3_SECGRP. */
3362 {
3363  volatile uint32_t l4main; /* ALT_L3_SEC_L4MAIN */
3364  volatile uint32_t l4sp; /* ALT_L3_SEC_L4SP */
3365  volatile uint32_t l4mp; /* ALT_L3_SEC_L4MP */
3366  volatile uint32_t l4osc1; /* ALT_L3_SEC_L4OSC1 */
3367  volatile uint32_t l4spim; /* ALT_L3_SEC_L4SPIM */
3368  volatile uint32_t stm; /* ALT_L3_SEC_STM */
3369  volatile uint32_t lwhps2fpgaregs; /* ALT_L3_SEC_LWH2F */
3370  volatile uint32_t _pad_0x1c_0x1f; /* *UNDEFINED* */
3371  volatile uint32_t usb1; /* ALT_L3_SEC_USB1 */
3372  volatile uint32_t nanddata; /* ALT_L3_SEC_NANDDATA */
3373  volatile uint32_t _pad_0x28_0x77[20]; /* *UNDEFINED* */
3374  volatile uint32_t usb0; /* ALT_L3_SEC_USB0 */
3375  volatile uint32_t nandregs; /* ALT_L3_SEC_NAND */
3376  volatile uint32_t qspidata; /* ALT_L3_SEC_QSPIDATA */
3377  volatile uint32_t fpgamgrdata; /* ALT_L3_SEC_FPGAMGRDATA */
3378  volatile uint32_t hps2fpgaregs; /* ALT_L3_SEC_H2F */
3379  volatile uint32_t acp; /* ALT_L3_SEC_ACP */
3380  volatile uint32_t rom; /* ALT_L3_SEC_ROM */
3381  volatile uint32_t ocram; /* ALT_L3_SEC_OCRAM */
3382  volatile uint32_t sdrdata; /* ALT_L3_SEC_SDRDATA */
3383 };
3384 
3385 /* The typedef declaration for the raw register contents of register group ALT_L3_SECGRP. */
3386 typedef volatile struct ALT_L3_SECGRP_raw_s ALT_L3_SECGRP_raw_t;
3387 #endif /* __ASSEMBLY__ */
3388 
3389 
3390 /*
3391  * Register Group : ID Register Group - ALT_L3_IDGRP
3392  * ID Register Group
3393  *
3394  * Contains registers that identify the ARM NIC-301 IP Core.
3395  *
3396  */
3397 /*
3398  * Register : Peripheral ID4 Register - periph_id_4
3399  *
3400  * JEP106 continuation code
3401  *
3402  * Register Layout
3403  *
3404  * Bits | Access | Reset | Description
3405  * :-------|:-------|:------|:---------------
3406  * [7:0] | R | 0x4 | Peripheral ID4
3407  * [31:8] | ??? | 0x0 | *UNDEFINED*
3408  *
3409  */
3410 /*
3411  * Field : Peripheral ID4 - periph_id_4
3412  *
3413  * JEP106 continuation code
3414  *
3415  * Field Access Macros:
3416  *
3417  */
3418 /* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */
3419 #define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_LSB 0
3420 /* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */
3421 #define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_MSB 7
3422 /* The width in bits of the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */
3423 #define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_WIDTH 8
3424 /* The mask used to set the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field value. */
3425 #define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_SET_MSK 0x000000ff
3426 /* The mask used to clear the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field value. */
3427 #define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_CLR_MSK 0xffffff00
3428 /* The reset value of the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */
3429 #define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_RESET 0x4
3430 /* Extracts the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 field value from a register. */
3431 #define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_GET(value) (((value) & 0x000000ff) >> 0)
3432 /* Produces a ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field value suitable for setting the register. */
3433 #define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_SET(value) (((value) << 0) & 0x000000ff)
3434 
3435 #ifndef __ASSEMBLY__
3436 /*
3437  * WARNING: The C register and register group struct declarations are provided for
3438  * convenience and illustrative purposes. They should, however, be used with
3439  * caution as the C language standard provides no guarantees about the alignment or
3440  * atomicity of device memory accesses. The recommended practice for writing
3441  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3442  * alt_write_word() functions.
3443  *
3444  * The struct declaration for register ALT_L3_ID_PERIPH_ID_4.
3445  */
3447 {
3448  const uint32_t periph_id_4 : 8; /* Peripheral ID4 */
3449  uint32_t : 24; /* *UNDEFINED* */
3450 };
3451 
3452 /* The typedef declaration for register ALT_L3_ID_PERIPH_ID_4. */
3453 typedef volatile struct ALT_L3_ID_PERIPH_ID_4_s ALT_L3_ID_PERIPH_ID_4_t;
3454 #endif /* __ASSEMBLY__ */
3455 
3456 /* The byte offset of the ALT_L3_ID_PERIPH_ID_4 register from the beginning of the component. */
3457 #define ALT_L3_ID_PERIPH_ID_4_OFST 0xfd0
3458 
3459 /*
3460  * Register : Peripheral ID0 Register - periph_id_0
3461  *
3462  * Peripheral ID0
3463  *
3464  * Register Layout
3465  *
3466  * Bits | Access | Reset | Description
3467  * :-------|:-------|:------|:------------------
3468  * [7:0] | R | 0x1 | Part Number [7:0]
3469  * [31:8] | ??? | 0x0 | *UNDEFINED*
3470  *
3471  */
3472 /*
3473  * Field : Part Number [7:0] - pn7to0
3474  *
3475  * Part Number [7:0]
3476  *
3477  * Field Access Macros:
3478  *
3479  */
3480 /* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field. */
3481 #define ALT_L3_ID_PERIPH_ID_0_PN7TO0_LSB 0
3482 /* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field. */
3483 #define ALT_L3_ID_PERIPH_ID_0_PN7TO0_MSB 7
3484 /* The width in bits of the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field. */
3485 #define ALT_L3_ID_PERIPH_ID_0_PN7TO0_WIDTH 8
3486 /* The mask used to set the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field value. */
3487 #define ALT_L3_ID_PERIPH_ID_0_PN7TO0_SET_MSK 0x000000ff
3488 /* The mask used to clear the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field value. */
3489 #define ALT_L3_ID_PERIPH_ID_0_PN7TO0_CLR_MSK 0xffffff00
3490 /* The reset value of the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field. */
3491 #define ALT_L3_ID_PERIPH_ID_0_PN7TO0_RESET 0x1
3492 /* Extracts the ALT_L3_ID_PERIPH_ID_0_PN7TO0 field value from a register. */
3493 #define ALT_L3_ID_PERIPH_ID_0_PN7TO0_GET(value) (((value) & 0x000000ff) >> 0)
3494 /* Produces a ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field value suitable for setting the register. */
3495 #define ALT_L3_ID_PERIPH_ID_0_PN7TO0_SET(value) (((value) << 0) & 0x000000ff)
3496 
3497 #ifndef __ASSEMBLY__
3498 /*
3499  * WARNING: The C register and register group struct declarations are provided for
3500  * convenience and illustrative purposes. They should, however, be used with
3501  * caution as the C language standard provides no guarantees about the alignment or
3502  * atomicity of device memory accesses. The recommended practice for writing
3503  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3504  * alt_write_word() functions.
3505  *
3506  * The struct declaration for register ALT_L3_ID_PERIPH_ID_0.
3507  */
3509 {
3510  const uint32_t pn7to0 : 8; /* Part Number [7:0] */
3511  uint32_t : 24; /* *UNDEFINED* */
3512 };
3513 
3514 /* The typedef declaration for register ALT_L3_ID_PERIPH_ID_0. */
3515 typedef volatile struct ALT_L3_ID_PERIPH_ID_0_s ALT_L3_ID_PERIPH_ID_0_t;
3516 #endif /* __ASSEMBLY__ */
3517 
3518 /* The byte offset of the ALT_L3_ID_PERIPH_ID_0 register from the beginning of the component. */
3519 #define ALT_L3_ID_PERIPH_ID_0_OFST 0xfe0
3520 
3521 /*
3522  * Register : Peripheral ID1 Register - periph_id_1
3523  *
3524  * Peripheral ID1
3525  *
3526  * Register Layout
3527  *
3528  * Bits | Access | Reset | Description
3529  * :-------|:-------|:------|:--------------------------------
3530  * [7:0] | R | 0xb3 | JEP106[3:0], Part Number [11:8]
3531  * [31:8] | ??? | 0x0 | *UNDEFINED*
3532  *
3533  */
3534 /*
3535  * Field : JEP106[3:0], Part Number [11:8] - jep3to0_pn11to8
3536  *
3537  * JEP106[3:0], Part Number [11:8]
3538  *
3539  * Field Access Macros:
3540  *
3541  */
3542 /* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */
3543 #define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_LSB 0
3544 /* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */
3545 #define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_MSB 7
3546 /* The width in bits of the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */
3547 #define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_WIDTH 8
3548 /* The mask used to set the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value. */
3549 #define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_SET_MSK 0x000000ff
3550 /* The mask used to clear the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value. */
3551 #define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_CLR_MSK 0xffffff00
3552 /* The reset value of the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */
3553 #define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_RESET 0xb3
3554 /* Extracts the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 field value from a register. */
3555 #define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_GET(value) (((value) & 0x000000ff) >> 0)
3556 /* Produces a ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value suitable for setting the register. */
3557 #define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_SET(value) (((value) << 0) & 0x000000ff)
3558 
3559 #ifndef __ASSEMBLY__
3560 /*
3561  * WARNING: The C register and register group struct declarations are provided for
3562  * convenience and illustrative purposes. They should, however, be used with
3563  * caution as the C language standard provides no guarantees about the alignment or
3564  * atomicity of device memory accesses. The recommended practice for writing
3565  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3566  * alt_write_word() functions.
3567  *
3568  * The struct declaration for register ALT_L3_ID_PERIPH_ID_1.
3569  */
3571 {
3572  const uint32_t jep3to0_pn11to8 : 8; /* JEP106[3:0], Part Number [11:8] */
3573  uint32_t : 24; /* *UNDEFINED* */
3574 };
3575 
3576 /* The typedef declaration for register ALT_L3_ID_PERIPH_ID_1. */
3577 typedef volatile struct ALT_L3_ID_PERIPH_ID_1_s ALT_L3_ID_PERIPH_ID_1_t;
3578 #endif /* __ASSEMBLY__ */
3579 
3580 /* The byte offset of the ALT_L3_ID_PERIPH_ID_1 register from the beginning of the component. */
3581 #define ALT_L3_ID_PERIPH_ID_1_OFST 0xfe4
3582 
3583 /*
3584  * Register : Peripheral ID2 Register - periph_id_2
3585  *
3586  * Peripheral ID2
3587  *
3588  * Register Layout
3589  *
3590  * Bits | Access | Reset | Description
3591  * :-------|:-------|:------|:----------------------------------------
3592  * [7:0] | R | 0x6b | Revision, JEP106 code flag, JEP106[6:4]
3593  * [31:8] | ??? | 0x0 | *UNDEFINED*
3594  *
3595  */
3596 /*
3597  * Field : Revision, JEP106 code flag, JEP106[6:4] - rev_jepcode_jep6to4
3598  *
3599  * Revision, JEP106 code flag, JEP106[6:4]
3600  *
3601  * Field Access Macros:
3602  *
3603  */
3604 /* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */
3605 #define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_LSB 0
3606 /* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */
3607 #define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_MSB 7
3608 /* The width in bits of the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */
3609 #define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_WIDTH 8
3610 /* The mask used to set the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value. */
3611 #define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_SET_MSK 0x000000ff
3612 /* The mask used to clear the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value. */
3613 #define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_CLR_MSK 0xffffff00
3614 /* The reset value of the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */
3615 #define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_RESET 0x6b
3616 /* Extracts the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 field value from a register. */
3617 #define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_GET(value) (((value) & 0x000000ff) >> 0)
3618 /* Produces a ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value suitable for setting the register. */
3619 #define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_SET(value) (((value) << 0) & 0x000000ff)
3620 
3621 #ifndef __ASSEMBLY__
3622 /*
3623  * WARNING: The C register and register group struct declarations are provided for
3624  * convenience and illustrative purposes. They should, however, be used with
3625  * caution as the C language standard provides no guarantees about the alignment or
3626  * atomicity of device memory accesses. The recommended practice for writing
3627  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3628  * alt_write_word() functions.
3629  *
3630  * The struct declaration for register ALT_L3_ID_PERIPH_ID_2.
3631  */
3633 {
3634  const uint32_t rev_jepcode_jep6to4 : 8; /* Revision, JEP106 code flag, JEP106[6:4] */
3635  uint32_t : 24; /* *UNDEFINED* */
3636 };
3637 
3638 /* The typedef declaration for register ALT_L3_ID_PERIPH_ID_2. */
3639 typedef volatile struct ALT_L3_ID_PERIPH_ID_2_s ALT_L3_ID_PERIPH_ID_2_t;
3640 #endif /* __ASSEMBLY__ */
3641 
3642 /* The byte offset of the ALT_L3_ID_PERIPH_ID_2 register from the beginning of the component. */
3643 #define ALT_L3_ID_PERIPH_ID_2_OFST 0xfe8
3644 
3645 /*
3646  * Register : Peripheral ID3 Register - periph_id_3
3647  *
3648  * Peripheral ID3
3649  *
3650  * Register Layout
3651  *
3652  * Bits | Access | Reset | Description
3653  * :-------|:-------|:------|:----------------------
3654  * [3:0] | R | 0x0 | Customer Model Number
3655  * [7:4] | R | 0x0 | Revision
3656  * [31:8] | ??? | 0x0 | *UNDEFINED*
3657  *
3658  */
3659 /*
3660  * Field : Customer Model Number - cust_mod_num
3661  *
3662  * Customer Model Number
3663  *
3664  * Field Access Macros:
3665  *
3666  */
3667 /* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */
3668 #define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_LSB 0
3669 /* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */
3670 #define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_MSB 3
3671 /* The width in bits of the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */
3672 #define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_WIDTH 4
3673 /* The mask used to set the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field value. */
3674 #define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_SET_MSK 0x0000000f
3675 /* The mask used to clear the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field value. */
3676 #define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_CLR_MSK 0xfffffff0
3677 /* The reset value of the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */
3678 #define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_RESET 0x0
3679 /* Extracts the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM field value from a register. */
3680 #define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_GET(value) (((value) & 0x0000000f) >> 0)
3681 /* Produces a ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field value suitable for setting the register. */
3682 #define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_SET(value) (((value) << 0) & 0x0000000f)
3683 
3684 /*
3685  * Field : Revision - rev_and
3686  *
3687  * Revision
3688  *
3689  * Field Access Macros:
3690  *
3691  */
3692 /* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_3_REV_AND register field. */
3693 #define ALT_L3_ID_PERIPH_ID_3_REV_AND_LSB 4
3694 /* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_3_REV_AND register field. */
3695 #define ALT_L3_ID_PERIPH_ID_3_REV_AND_MSB 7
3696 /* The width in bits of the ALT_L3_ID_PERIPH_ID_3_REV_AND register field. */
3697 #define ALT_L3_ID_PERIPH_ID_3_REV_AND_WIDTH 4
3698 /* The mask used to set the ALT_L3_ID_PERIPH_ID_3_REV_AND register field value. */
3699 #define ALT_L3_ID_PERIPH_ID_3_REV_AND_SET_MSK 0x000000f0
3700 /* The mask used to clear the ALT_L3_ID_PERIPH_ID_3_REV_AND register field value. */
3701 #define ALT_L3_ID_PERIPH_ID_3_REV_AND_CLR_MSK 0xffffff0f
3702 /* The reset value of the ALT_L3_ID_PERIPH_ID_3_REV_AND register field. */
3703 #define ALT_L3_ID_PERIPH_ID_3_REV_AND_RESET 0x0
3704 /* Extracts the ALT_L3_ID_PERIPH_ID_3_REV_AND field value from a register. */
3705 #define ALT_L3_ID_PERIPH_ID_3_REV_AND_GET(value) (((value) & 0x000000f0) >> 4)
3706 /* Produces a ALT_L3_ID_PERIPH_ID_3_REV_AND register field value suitable for setting the register. */
3707 #define ALT_L3_ID_PERIPH_ID_3_REV_AND_SET(value) (((value) << 4) & 0x000000f0)
3708 
3709 #ifndef __ASSEMBLY__
3710 /*
3711  * WARNING: The C register and register group struct declarations are provided for
3712  * convenience and illustrative purposes. They should, however, be used with
3713  * caution as the C language standard provides no guarantees about the alignment or
3714  * atomicity of device memory accesses. The recommended practice for writing
3715  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3716  * alt_write_word() functions.
3717  *
3718  * The struct declaration for register ALT_L3_ID_PERIPH_ID_3.
3719  */
3721 {
3722  const uint32_t cust_mod_num : 4; /* Customer Model Number */
3723  const uint32_t rev_and : 4; /* Revision */
3724  uint32_t : 24; /* *UNDEFINED* */
3725 };
3726 
3727 /* The typedef declaration for register ALT_L3_ID_PERIPH_ID_3. */
3728 typedef volatile struct ALT_L3_ID_PERIPH_ID_3_s ALT_L3_ID_PERIPH_ID_3_t;
3729 #endif /* __ASSEMBLY__ */
3730 
3731 /* The byte offset of the ALT_L3_ID_PERIPH_ID_3 register from the beginning of the component. */
3732 #define ALT_L3_ID_PERIPH_ID_3_OFST 0xfec
3733 
3734 /*
3735  * Register : Component ID0 Register - comp_id_0
3736  *
3737  * Component ID0
3738  *
3739  * Register Layout
3740  *
3741  * Bits | Access | Reset | Description
3742  * :-------|:-------|:------|:------------
3743  * [7:0] | R | 0xd | Preamble
3744  * [31:8] | ??? | 0x0 | *UNDEFINED*
3745  *
3746  */
3747 /*
3748  * Field : Preamble - preamble
3749  *
3750  * Preamble
3751  *
3752  * Field Access Macros:
3753  *
3754  */
3755 /* The Least Significant Bit (LSB) position of the ALT_L3_ID_COMP_ID_0_PREAMBLE register field. */
3756 #define ALT_L3_ID_COMP_ID_0_PREAMBLE_LSB 0
3757 /* The Most Significant Bit (MSB) position of the ALT_L3_ID_COMP_ID_0_PREAMBLE register field. */
3758 #define ALT_L3_ID_COMP_ID_0_PREAMBLE_MSB 7
3759 /* The width in bits of the ALT_L3_ID_COMP_ID_0_PREAMBLE register field. */
3760 #define ALT_L3_ID_COMP_ID_0_PREAMBLE_WIDTH 8
3761 /* The mask used to set the ALT_L3_ID_COMP_ID_0_PREAMBLE register field value. */
3762 #define ALT_L3_ID_COMP_ID_0_PREAMBLE_SET_MSK 0x000000ff
3763 /* The mask used to clear the ALT_L3_ID_COMP_ID_0_PREAMBLE register field value. */
3764 #define ALT_L3_ID_COMP_ID_0_PREAMBLE_CLR_MSK 0xffffff00
3765 /* The reset value of the ALT_L3_ID_COMP_ID_0_PREAMBLE register field. */
3766 #define ALT_L3_ID_COMP_ID_0_PREAMBLE_RESET 0xd
3767 /* Extracts the ALT_L3_ID_COMP_ID_0_PREAMBLE field value from a register. */
3768 #define ALT_L3_ID_COMP_ID_0_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0)
3769 /* Produces a ALT_L3_ID_COMP_ID_0_PREAMBLE register field value suitable for setting the register. */
3770 #define ALT_L3_ID_COMP_ID_0_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff)
3771 
3772 #ifndef __ASSEMBLY__
3773 /*
3774  * WARNING: The C register and register group struct declarations are provided for
3775  * convenience and illustrative purposes. They should, however, be used with
3776  * caution as the C language standard provides no guarantees about the alignment or
3777  * atomicity of device memory accesses. The recommended practice for writing
3778  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3779  * alt_write_word() functions.
3780  *
3781  * The struct declaration for register ALT_L3_ID_COMP_ID_0.
3782  */
3784 {
3785  const uint32_t preamble : 8; /* Preamble */
3786  uint32_t : 24; /* *UNDEFINED* */
3787 };
3788 
3789 /* The typedef declaration for register ALT_L3_ID_COMP_ID_0. */
3790 typedef volatile struct ALT_L3_ID_COMP_ID_0_s ALT_L3_ID_COMP_ID_0_t;
3791 #endif /* __ASSEMBLY__ */
3792 
3793 /* The byte offset of the ALT_L3_ID_COMP_ID_0 register from the beginning of the component. */
3794 #define ALT_L3_ID_COMP_ID_0_OFST 0xff0
3795 
3796 /*
3797  * Register : Component ID1 Register - comp_id_1
3798  *
3799  * Component ID1
3800  *
3801  * Register Layout
3802  *
3803  * Bits | Access | Reset | Description
3804  * :-------|:-------|:------|:-------------------------------------
3805  * [7:0] | R | 0xf0 | Generic IP component class, Preamble
3806  * [31:8] | ??? | 0x0 | *UNDEFINED*
3807  *
3808  */
3809 /*
3810  * Field : Generic IP component class, Preamble - genipcompcls_preamble
3811  *
3812  * Generic IP component class, Preamble
3813  *
3814  * Field Access Macros:
3815  *
3816  */
3817 /* The Least Significant Bit (LSB) position of the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */
3818 #define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_LSB 0
3819 /* The Most Significant Bit (MSB) position of the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */
3820 #define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_MSB 7
3821 /* The width in bits of the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */
3822 #define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_WIDTH 8
3823 /* The mask used to set the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value. */
3824 #define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_SET_MSK 0x000000ff
3825 /* The mask used to clear the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value. */
3826 #define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_CLR_MSK 0xffffff00
3827 /* The reset value of the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */
3828 #define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_RESET 0xf0
3829 /* Extracts the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE field value from a register. */
3830 #define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0)
3831 /* Produces a ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value suitable for setting the register. */
3832 #define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff)
3833 
3834 #ifndef __ASSEMBLY__
3835 /*
3836  * WARNING: The C register and register group struct declarations are provided for
3837  * convenience and illustrative purposes. They should, however, be used with
3838  * caution as the C language standard provides no guarantees about the alignment or
3839  * atomicity of device memory accesses. The recommended practice for writing
3840  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3841  * alt_write_word() functions.
3842  *
3843  * The struct declaration for register ALT_L3_ID_COMP_ID_1.
3844  */
3846 {
3847  const uint32_t genipcompcls_preamble : 8; /* Generic IP component class, Preamble */
3848  uint32_t : 24; /* *UNDEFINED* */
3849 };
3850 
3851 /* The typedef declaration for register ALT_L3_ID_COMP_ID_1. */
3852 typedef volatile struct ALT_L3_ID_COMP_ID_1_s ALT_L3_ID_COMP_ID_1_t;
3853 #endif /* __ASSEMBLY__ */
3854 
3855 /* The byte offset of the ALT_L3_ID_COMP_ID_1 register from the beginning of the component. */
3856 #define ALT_L3_ID_COMP_ID_1_OFST 0xff4
3857 
3858 /*
3859  * Register : Component ID2 Register - comp_id_2
3860  *
3861  * Component ID2
3862  *
3863  * Register Layout
3864  *
3865  * Bits | Access | Reset | Description
3866  * :-------|:-------|:------|:------------
3867  * [7:0] | R | 0x5 | Preamble
3868  * [31:8] | ??? | 0x0 | *UNDEFINED*
3869  *
3870  */
3871 /*
3872  * Field : Preamble - preamble
3873  *
3874  * Preamble
3875  *
3876  * Field Access Macros:
3877  *
3878  */
3879 /* The Least Significant Bit (LSB) position of the ALT_L3_ID_COMP_ID_2_PREAMBLE register field. */
3880 #define ALT_L3_ID_COMP_ID_2_PREAMBLE_LSB 0
3881 /* The Most Significant Bit (MSB) position of the ALT_L3_ID_COMP_ID_2_PREAMBLE register field. */
3882 #define ALT_L3_ID_COMP_ID_2_PREAMBLE_MSB 7
3883 /* The width in bits of the ALT_L3_ID_COMP_ID_2_PREAMBLE register field. */
3884 #define ALT_L3_ID_COMP_ID_2_PREAMBLE_WIDTH 8
3885 /* The mask used to set the ALT_L3_ID_COMP_ID_2_PREAMBLE register field value. */
3886 #define ALT_L3_ID_COMP_ID_2_PREAMBLE_SET_MSK 0x000000ff
3887 /* The mask used to clear the ALT_L3_ID_COMP_ID_2_PREAMBLE register field value. */
3888 #define ALT_L3_ID_COMP_ID_2_PREAMBLE_CLR_MSK 0xffffff00
3889 /* The reset value of the ALT_L3_ID_COMP_ID_2_PREAMBLE register field. */
3890 #define ALT_L3_ID_COMP_ID_2_PREAMBLE_RESET 0x5
3891 /* Extracts the ALT_L3_ID_COMP_ID_2_PREAMBLE field value from a register. */
3892 #define ALT_L3_ID_COMP_ID_2_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0)
3893 /* Produces a ALT_L3_ID_COMP_ID_2_PREAMBLE register field value suitable for setting the register. */
3894 #define ALT_L3_ID_COMP_ID_2_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff)
3895 
3896 #ifndef __ASSEMBLY__
3897 /*
3898  * WARNING: The C register and register group struct declarations are provided for
3899  * convenience and illustrative purposes. They should, however, be used with
3900  * caution as the C language standard provides no guarantees about the alignment or
3901  * atomicity of device memory accesses. The recommended practice for writing
3902  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3903  * alt_write_word() functions.
3904  *
3905  * The struct declaration for register ALT_L3_ID_COMP_ID_2.
3906  */
3908 {
3909  const uint32_t preamble : 8; /* Preamble */
3910  uint32_t : 24; /* *UNDEFINED* */
3911 };
3912 
3913 /* The typedef declaration for register ALT_L3_ID_COMP_ID_2. */
3914 typedef volatile struct ALT_L3_ID_COMP_ID_2_s ALT_L3_ID_COMP_ID_2_t;
3915 #endif /* __ASSEMBLY__ */
3916 
3917 /* The byte offset of the ALT_L3_ID_COMP_ID_2 register from the beginning of the component. */
3918 #define ALT_L3_ID_COMP_ID_2_OFST 0xff8
3919 
3920 /*
3921  * Register : Component ID3 Register - comp_id_3
3922  *
3923  * Component ID3
3924  *
3925  * Register Layout
3926  *
3927  * Bits | Access | Reset | Description
3928  * :-------|:-------|:------|:------------
3929  * [7:0] | R | 0xb1 | Preamble
3930  * [31:8] | ??? | 0x0 | *UNDEFINED*
3931  *
3932  */
3933 /*
3934  * Field : Preamble - preamble
3935  *
3936  * Preamble
3937  *
3938  * Field Access Macros:
3939  *
3940  */
3941 /* The Least Significant Bit (LSB) position of the ALT_L3_ID_COMP_ID_3_PREAMBLE register field. */
3942 #define ALT_L3_ID_COMP_ID_3_PREAMBLE_LSB 0
3943 /* The Most Significant Bit (MSB) position of the ALT_L3_ID_COMP_ID_3_PREAMBLE register field. */
3944 #define ALT_L3_ID_COMP_ID_3_PREAMBLE_MSB 7
3945 /* The width in bits of the ALT_L3_ID_COMP_ID_3_PREAMBLE register field. */
3946 #define ALT_L3_ID_COMP_ID_3_PREAMBLE_WIDTH 8
3947 /* The mask used to set the ALT_L3_ID_COMP_ID_3_PREAMBLE register field value. */
3948 #define ALT_L3_ID_COMP_ID_3_PREAMBLE_SET_MSK 0x000000ff
3949 /* The mask used to clear the ALT_L3_ID_COMP_ID_3_PREAMBLE register field value. */
3950 #define ALT_L3_ID_COMP_ID_3_PREAMBLE_CLR_MSK 0xffffff00
3951 /* The reset value of the ALT_L3_ID_COMP_ID_3_PREAMBLE register field. */
3952 #define ALT_L3_ID_COMP_ID_3_PREAMBLE_RESET 0xb1
3953 /* Extracts the ALT_L3_ID_COMP_ID_3_PREAMBLE field value from a register. */
3954 #define ALT_L3_ID_COMP_ID_3_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0)
3955 /* Produces a ALT_L3_ID_COMP_ID_3_PREAMBLE register field value suitable for setting the register. */
3956 #define ALT_L3_ID_COMP_ID_3_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff)
3957 
3958 #ifndef __ASSEMBLY__
3959 /*
3960  * WARNING: The C register and register group struct declarations are provided for
3961  * convenience and illustrative purposes. They should, however, be used with
3962  * caution as the C language standard provides no guarantees about the alignment or
3963  * atomicity of device memory accesses. The recommended practice for writing
3964  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3965  * alt_write_word() functions.
3966  *
3967  * The struct declaration for register ALT_L3_ID_COMP_ID_3.
3968  */
3970 {
3971  const uint32_t preamble : 8; /* Preamble */
3972  uint32_t : 24; /* *UNDEFINED* */
3973 };
3974 
3975 /* The typedef declaration for register ALT_L3_ID_COMP_ID_3. */
3976 typedef volatile struct ALT_L3_ID_COMP_ID_3_s ALT_L3_ID_COMP_ID_3_t;
3977 #endif /* __ASSEMBLY__ */
3978 
3979 /* The byte offset of the ALT_L3_ID_COMP_ID_3 register from the beginning of the component. */
3980 #define ALT_L3_ID_COMP_ID_3_OFST 0xffc
3981 
3982 #ifndef __ASSEMBLY__
3983 /*
3984  * WARNING: The C register and register group struct declarations are provided for
3985  * convenience and illustrative purposes. They should, however, be used with
3986  * caution as the C language standard provides no guarantees about the alignment or
3987  * atomicity of device memory accesses. The recommended practice for writing
3988  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3989  * alt_write_word() functions.
3990  *
3991  * The struct declaration for register group ALT_L3_IDGRP.
3992  */
3994 {
3995  volatile uint32_t _pad_0x0_0xfcf[1012]; /* *UNDEFINED* */
3996  volatile ALT_L3_ID_PERIPH_ID_4_t periph_id_4; /* ALT_L3_ID_PERIPH_ID_4 */
3997  volatile uint32_t _pad_0xfd4_0xfdf[3]; /* *UNDEFINED* */
3998  volatile ALT_L3_ID_PERIPH_ID_0_t periph_id_0; /* ALT_L3_ID_PERIPH_ID_0 */
3999  volatile ALT_L3_ID_PERIPH_ID_1_t periph_id_1; /* ALT_L3_ID_PERIPH_ID_1 */
4000  volatile ALT_L3_ID_PERIPH_ID_2_t periph_id_2; /* ALT_L3_ID_PERIPH_ID_2 */
4001  volatile ALT_L3_ID_PERIPH_ID_3_t periph_id_3; /* ALT_L3_ID_PERIPH_ID_3 */
4002  volatile ALT_L3_ID_COMP_ID_0_t comp_id_0; /* ALT_L3_ID_COMP_ID_0 */
4003  volatile ALT_L3_ID_COMP_ID_1_t comp_id_1; /* ALT_L3_ID_COMP_ID_1 */
4004  volatile ALT_L3_ID_COMP_ID_2_t comp_id_2; /* ALT_L3_ID_COMP_ID_2 */
4005  volatile ALT_L3_ID_COMP_ID_3_t comp_id_3; /* ALT_L3_ID_COMP_ID_3 */
4006 };
4007 
4008 /* The typedef declaration for register group ALT_L3_IDGRP. */
4009 typedef volatile struct ALT_L3_IDGRP_s ALT_L3_IDGRP_t;
4010 /* The struct declaration for the raw register contents of register group ALT_L3_IDGRP. */
4012 {
4013  volatile uint32_t _pad_0x0_0xfcf[1012]; /* *UNDEFINED* */
4014  volatile uint32_t periph_id_4; /* ALT_L3_ID_PERIPH_ID_4 */
4015  volatile uint32_t _pad_0xfd4_0xfdf[3]; /* *UNDEFINED* */
4016  volatile uint32_t periph_id_0; /* ALT_L3_ID_PERIPH_ID_0 */
4017  volatile uint32_t periph_id_1; /* ALT_L3_ID_PERIPH_ID_1 */
4018  volatile uint32_t periph_id_2; /* ALT_L3_ID_PERIPH_ID_2 */
4019  volatile uint32_t periph_id_3; /* ALT_L3_ID_PERIPH_ID_3 */
4020  volatile uint32_t comp_id_0; /* ALT_L3_ID_COMP_ID_0 */
4021  volatile uint32_t comp_id_1; /* ALT_L3_ID_COMP_ID_1 */
4022  volatile uint32_t comp_id_2; /* ALT_L3_ID_COMP_ID_2 */
4023  volatile uint32_t comp_id_3; /* ALT_L3_ID_COMP_ID_3 */
4024 };
4025 
4026 /* The typedef declaration for the raw register contents of register group ALT_L3_IDGRP. */
4027 typedef volatile struct ALT_L3_IDGRP_raw_s ALT_L3_IDGRP_raw_t;
4028 #endif /* __ASSEMBLY__ */
4029 
4030 
4031 /*
4032  * Register Group : Master Register Group - ALT_L3_MSTGRP
4033  * Master Register Group
4034  *
4035  * Registers associated with master interfaces in the L3 Interconnect. Note that a
4036  * master in the L3 Interconnect connects to a slave in a module.
4037  *
4038  */
4039 /*
4040  * Register Group : L4 MAIN - ALT_L3_MST_L4MAIN
4041  * L4 MAIN
4042  *
4043  * Registers associated with the L4 MAIN master. This master is used to access the
4044  * APB slaves on the L4 MAIN bus.
4045  *
4046  */
4047 /*
4048  * Register : Bus Matrix Issuing Functionality Modification Register - fn_mod_bm_iss
4049  *
4050  * Sets the issuing capability of the preceding switch arbitration scheme to
4051  * multiple or single outstanding transactions.
4052  *
4053  * Register Layout
4054  *
4055  * Bits | Access | Reset | Description
4056  * :-------|:-------|:------|:------------------------
4057  * [0] | RW | 0x0 | ALT_L3_FN_MOD_BM_ISS_RD
4058  * [1] | RW | 0x0 | ALT_L3_FN_MOD_BM_ISS_WR
4059  * [31:2] | ??? | 0x0 | *UNDEFINED*
4060  *
4061  */
4062 /*
4063  * Field : rd
4064  *
4065  * Field Enumeration Values:
4066  *
4067  * Enum | Value | Description
4068  * :---------------------------------|:------|:-------------------------------------------
4069  * ALT_L3_FN_MOD_BM_ISS_RD_E_MULT | 0x0 | Multiple outstanding read transactions
4070  * ALT_L3_FN_MOD_BM_ISS_RD_E_SINGLE | 0x1 | Only a single outstanding read transaction
4071  *
4072  * Field Access Macros:
4073  *
4074  */
4075 /*
4076  * Enumerated value for register field ALT_L3_FN_MOD_BM_ISS_RD
4077  *
4078  * Multiple outstanding read transactions
4079  */
4080 #define ALT_L3_FN_MOD_BM_ISS_RD_E_MULT 0x0
4081 /*
4082  * Enumerated value for register field ALT_L3_FN_MOD_BM_ISS_RD
4083  *
4084  * Only a single outstanding read transaction
4085  */
4086 #define ALT_L3_FN_MOD_BM_ISS_RD_E_SINGLE 0x1
4087 
4088 /* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_BM_ISS_RD register field. */
4089 #define ALT_L3_FN_MOD_BM_ISS_RD_LSB 0
4090 /* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_BM_ISS_RD register field. */
4091 #define ALT_L3_FN_MOD_BM_ISS_RD_MSB 0
4092 /* The width in bits of the ALT_L3_FN_MOD_BM_ISS_RD register field. */
4093 #define ALT_L3_FN_MOD_BM_ISS_RD_WIDTH 1
4094 /* The mask used to set the ALT_L3_FN_MOD_BM_ISS_RD register field value. */
4095 #define ALT_L3_FN_MOD_BM_ISS_RD_SET_MSK 0x00000001
4096 /* The mask used to clear the ALT_L3_FN_MOD_BM_ISS_RD register field value. */
4097 #define ALT_L3_FN_MOD_BM_ISS_RD_CLR_MSK 0xfffffffe
4098 /* The reset value of the ALT_L3_FN_MOD_BM_ISS_RD register field. */
4099 #define ALT_L3_FN_MOD_BM_ISS_RD_RESET 0x0
4100 /* Extracts the ALT_L3_FN_MOD_BM_ISS_RD field value from a register. */
4101 #define ALT_L3_FN_MOD_BM_ISS_RD_GET(value) (((value) & 0x00000001) >> 0)
4102 /* Produces a ALT_L3_FN_MOD_BM_ISS_RD register field value suitable for setting the register. */
4103 #define ALT_L3_FN_MOD_BM_ISS_RD_SET(value) (((value) << 0) & 0x00000001)
4104 
4105 /*
4106  * Field : wr
4107  *
4108  * Field Enumeration Values:
4109  *
4110  * Enum | Value | Description
4111  * :---------------------------------|:------|:--------------------------------------------
4112  * ALT_L3_FN_MOD_BM_ISS_WR_E_MULT | 0x0 | Multiple outstanding write transactions
4113  * ALT_L3_FN_MOD_BM_ISS_WR_E_SINGLE | 0x1 | Only a single outstanding write transaction
4114  *
4115  * Field Access Macros:
4116  *
4117  */
4118 /*
4119  * Enumerated value for register field ALT_L3_FN_MOD_BM_ISS_WR
4120  *
4121  * Multiple outstanding write transactions
4122  */
4123 #define ALT_L3_FN_MOD_BM_ISS_WR_E_MULT 0x0
4124 /*
4125  * Enumerated value for register field ALT_L3_FN_MOD_BM_ISS_WR
4126  *
4127  * Only a single outstanding write transaction
4128  */
4129 #define ALT_L3_FN_MOD_BM_ISS_WR_E_SINGLE 0x1
4130 
4131 /* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_BM_ISS_WR register field. */
4132 #define ALT_L3_FN_MOD_BM_ISS_WR_LSB 1
4133 /* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_BM_ISS_WR register field. */
4134 #define ALT_L3_FN_MOD_BM_ISS_WR_MSB 1
4135 /* The width in bits of the ALT_L3_FN_MOD_BM_ISS_WR register field. */
4136 #define ALT_L3_FN_MOD_BM_ISS_WR_WIDTH 1
4137 /* The mask used to set the ALT_L3_FN_MOD_BM_ISS_WR register field value. */
4138 #define ALT_L3_FN_MOD_BM_ISS_WR_SET_MSK 0x00000002
4139 /* The mask used to clear the ALT_L3_FN_MOD_BM_ISS_WR register field value. */
4140 #define ALT_L3_FN_MOD_BM_ISS_WR_CLR_MSK 0xfffffffd
4141 /* The reset value of the ALT_L3_FN_MOD_BM_ISS_WR register field. */
4142 #define ALT_L3_FN_MOD_BM_ISS_WR_RESET 0x0
4143 /* Extracts the ALT_L3_FN_MOD_BM_ISS_WR field value from a register. */
4144 #define ALT_L3_FN_MOD_BM_ISS_WR_GET(value) (((value) & 0x00000002) >> 1)
4145 /* Produces a ALT_L3_FN_MOD_BM_ISS_WR register field value suitable for setting the register. */
4146 #define ALT_L3_FN_MOD_BM_ISS_WR_SET(value) (((value) << 1) & 0x00000002)
4147 
4148 #ifndef __ASSEMBLY__
4149 /*
4150  * WARNING: The C register and register group struct declarations are provided for
4151  * convenience and illustrative purposes. They should, however, be used with
4152  * caution as the C language standard provides no guarantees about the alignment or
4153  * atomicity of device memory accesses. The recommended practice for writing
4154  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4155  * alt_write_word() functions.
4156  *
4157  * The struct declaration for register ALT_L3_FN_MOD_BM_ISS.
4158  */
4160 {
4161  uint32_t rd : 1; /* ALT_L3_FN_MOD_BM_ISS_RD */
4162  uint32_t wr : 1; /* ALT_L3_FN_MOD_BM_ISS_WR */
4163  uint32_t : 30; /* *UNDEFINED* */
4164 };
4165 
4166 /* The typedef declaration for register ALT_L3_FN_MOD_BM_ISS. */
4167 typedef volatile struct ALT_L3_FN_MOD_BM_ISS_s ALT_L3_FN_MOD_BM_ISS_t;
4168 #endif /* __ASSEMBLY__ */
4169 
4170 /* The byte offset of the ALT_L3_FN_MOD_BM_ISS register from the beginning of the component. */
4171 #define ALT_L3_FN_MOD_BM_ISS_OFST 0x8
4172 /* The address of the ALT_L3_FN_MOD_BM_ISS register. */
4173 #define ALT_L3_FN_MOD_BM_ISS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_FN_MOD_BM_ISS_OFST))
4174 
4175 #ifndef __ASSEMBLY__
4176 /*
4177  * WARNING: The C register and register group struct declarations are provided for
4178  * convenience and illustrative purposes. They should, however, be used with
4179  * caution as the C language standard provides no guarantees about the alignment or
4180  * atomicity of device memory accesses. The recommended practice for writing
4181  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4182  * alt_write_word() functions.
4183  *
4184  * The struct declaration for register group ALT_L3_MST_L4MAIN.
4185  */
4187 {
4188  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4189  volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4190 };
4191 
4192 /* The typedef declaration for register group ALT_L3_MST_L4MAIN. */
4193 typedef volatile struct ALT_L3_MST_L4MAIN_s ALT_L3_MST_L4MAIN_t;
4194 /* The struct declaration for the raw register contents of register group ALT_L3_MST_L4MAIN. */
4196 {
4197  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4198  volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4199 };
4200 
4201 /* The typedef declaration for the raw register contents of register group ALT_L3_MST_L4MAIN. */
4202 typedef volatile struct ALT_L3_MST_L4MAIN_raw_s ALT_L3_MST_L4MAIN_raw_t;
4203 #endif /* __ASSEMBLY__ */
4204 
4205 
4206 /*
4207  * Register Group : L4 SP - ALT_L3_MST_L4SP
4208  * L4 SP
4209  *
4210  * Registers associated with the L4 SP master. This master is used to access the
4211  * APB slaves on the L4 SP bus.
4212  *
4213  */
4214 #ifndef __ASSEMBLY__
4215 /*
4216  * WARNING: The C register and register group struct declarations are provided for
4217  * convenience and illustrative purposes. They should, however, be used with
4218  * caution as the C language standard provides no guarantees about the alignment or
4219  * atomicity of device memory accesses. The recommended practice for writing
4220  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4221  * alt_write_word() functions.
4222  *
4223  * The struct declaration for register group ALT_L3_MST_L4SP.
4224  */
4226 {
4227  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4228  volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4229 };
4230 
4231 /* The typedef declaration for register group ALT_L3_MST_L4SP. */
4232 typedef volatile struct ALT_L3_MST_L4SP_s ALT_L3_MST_L4SP_t;
4233 /* The struct declaration for the raw register contents of register group ALT_L3_MST_L4SP. */
4235 {
4236  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4237  volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4238 };
4239 
4240 /* The typedef declaration for the raw register contents of register group ALT_L3_MST_L4SP. */
4241 typedef volatile struct ALT_L3_MST_L4SP_raw_s ALT_L3_MST_L4SP_raw_t;
4242 #endif /* __ASSEMBLY__ */
4243 
4244 
4245 /*
4246  * Register Group : L4 MP - ALT_L3_MST_L4MP
4247  * L4 MP
4248  *
4249  * Registers associated with the L4 MP master. This master is used to access the
4250  * APB slaves on the L4 MP bus.
4251  *
4252  */
4253 #ifndef __ASSEMBLY__
4254 /*
4255  * WARNING: The C register and register group struct declarations are provided for
4256  * convenience and illustrative purposes. They should, however, be used with
4257  * caution as the C language standard provides no guarantees about the alignment or
4258  * atomicity of device memory accesses. The recommended practice for writing
4259  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4260  * alt_write_word() functions.
4261  *
4262  * The struct declaration for register group ALT_L3_MST_L4MP.
4263  */
4265 {
4266  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4267  volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4268 };
4269 
4270 /* The typedef declaration for register group ALT_L3_MST_L4MP. */
4271 typedef volatile struct ALT_L3_MST_L4MP_s ALT_L3_MST_L4MP_t;
4272 /* The struct declaration for the raw register contents of register group ALT_L3_MST_L4MP. */
4274 {
4275  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4276  volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4277 };
4278 
4279 /* The typedef declaration for the raw register contents of register group ALT_L3_MST_L4MP. */
4280 typedef volatile struct ALT_L3_MST_L4MP_raw_s ALT_L3_MST_L4MP_raw_t;
4281 #endif /* __ASSEMBLY__ */
4282 
4283 
4284 /*
4285  * Register Group : L4 OSC1 - ALT_L3_MST_L4OSC1
4286  * L4 OSC1
4287  *
4288  * Registers associated with the L4 OSC1 master. This master is used to access the
4289  * APB slaves on the L4 OSC1 bus.
4290  *
4291  */
4292 #ifndef __ASSEMBLY__
4293 /*
4294  * WARNING: The C register and register group struct declarations are provided for
4295  * convenience and illustrative purposes. They should, however, be used with
4296  * caution as the C language standard provides no guarantees about the alignment or
4297  * atomicity of device memory accesses. The recommended practice for writing
4298  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4299  * alt_write_word() functions.
4300  *
4301  * The struct declaration for register group ALT_L3_MST_L4OSC1.
4302  */
4304 {
4305  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4306  volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4307 };
4308 
4309 /* The typedef declaration for register group ALT_L3_MST_L4OSC1. */
4310 typedef volatile struct ALT_L3_MST_L4OSC1_s ALT_L3_MST_L4OSC1_t;
4311 /* The struct declaration for the raw register contents of register group ALT_L3_MST_L4OSC1. */
4313 {
4314  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4315  volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4316 };
4317 
4318 /* The typedef declaration for the raw register contents of register group ALT_L3_MST_L4OSC1. */
4319 typedef volatile struct ALT_L3_MST_L4OSC1_raw_s ALT_L3_MST_L4OSC1_raw_t;
4320 #endif /* __ASSEMBLY__ */
4321 
4322 
4323 /*
4324  * Register Group : L4 SPIM - ALT_L3_MST_L4SPIM
4325  * L4 SPIM
4326  *
4327  * Registers associated with the L4 SPIM master. This master is used to access the
4328  * APB slaves on the L4 SPIM bus.
4329  *
4330  */
4331 #ifndef __ASSEMBLY__
4332 /*
4333  * WARNING: The C register and register group struct declarations are provided for
4334  * convenience and illustrative purposes. They should, however, be used with
4335  * caution as the C language standard provides no guarantees about the alignment or
4336  * atomicity of device memory accesses. The recommended practice for writing
4337  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4338  * alt_write_word() functions.
4339  *
4340  * The struct declaration for register group ALT_L3_MST_L4SPIM.
4341  */
4343 {
4344  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4345  volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4346 };
4347 
4348 /* The typedef declaration for register group ALT_L3_MST_L4SPIM. */
4349 typedef volatile struct ALT_L3_MST_L4SPIM_s ALT_L3_MST_L4SPIM_t;
4350 /* The struct declaration for the raw register contents of register group ALT_L3_MST_L4SPIM. */
4352 {
4353  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4354  volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4355 };
4356 
4357 /* The typedef declaration for the raw register contents of register group ALT_L3_MST_L4SPIM. */
4358 typedef volatile struct ALT_L3_MST_L4SPIM_raw_s ALT_L3_MST_L4SPIM_raw_t;
4359 #endif /* __ASSEMBLY__ */
4360 
4361 
4362 /*
4363  * Register Group : STM - ALT_L3_MST_STM
4364  * STM
4365  *
4366  * Registers associated with the STM master. This master is used to access the STM
4367  * AXI slave.
4368  *
4369  */
4370 /*
4371  * Register : Issuing Functionality Modification Register - fn_mod
4372  *
4373  * Sets the block issuing capability to multiple or single outstanding
4374  * transactions.
4375  *
4376  * Register Layout
4377  *
4378  * Bits | Access | Reset | Description
4379  * :-------|:-------|:------|:-----------------
4380  * [0] | RW | 0x0 | ALT_L3_FN_MOD_RD
4381  * [1] | RW | 0x0 | ALT_L3_FN_MOD_WR
4382  * [31:2] | ??? | 0x0 | *UNDEFINED*
4383  *
4384  */
4385 /*
4386  * Field : rd
4387  *
4388  * Field Enumeration Values:
4389  *
4390  * Enum | Value | Description
4391  * :--------------------------|:------|:-------------------------------------------
4392  * ALT_L3_FN_MOD_RD_E_MULT | 0x0 | Multiple outstanding read transactions
4393  * ALT_L3_FN_MOD_RD_E_SINGLE | 0x1 | Only a single outstanding read transaction
4394  *
4395  * Field Access Macros:
4396  *
4397  */
4398 /*
4399  * Enumerated value for register field ALT_L3_FN_MOD_RD
4400  *
4401  * Multiple outstanding read transactions
4402  */
4403 #define ALT_L3_FN_MOD_RD_E_MULT 0x0
4404 /*
4405  * Enumerated value for register field ALT_L3_FN_MOD_RD
4406  *
4407  * Only a single outstanding read transaction
4408  */
4409 #define ALT_L3_FN_MOD_RD_E_SINGLE 0x1
4410 
4411 /* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_RD register field. */
4412 #define ALT_L3_FN_MOD_RD_LSB 0
4413 /* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_RD register field. */
4414 #define ALT_L3_FN_MOD_RD_MSB 0
4415 /* The width in bits of the ALT_L3_FN_MOD_RD register field. */
4416 #define ALT_L3_FN_MOD_RD_WIDTH 1
4417 /* The mask used to set the ALT_L3_FN_MOD_RD register field value. */
4418 #define ALT_L3_FN_MOD_RD_SET_MSK 0x00000001
4419 /* The mask used to clear the ALT_L3_FN_MOD_RD register field value. */
4420 #define ALT_L3_FN_MOD_RD_CLR_MSK 0xfffffffe
4421 /* The reset value of the ALT_L3_FN_MOD_RD register field. */
4422 #define ALT_L3_FN_MOD_RD_RESET 0x0
4423 /* Extracts the ALT_L3_FN_MOD_RD field value from a register. */
4424 #define ALT_L3_FN_MOD_RD_GET(value) (((value) & 0x00000001) >> 0)
4425 /* Produces a ALT_L3_FN_MOD_RD register field value suitable for setting the register. */
4426 #define ALT_L3_FN_MOD_RD_SET(value) (((value) << 0) & 0x00000001)
4427 
4428 /*
4429  * Field : wr
4430  *
4431  * Field Enumeration Values:
4432  *
4433  * Enum | Value | Description
4434  * :--------------------------|:------|:--------------------------------------------
4435  * ALT_L3_FN_MOD_WR_E_MULT | 0x0 | Multiple outstanding write transactions
4436  * ALT_L3_FN_MOD_WR_E_SINGLE | 0x1 | Only a single outstanding write transaction
4437  *
4438  * Field Access Macros:
4439  *
4440  */
4441 /*
4442  * Enumerated value for register field ALT_L3_FN_MOD_WR
4443  *
4444  * Multiple outstanding write transactions
4445  */
4446 #define ALT_L3_FN_MOD_WR_E_MULT 0x0
4447 /*
4448  * Enumerated value for register field ALT_L3_FN_MOD_WR
4449  *
4450  * Only a single outstanding write transaction
4451  */
4452 #define ALT_L3_FN_MOD_WR_E_SINGLE 0x1
4453 
4454 /* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_WR register field. */
4455 #define ALT_L3_FN_MOD_WR_LSB 1
4456 /* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_WR register field. */
4457 #define ALT_L3_FN_MOD_WR_MSB 1
4458 /* The width in bits of the ALT_L3_FN_MOD_WR register field. */
4459 #define ALT_L3_FN_MOD_WR_WIDTH 1
4460 /* The mask used to set the ALT_L3_FN_MOD_WR register field value. */
4461 #define ALT_L3_FN_MOD_WR_SET_MSK 0x00000002
4462 /* The mask used to clear the ALT_L3_FN_MOD_WR register field value. */
4463 #define ALT_L3_FN_MOD_WR_CLR_MSK 0xfffffffd
4464 /* The reset value of the ALT_L3_FN_MOD_WR register field. */
4465 #define ALT_L3_FN_MOD_WR_RESET 0x0
4466 /* Extracts the ALT_L3_FN_MOD_WR field value from a register. */
4467 #define ALT_L3_FN_MOD_WR_GET(value) (((value) & 0x00000002) >> 1)
4468 /* Produces a ALT_L3_FN_MOD_WR register field value suitable for setting the register. */
4469 #define ALT_L3_FN_MOD_WR_SET(value) (((value) << 1) & 0x00000002)
4470 
4471 #ifndef __ASSEMBLY__
4472 /*
4473  * WARNING: The C register and register group struct declarations are provided for
4474  * convenience and illustrative purposes. They should, however, be used with
4475  * caution as the C language standard provides no guarantees about the alignment or
4476  * atomicity of device memory accesses. The recommended practice for writing
4477  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4478  * alt_write_word() functions.
4479  *
4480  * The struct declaration for register ALT_L3_FN_MOD.
4481  */
4483 {
4484  uint32_t rd : 1; /* ALT_L3_FN_MOD_RD */
4485  uint32_t wr : 1; /* ALT_L3_FN_MOD_WR */
4486  uint32_t : 30; /* *UNDEFINED* */
4487 };
4488 
4489 /* The typedef declaration for register ALT_L3_FN_MOD. */
4490 typedef volatile struct ALT_L3_FN_MOD_s ALT_L3_FN_MOD_t;
4491 #endif /* __ASSEMBLY__ */
4492 
4493 /* The byte offset of the ALT_L3_FN_MOD register from the beginning of the component. */
4494 #define ALT_L3_FN_MOD_OFST 0x108
4495 /* The address of the ALT_L3_FN_MOD register. */
4496 #define ALT_L3_FN_MOD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_FN_MOD_OFST))
4497 
4498 #ifndef __ASSEMBLY__
4499 /*
4500  * WARNING: The C register and register group struct declarations are provided for
4501  * convenience and illustrative purposes. They should, however, be used with
4502  * caution as the C language standard provides no guarantees about the alignment or
4503  * atomicity of device memory accesses. The recommended practice for writing
4504  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4505  * alt_write_word() functions.
4506  *
4507  * The struct declaration for register group ALT_L3_MST_STM.
4508  */
4510 {
4511  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4512  volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4513  volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */
4514  volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
4515 };
4516 
4517 /* The typedef declaration for register group ALT_L3_MST_STM. */
4518 typedef volatile struct ALT_L3_MST_STM_s ALT_L3_MST_STM_t;
4519 /* The struct declaration for the raw register contents of register group ALT_L3_MST_STM. */
4521 {
4522  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4523  volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4524  volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */
4525  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
4526 };
4527 
4528 /* The typedef declaration for the raw register contents of register group ALT_L3_MST_STM. */
4529 typedef volatile struct ALT_L3_MST_STM_raw_s ALT_L3_MST_STM_raw_t;
4530 #endif /* __ASSEMBLY__ */
4531 
4532 
4533 /*
4534  * Register Group : LWHPS2FPGA - ALT_L3_MST_LWH2F
4535  * LWHPS2FPGA
4536  *
4537  * Registers associated with the LWHPS2FPGA AXI Bridge master. This master is used
4538  * to access the LWHPS2FPGA AXI Bridge slave. This slave is used to access the
4539  * registers for all 3 AXI bridges and to access slaves in the FPGA connected to
4540  * the LWHPS2FPGA AXI Bridge.
4541  *
4542  */
4543 #ifndef __ASSEMBLY__
4544 /*
4545  * WARNING: The C register and register group struct declarations are provided for
4546  * convenience and illustrative purposes. They should, however, be used with
4547  * caution as the C language standard provides no guarantees about the alignment or
4548  * atomicity of device memory accesses. The recommended practice for writing
4549  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4550  * alt_write_word() functions.
4551  *
4552  * The struct declaration for register group ALT_L3_MST_LWH2F.
4553  */
4555 {
4556  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4557  volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4558  volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */
4559  volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
4560 };
4561 
4562 /* The typedef declaration for register group ALT_L3_MST_LWH2F. */
4563 typedef volatile struct ALT_L3_MST_LWH2F_s ALT_L3_MST_LWH2F_t;
4564 /* The struct declaration for the raw register contents of register group ALT_L3_MST_LWH2F. */
4566 {
4567  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4568  volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4569  volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */
4570  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
4571 };
4572 
4573 /* The typedef declaration for the raw register contents of register group ALT_L3_MST_LWH2F. */
4574 typedef volatile struct ALT_L3_MST_LWH2F_raw_s ALT_L3_MST_LWH2F_raw_t;
4575 #endif /* __ASSEMBLY__ */
4576 
4577 
4578 /*
4579  * Register Group : USB1 - ALT_L3_MST_USB1
4580  * USB1
4581  *
4582  * Registers associated with the USB1 master. This master is used to access the
4583  * registers in USB1.
4584  *
4585  */
4586 /*
4587  * Register : AHB Control Register - ahb_cntl
4588  *
4589  * Sets the block issuing capability to one outstanding transaction.
4590  *
4591  * Register Layout
4592  *
4593  * Bits | Access | Reset | Description
4594  * :-------|:-------|:------|:---------------------------
4595  * [0] | RW | 0x0 | ALT_L3_AHB_CNTL_DECERR_EN
4596  * [1] | RW | 0x0 | ALT_L3_AHB_CNTL_FORCE_INCR
4597  * [31:2] | ??? | 0x0 | *UNDEFINED*
4598  *
4599  */
4600 /*
4601  * Field : decerr_en
4602  *
4603  * Field Enumeration Values:
4604  *
4605  * Enum | Value | Description
4606  * :--------------------------------|:------|:-------------------------------------------------
4607  * ALT_L3_AHB_CNTL_DECERR_EN_E_DIS | 0x0 | No DECERR response.
4608  * ALT_L3_AHB_CNTL_DECERR_EN_E_EN | 0x1 | If the AHB protocol conversion function receives
4609  * : | | an unaligned address or a write data beat
4610  * : | | without all the byte strobes set, creates a
4611  * : | | DECERR response.
4612  *
4613  * Field Access Macros:
4614  *
4615  */
4616 /*
4617  * Enumerated value for register field ALT_L3_AHB_CNTL_DECERR_EN
4618  *
4619  * No DECERR response.
4620  */
4621 #define ALT_L3_AHB_CNTL_DECERR_EN_E_DIS 0x0
4622 /*
4623  * Enumerated value for register field ALT_L3_AHB_CNTL_DECERR_EN
4624  *
4625  * If the AHB protocol conversion function receives an unaligned address or a write
4626  * data beat without all the byte strobes set, creates a DECERR response.
4627  */
4628 #define ALT_L3_AHB_CNTL_DECERR_EN_E_EN 0x1
4629 
4630 /* The Least Significant Bit (LSB) position of the ALT_L3_AHB_CNTL_DECERR_EN register field. */
4631 #define ALT_L3_AHB_CNTL_DECERR_EN_LSB 0
4632 /* The Most Significant Bit (MSB) position of the ALT_L3_AHB_CNTL_DECERR_EN register field. */
4633 #define ALT_L3_AHB_CNTL_DECERR_EN_MSB 0
4634 /* The width in bits of the ALT_L3_AHB_CNTL_DECERR_EN register field. */
4635 #define ALT_L3_AHB_CNTL_DECERR_EN_WIDTH 1
4636 /* The mask used to set the ALT_L3_AHB_CNTL_DECERR_EN register field value. */
4637 #define ALT_L3_AHB_CNTL_DECERR_EN_SET_MSK 0x00000001
4638 /* The mask used to clear the ALT_L3_AHB_CNTL_DECERR_EN register field value. */
4639 #define ALT_L3_AHB_CNTL_DECERR_EN_CLR_MSK 0xfffffffe
4640 /* The reset value of the ALT_L3_AHB_CNTL_DECERR_EN register field. */
4641 #define ALT_L3_AHB_CNTL_DECERR_EN_RESET 0x0
4642 /* Extracts the ALT_L3_AHB_CNTL_DECERR_EN field value from a register. */
4643 #define ALT_L3_AHB_CNTL_DECERR_EN_GET(value) (((value) & 0x00000001) >> 0)
4644 /* Produces a ALT_L3_AHB_CNTL_DECERR_EN register field value suitable for setting the register. */
4645 #define ALT_L3_AHB_CNTL_DECERR_EN_SET(value) (((value) << 0) & 0x00000001)
4646 
4647 /*
4648  * Field : force_incr
4649  *
4650  * Field Enumeration Values:
4651  *
4652  * Enum | Value | Description
4653  * :---------------------------------|:------|:-------------------------------------------------
4654  * ALT_L3_AHB_CNTL_FORCE_INCR_E_DIS | 0x0 | Multiple outstanding write transactions
4655  * ALT_L3_AHB_CNTL_FORCE_INCR_E_EN | 0x1 | If a beat is received that has no write data
4656  * : | | strobes set, that write data beat is replaced
4657  * : | | with an IDLE beat. Also, causes all transactions
4658  * : | | that are to be output to the AHB domain to be an
4659  * : | | undefined length INCR.
4660  *
4661  * Field Access Macros:
4662  *
4663  */
4664 /*
4665  * Enumerated value for register field ALT_L3_AHB_CNTL_FORCE_INCR
4666  *
4667  * Multiple outstanding write transactions
4668  */
4669 #define ALT_L3_AHB_CNTL_FORCE_INCR_E_DIS 0x0
4670 /*
4671  * Enumerated value for register field ALT_L3_AHB_CNTL_FORCE_INCR
4672  *
4673  * If a beat is received that has no write data strobes set, that write data beat
4674  * is replaced with an IDLE beat. Also, causes all transactions that are to be
4675  * output to the AHB domain to be an undefined length INCR.
4676  */
4677 #define ALT_L3_AHB_CNTL_FORCE_INCR_E_EN 0x1
4678 
4679 /* The Least Significant Bit (LSB) position of the ALT_L3_AHB_CNTL_FORCE_INCR register field. */
4680 #define ALT_L3_AHB_CNTL_FORCE_INCR_LSB 1
4681 /* The Most Significant Bit (MSB) position of the ALT_L3_AHB_CNTL_FORCE_INCR register field. */
4682 #define ALT_L3_AHB_CNTL_FORCE_INCR_MSB 1
4683 /* The width in bits of the ALT_L3_AHB_CNTL_FORCE_INCR register field. */
4684 #define ALT_L3_AHB_CNTL_FORCE_INCR_WIDTH 1
4685 /* The mask used to set the ALT_L3_AHB_CNTL_FORCE_INCR register field value. */
4686 #define ALT_L3_AHB_CNTL_FORCE_INCR_SET_MSK 0x00000002
4687 /* The mask used to clear the ALT_L3_AHB_CNTL_FORCE_INCR register field value. */
4688 #define ALT_L3_AHB_CNTL_FORCE_INCR_CLR_MSK 0xfffffffd
4689 /* The reset value of the ALT_L3_AHB_CNTL_FORCE_INCR register field. */
4690 #define ALT_L3_AHB_CNTL_FORCE_INCR_RESET 0x0
4691 /* Extracts the ALT_L3_AHB_CNTL_FORCE_INCR field value from a register. */
4692 #define ALT_L3_AHB_CNTL_FORCE_INCR_GET(value) (((value) & 0x00000002) >> 1)
4693 /* Produces a ALT_L3_AHB_CNTL_FORCE_INCR register field value suitable for setting the register. */
4694 #define ALT_L3_AHB_CNTL_FORCE_INCR_SET(value) (((value) << 1) & 0x00000002)
4695 
4696 #ifndef __ASSEMBLY__
4697 /*
4698  * WARNING: The C register and register group struct declarations are provided for
4699  * convenience and illustrative purposes. They should, however, be used with
4700  * caution as the C language standard provides no guarantees about the alignment or
4701  * atomicity of device memory accesses. The recommended practice for writing
4702  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4703  * alt_write_word() functions.
4704  *
4705  * The struct declaration for register ALT_L3_AHB_CNTL.
4706  */
4708 {
4709  uint32_t decerr_en : 1; /* ALT_L3_AHB_CNTL_DECERR_EN */
4710  uint32_t force_incr : 1; /* ALT_L3_AHB_CNTL_FORCE_INCR */
4711  uint32_t : 30; /* *UNDEFINED* */
4712 };
4713 
4714 /* The typedef declaration for register ALT_L3_AHB_CNTL. */
4715 typedef volatile struct ALT_L3_AHB_CNTL_s ALT_L3_AHB_CNTL_t;
4716 #endif /* __ASSEMBLY__ */
4717 
4718 /* The byte offset of the ALT_L3_AHB_CNTL register from the beginning of the component. */
4719 #define ALT_L3_AHB_CNTL_OFST 0x44
4720 /* The address of the ALT_L3_AHB_CNTL register. */
4721 #define ALT_L3_AHB_CNTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_AHB_CNTL_OFST))
4722 
4723 #ifndef __ASSEMBLY__
4724 /*
4725  * WARNING: The C register and register group struct declarations are provided for
4726  * convenience and illustrative purposes. They should, however, be used with
4727  * caution as the C language standard provides no guarantees about the alignment or
4728  * atomicity of device memory accesses. The recommended practice for writing
4729  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4730  * alt_write_word() functions.
4731  *
4732  * The struct declaration for register group ALT_L3_MST_USB1.
4733  */
4735 {
4736  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4737  volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4738  volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */
4739  volatile ALT_L3_AHB_CNTL_t ahb_cntl; /* ALT_L3_AHB_CNTL */
4740 };
4741 
4742 /* The typedef declaration for register group ALT_L3_MST_USB1. */
4743 typedef volatile struct ALT_L3_MST_USB1_s ALT_L3_MST_USB1_t;
4744 /* The struct declaration for the raw register contents of register group ALT_L3_MST_USB1. */
4746 {
4747  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4748  volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4749  volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */
4750  volatile uint32_t ahb_cntl; /* ALT_L3_AHB_CNTL */
4751 };
4752 
4753 /* The typedef declaration for the raw register contents of register group ALT_L3_MST_USB1. */
4754 typedef volatile struct ALT_L3_MST_USB1_raw_s ALT_L3_MST_USB1_raw_t;
4755 #endif /* __ASSEMBLY__ */
4756 
4757 
4758 /*
4759  * Register Group : NANDDATA - ALT_L3_MST_NANDDATA
4760  * NANDDATA
4761  *
4762  * Registers associated with the NANDDATA master. This master is used to access
4763  * data in the NAND flash controller.
4764  *
4765  */
4766 #ifndef __ASSEMBLY__
4767 /*
4768  * WARNING: The C register and register group struct declarations are provided for
4769  * convenience and illustrative purposes. They should, however, be used with
4770  * caution as the C language standard provides no guarantees about the alignment or
4771  * atomicity of device memory accesses. The recommended practice for writing
4772  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4773  * alt_write_word() functions.
4774  *
4775  * The struct declaration for register group ALT_L3_MST_NANDDATA.
4776  */
4778 {
4779  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4780  volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4781  volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */
4782  volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
4783 };
4784 
4785 /* The typedef declaration for register group ALT_L3_MST_NANDDATA. */
4786 typedef volatile struct ALT_L3_MST_NANDDATA_s ALT_L3_MST_NANDDATA_t;
4787 /* The struct declaration for the raw register contents of register group ALT_L3_MST_NANDDATA. */
4789 {
4790  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4791  volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4792  volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */
4793  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
4794 };
4795 
4796 /* The typedef declaration for the raw register contents of register group ALT_L3_MST_NANDDATA. */
4797 typedef volatile struct ALT_L3_MST_NANDDATA_raw_s ALT_L3_MST_NANDDATA_raw_t;
4798 #endif /* __ASSEMBLY__ */
4799 
4800 
4801 /*
4802  * Register Group : USB0 - ALT_L3_MST_USB0
4803  * USB0
4804  *
4805  * Registers associated with the USB0 master. This master is used to access the
4806  * registers in USB0.
4807  *
4808  */
4809 #ifndef __ASSEMBLY__
4810 /*
4811  * WARNING: The C register and register group struct declarations are provided for
4812  * convenience and illustrative purposes. They should, however, be used with
4813  * caution as the C language standard provides no guarantees about the alignment or
4814  * atomicity of device memory accesses. The recommended practice for writing
4815  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4816  * alt_write_word() functions.
4817  *
4818  * The struct declaration for register group ALT_L3_MST_USB0.
4819  */
4821 {
4822  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4823  volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4824  volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */
4825  volatile ALT_L3_AHB_CNTL_t ahb_cntl; /* ALT_L3_AHB_CNTL */
4826 };
4827 
4828 /* The typedef declaration for register group ALT_L3_MST_USB0. */
4829 typedef volatile struct ALT_L3_MST_USB0_s ALT_L3_MST_USB0_t;
4830 /* The struct declaration for the raw register contents of register group ALT_L3_MST_USB0. */
4832 {
4833  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4834  volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4835  volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */
4836  volatile uint32_t ahb_cntl; /* ALT_L3_AHB_CNTL */
4837 };
4838 
4839 /* The typedef declaration for the raw register contents of register group ALT_L3_MST_USB0. */
4840 typedef volatile struct ALT_L3_MST_USB0_raw_s ALT_L3_MST_USB0_raw_t;
4841 #endif /* __ASSEMBLY__ */
4842 
4843 
4844 /*
4845  * Register Group : NANDREGS - ALT_L3_MST_NAND
4846  * NANDREGS
4847  *
4848  * Registers associated with the NANDREGS master. This master is used to access the
4849  * registers in the NAND flash controller.
4850  *
4851  */
4852 #ifndef __ASSEMBLY__
4853 /*
4854  * WARNING: The C register and register group struct declarations are provided for
4855  * convenience and illustrative purposes. They should, however, be used with
4856  * caution as the C language standard provides no guarantees about the alignment or
4857  * atomicity of device memory accesses. The recommended practice for writing
4858  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4859  * alt_write_word() functions.
4860  *
4861  * The struct declaration for register group ALT_L3_MST_NAND.
4862  */
4864 {
4865  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4866  volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4867  volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */
4868  volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
4869 };
4870 
4871 /* The typedef declaration for register group ALT_L3_MST_NAND. */
4872 typedef volatile struct ALT_L3_MST_NAND_s ALT_L3_MST_NAND_t;
4873 /* The struct declaration for the raw register contents of register group ALT_L3_MST_NAND. */
4875 {
4876  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4877  volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4878  volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */
4879  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
4880 };
4881 
4882 /* The typedef declaration for the raw register contents of register group ALT_L3_MST_NAND. */
4883 typedef volatile struct ALT_L3_MST_NAND_raw_s ALT_L3_MST_NAND_raw_t;
4884 #endif /* __ASSEMBLY__ */
4885 
4886 
4887 /*
4888  * Register Group : QSPIDATA - ALT_L3_MST_QSPIDATA
4889  * QSPIDATA
4890  *
4891  * Registers associated with the QSPIDATA master. This master is used to access
4892  * data in the QSPI flash controller.
4893  *
4894  */
4895 #ifndef __ASSEMBLY__
4896 /*
4897  * WARNING: The C register and register group struct declarations are provided for
4898  * convenience and illustrative purposes. They should, however, be used with
4899  * caution as the C language standard provides no guarantees about the alignment or
4900  * atomicity of device memory accesses. The recommended practice for writing
4901  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4902  * alt_write_word() functions.
4903  *
4904  * The struct declaration for register group ALT_L3_MST_QSPIDATA.
4905  */
4907 {
4908  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4909  volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4910  volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */
4911  volatile ALT_L3_AHB_CNTL_t ahb_cntl; /* ALT_L3_AHB_CNTL */
4912 };
4913 
4914 /* The typedef declaration for register group ALT_L3_MST_QSPIDATA. */
4915 typedef volatile struct ALT_L3_MST_QSPIDATA_s ALT_L3_MST_QSPIDATA_t;
4916 /* The struct declaration for the raw register contents of register group ALT_L3_MST_QSPIDATA. */
4918 {
4919  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4920  volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4921  volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */
4922  volatile uint32_t ahb_cntl; /* ALT_L3_AHB_CNTL */
4923 };
4924 
4925 /* The typedef declaration for the raw register contents of register group ALT_L3_MST_QSPIDATA. */
4926 typedef volatile struct ALT_L3_MST_QSPIDATA_raw_s ALT_L3_MST_QSPIDATA_raw_t;
4927 #endif /* __ASSEMBLY__ */
4928 
4929 
4930 /*
4931  * Register Group : FPGAMGRDATA - ALT_L3_MST_FPGAMGRDATA
4932  * FPGAMGRDATA
4933  *
4934  * Registers associated with the FPGAMGRDATA master. This master is used to send
4935  * FPGA configuration image data to the FPGA Manager.
4936  *
4937  */
4938 /*
4939  * Register : Write Tidemark - wr_tidemark
4940  *
4941  * Controls the release of the transaction in the write data FIFO.
4942  *
4943  * Register Layout
4944  *
4945  * Bits | Access | Reset | Description
4946  * :-------|:-------|:------|:------------
4947  * [3:0] | RW | 0x4 | Level
4948  * [31:4] | ??? | 0x0 | *UNDEFINED*
4949  *
4950  */
4951 /*
4952  * Field : Level - level
4953  *
4954  * Stalls the transaction in the write data FIFO until the number of occupied slots
4955  * in the write data FIFO exceeds the level. Note that the transaction is released
4956  * before this level is achieved if the network receives the WLAST beat or the
4957  * write FIFO becomes full.
4958  *
4959  * Field Access Macros:
4960  *
4961  */
4962 /* The Least Significant Bit (LSB) position of the ALT_L3_WR_TIDEMARK_LEVEL register field. */
4963 #define ALT_L3_WR_TIDEMARK_LEVEL_LSB 0
4964 /* The Most Significant Bit (MSB) position of the ALT_L3_WR_TIDEMARK_LEVEL register field. */
4965 #define ALT_L3_WR_TIDEMARK_LEVEL_MSB 3
4966 /* The width in bits of the ALT_L3_WR_TIDEMARK_LEVEL register field. */
4967 #define ALT_L3_WR_TIDEMARK_LEVEL_WIDTH 4
4968 /* The mask used to set the ALT_L3_WR_TIDEMARK_LEVEL register field value. */
4969 #define ALT_L3_WR_TIDEMARK_LEVEL_SET_MSK 0x0000000f
4970 /* The mask used to clear the ALT_L3_WR_TIDEMARK_LEVEL register field value. */
4971 #define ALT_L3_WR_TIDEMARK_LEVEL_CLR_MSK 0xfffffff0
4972 /* The reset value of the ALT_L3_WR_TIDEMARK_LEVEL register field. */
4973 #define ALT_L3_WR_TIDEMARK_LEVEL_RESET 0x4
4974 /* Extracts the ALT_L3_WR_TIDEMARK_LEVEL field value from a register. */
4975 #define ALT_L3_WR_TIDEMARK_LEVEL_GET(value) (((value) & 0x0000000f) >> 0)
4976 /* Produces a ALT_L3_WR_TIDEMARK_LEVEL register field value suitable for setting the register. */
4977 #define ALT_L3_WR_TIDEMARK_LEVEL_SET(value) (((value) << 0) & 0x0000000f)
4978 
4979 #ifndef __ASSEMBLY__
4980 /*
4981  * WARNING: The C register and register group struct declarations are provided for
4982  * convenience and illustrative purposes. They should, however, be used with
4983  * caution as the C language standard provides no guarantees about the alignment or
4984  * atomicity of device memory accesses. The recommended practice for writing
4985  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4986  * alt_write_word() functions.
4987  *
4988  * The struct declaration for register ALT_L3_WR_TIDEMARK.
4989  */
4991 {
4992  uint32_t level : 4; /* Level */
4993  uint32_t : 28; /* *UNDEFINED* */
4994 };
4995 
4996 /* The typedef declaration for register ALT_L3_WR_TIDEMARK. */
4997 typedef volatile struct ALT_L3_WR_TIDEMARK_s ALT_L3_WR_TIDEMARK_t;
4998 #endif /* __ASSEMBLY__ */
4999 
5000 /* The byte offset of the ALT_L3_WR_TIDEMARK register from the beginning of the component. */
5001 #define ALT_L3_WR_TIDEMARK_OFST 0x40
5002 /* The address of the ALT_L3_WR_TIDEMARK register. */
5003 #define ALT_L3_WR_TIDEMARK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_WR_TIDEMARK_OFST))
5004 
5005 #ifndef __ASSEMBLY__
5006 /*
5007  * WARNING: The C register and register group struct declarations are provided for
5008  * convenience and illustrative purposes. They should, however, be used with
5009  * caution as the C language standard provides no guarantees about the alignment or
5010  * atomicity of device memory accesses. The recommended practice for writing
5011  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5012  * alt_write_word() functions.
5013  *
5014  * The struct declaration for register group ALT_L3_MST_FPGAMGRDATA.
5015  */
5017 {
5018  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
5019  volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
5020  volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */
5021  volatile ALT_L3_WR_TIDEMARK_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */
5022  volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */
5023  volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
5024 };
5025 
5026 /* The typedef declaration for register group ALT_L3_MST_FPGAMGRDATA. */
5027 typedef volatile struct ALT_L3_MST_FPGAMGRDATA_s ALT_L3_MST_FPGAMGRDATA_t;
5028 /* The struct declaration for the raw register contents of register group ALT_L3_MST_FPGAMGRDATA. */
5030 {
5031  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
5032  volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
5033  volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */
5034  volatile uint32_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */
5035  volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */
5036  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
5037 };
5038 
5039 /* The typedef declaration for the raw register contents of register group ALT_L3_MST_FPGAMGRDATA. */
5040 typedef volatile struct ALT_L3_MST_FPGAMGRDATA_raw_s ALT_L3_MST_FPGAMGRDATA_raw_t;
5041 #endif /* __ASSEMBLY__ */
5042 
5043 
5044 /*
5045  * Register Group : HPS2FPGA - ALT_L3_MST_H2F
5046  * HPS2FPGA
5047  *
5048  * Registers associated with the HPS2FPGA AXI Bridge master. This master is used to
5049  * access the HPS2FPGA AXI Bridge slave. This slave is used to access slaves in the
5050  * FPGA connected to the HPS2FPGA AXI Bridge.
5051  *
5052  */
5053 #ifndef __ASSEMBLY__
5054 /*
5055  * WARNING: The C register and register group struct declarations are provided for
5056  * convenience and illustrative purposes. They should, however, be used with
5057  * caution as the C language standard provides no guarantees about the alignment or
5058  * atomicity of device memory accesses. The recommended practice for writing
5059  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5060  * alt_write_word() functions.
5061  *
5062  * The struct declaration for register group ALT_L3_MST_H2F.
5063  */
5065 {
5066  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
5067  volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
5068  volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */
5069  volatile ALT_L3_WR_TIDEMARK_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */
5070  volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */
5071  volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
5072 };
5073 
5074 /* The typedef declaration for register group ALT_L3_MST_H2F. */
5075 typedef volatile struct ALT_L3_MST_H2F_s ALT_L3_MST_H2F_t;
5076 /* The struct declaration for the raw register contents of register group ALT_L3_MST_H2F. */
5078 {
5079  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
5080  volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
5081  volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */
5082  volatile uint32_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */
5083  volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */
5084  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
5085 };
5086 
5087 /* The typedef declaration for the raw register contents of register group ALT_L3_MST_H2F. */
5088 typedef volatile struct ALT_L3_MST_H2F_raw_s ALT_L3_MST_H2F_raw_t;
5089 #endif /* __ASSEMBLY__ */
5090 
5091 
5092 /*
5093  * Register Group : ACP - ALT_L3_MST_ACP
5094  * ACP
5095  *
5096  * Registers associated with the ACP master. This master is used to access the MPU
5097  * ACP slave via the ACP ID Mapper.
5098  *
5099  */
5100 #ifndef __ASSEMBLY__
5101 /*
5102  * WARNING: The C register and register group struct declarations are provided for
5103  * convenience and illustrative purposes. They should, however, be used with
5104  * caution as the C language standard provides no guarantees about the alignment or
5105  * atomicity of device memory accesses. The recommended practice for writing
5106  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5107  * alt_write_word() functions.
5108  *
5109  * The struct declaration for register group ALT_L3_MST_ACP.
5110  */
5112 {
5113  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
5114  volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
5115  volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */
5116  volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
5117 };
5118 
5119 /* The typedef declaration for register group ALT_L3_MST_ACP. */
5120 typedef volatile struct ALT_L3_MST_ACP_s ALT_L3_MST_ACP_t;
5121 /* The struct declaration for the raw register contents of register group ALT_L3_MST_ACP. */
5123 {
5124  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
5125  volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
5126  volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */
5127  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
5128 };
5129 
5130 /* The typedef declaration for the raw register contents of register group ALT_L3_MST_ACP. */
5131 typedef volatile struct ALT_L3_MST_ACP_raw_s ALT_L3_MST_ACP_raw_t;
5132 #endif /* __ASSEMBLY__ */
5133 
5134 
5135 /*
5136  * Register Group : Boot ROM - ALT_L3_MST_ROM
5137  * Boot ROM
5138  *
5139  * Registers associated with the Boot ROM master. This master is used to access the
5140  * contents of the Boot ROM.
5141  *
5142  */
5143 #ifndef __ASSEMBLY__
5144 /*
5145  * WARNING: The C register and register group struct declarations are provided for
5146  * convenience and illustrative purposes. They should, however, be used with
5147  * caution as the C language standard provides no guarantees about the alignment or
5148  * atomicity of device memory accesses. The recommended practice for writing
5149  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5150  * alt_write_word() functions.
5151  *
5152  * The struct declaration for register group ALT_L3_MST_ROM.
5153  */
5155 {
5156  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
5157  volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
5158  volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */
5159  volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
5160 };
5161 
5162 /* The typedef declaration for register group ALT_L3_MST_ROM. */
5163 typedef volatile struct ALT_L3_MST_ROM_s ALT_L3_MST_ROM_t;
5164 /* The struct declaration for the raw register contents of register group ALT_L3_MST_ROM. */
5166 {
5167  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
5168  volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
5169  volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */
5170  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
5171 };
5172 
5173 /* The typedef declaration for the raw register contents of register group ALT_L3_MST_ROM. */
5174 typedef volatile struct ALT_L3_MST_ROM_raw_s ALT_L3_MST_ROM_raw_t;
5175 #endif /* __ASSEMBLY__ */
5176 
5177 
5178 /*
5179  * Register Group : On-chip RAM - ALT_L3_MST_OCRAM
5180  * On-chip RAM
5181  *
5182  * Registers associated with the On-chip RAM master. This master is used to access
5183  * the contents of the On-chip RAM.
5184  *
5185  */
5186 #ifndef __ASSEMBLY__
5187 /*
5188  * WARNING: The C register and register group struct declarations are provided for
5189  * convenience and illustrative purposes. They should, however, be used with
5190  * caution as the C language standard provides no guarantees about the alignment or
5191  * atomicity of device memory accesses. The recommended practice for writing
5192  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5193  * alt_write_word() functions.
5194  *
5195  * The struct declaration for register group ALT_L3_MST_OCRAM.
5196  */
5198 {
5199  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
5200  volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
5201  volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */
5202  volatile ALT_L3_WR_TIDEMARK_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */
5203  volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */
5204  volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
5205 };
5206 
5207 /* The typedef declaration for register group ALT_L3_MST_OCRAM. */
5208 typedef volatile struct ALT_L3_MST_OCRAM_s ALT_L3_MST_OCRAM_t;
5209 /* The struct declaration for the raw register contents of register group ALT_L3_MST_OCRAM. */
5211 {
5212  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
5213  volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
5214  volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */
5215  volatile uint32_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */
5216  volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */
5217  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
5218 };
5219 
5220 /* The typedef declaration for the raw register contents of register group ALT_L3_MST_OCRAM. */
5221 typedef volatile struct ALT_L3_MST_OCRAM_raw_s ALT_L3_MST_OCRAM_raw_t;
5222 #endif /* __ASSEMBLY__ */
5223 
5224 
5225 #ifndef __ASSEMBLY__
5226 /*
5227  * WARNING: The C register and register group struct declarations are provided for
5228  * convenience and illustrative purposes. They should, however, be used with
5229  * caution as the C language standard provides no guarantees about the alignment or
5230  * atomicity of device memory accesses. The recommended practice for writing
5231  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5232  * alt_write_word() functions.
5233  *
5234  * The struct declaration for register group ALT_L3_MSTGRP.
5235  */
5237 {
5238  volatile ALT_L3_MST_L4MAIN_t mastergrp_l4main; /* ALT_L3_MST_L4MAIN */
5239  volatile uint32_t _pad_0xc_0xfff[1021]; /* *UNDEFINED* */
5240  volatile ALT_L3_MST_L4SP_t mastergrp_l4sp; /* ALT_L3_MST_L4SP */
5241  volatile uint32_t _pad_0x100c_0x1fff[1021]; /* *UNDEFINED* */
5242  volatile ALT_L3_MST_L4MP_t mastergrp_l4mp; /* ALT_L3_MST_L4MP */
5243  volatile uint32_t _pad_0x200c_0x2fff[1021]; /* *UNDEFINED* */
5244  volatile ALT_L3_MST_L4OSC1_t mastergrp_l4osc1; /* ALT_L3_MST_L4OSC1 */
5245  volatile uint32_t _pad_0x300c_0x3fff[1021]; /* *UNDEFINED* */
5246  volatile ALT_L3_MST_L4SPIM_t mastergrp_l4spim; /* ALT_L3_MST_L4SPIM */
5247  volatile uint32_t _pad_0x400c_0x4fff[1021]; /* *UNDEFINED* */
5248  volatile ALT_L3_MST_STM_t mastergrp_stm; /* ALT_L3_MST_STM */
5249  volatile uint32_t _pad_0x510c_0x5fff[957]; /* *UNDEFINED* */
5250  volatile ALT_L3_MST_LWH2F_t mastergrp_lwhps2fpga; /* ALT_L3_MST_LWH2F */
5251  volatile uint32_t _pad_0x610c_0x7fff[1981]; /* *UNDEFINED* */
5252  volatile ALT_L3_MST_USB1_t mastergrp_usb1; /* ALT_L3_MST_USB1 */
5253  volatile uint32_t _pad_0x8048_0x8fff[1006]; /* *UNDEFINED* */
5254  volatile ALT_L3_MST_NANDDATA_t mastergrp_nanddata; /* ALT_L3_MST_NANDDATA */
5255  volatile uint32_t _pad_0x910c_0x1dfff[21437]; /* *UNDEFINED* */
5256  volatile ALT_L3_MST_USB0_t mastergrp_usb0; /* ALT_L3_MST_USB0 */
5257  volatile uint32_t _pad_0x1e048_0x1efff[1006]; /* *UNDEFINED* */
5258  volatile ALT_L3_MST_NAND_t mastergrp_nandregs; /* ALT_L3_MST_NAND */
5259  volatile uint32_t _pad_0x1f10c_0x1ffff[957]; /* *UNDEFINED* */
5260  volatile ALT_L3_MST_QSPIDATA_t mastergrp_qspidata; /* ALT_L3_MST_QSPIDATA */
5261  volatile uint32_t _pad_0x20048_0x20fff[1006]; /* *UNDEFINED* */
5262  volatile ALT_L3_MST_FPGAMGRDATA_t mastergrp_fpgamgrdata; /* ALT_L3_MST_FPGAMGRDATA */
5263  volatile uint32_t _pad_0x2110c_0x21fff[957]; /* *UNDEFINED* */
5264  volatile ALT_L3_MST_H2F_t mastergrp_hps2fpga; /* ALT_L3_MST_H2F */
5265  volatile uint32_t _pad_0x2210c_0x22fff[957]; /* *UNDEFINED* */
5266  volatile ALT_L3_MST_ACP_t mastergrp_acp; /* ALT_L3_MST_ACP */
5267  volatile uint32_t _pad_0x2310c_0x23fff[957]; /* *UNDEFINED* */
5268  volatile ALT_L3_MST_ROM_t mastergrp_rom; /* ALT_L3_MST_ROM */
5269  volatile uint32_t _pad_0x2410c_0x24fff[957]; /* *UNDEFINED* */
5270  volatile ALT_L3_MST_OCRAM_t mastergrp_ocram; /* ALT_L3_MST_OCRAM */
5271 };
5272 
5273 /* The typedef declaration for register group ALT_L3_MSTGRP. */
5274 typedef volatile struct ALT_L3_MSTGRP_s ALT_L3_MSTGRP_t;
5275 /* The struct declaration for the raw register contents of register group ALT_L3_MSTGRP. */
5277 {
5278  volatile ALT_L3_MST_L4MAIN_raw_t mastergrp_l4main; /* ALT_L3_MST_L4MAIN */
5279  volatile uint32_t _pad_0xc_0xfff[1021]; /* *UNDEFINED* */
5280  volatile ALT_L3_MST_L4SP_raw_t mastergrp_l4sp; /* ALT_L3_MST_L4SP */
5281  volatile uint32_t _pad_0x100c_0x1fff[1021]; /* *UNDEFINED* */
5282  volatile ALT_L3_MST_L4MP_raw_t mastergrp_l4mp; /* ALT_L3_MST_L4MP */
5283  volatile uint32_t _pad_0x200c_0x2fff[1021]; /* *UNDEFINED* */
5284  volatile ALT_L3_MST_L4OSC1_raw_t mastergrp_l4osc1; /* ALT_L3_MST_L4OSC1 */
5285  volatile uint32_t _pad_0x300c_0x3fff[1021]; /* *UNDEFINED* */
5286  volatile ALT_L3_MST_L4SPIM_raw_t mastergrp_l4spim; /* ALT_L3_MST_L4SPIM */
5287  volatile uint32_t _pad_0x400c_0x4fff[1021]; /* *UNDEFINED* */
5288  volatile ALT_L3_MST_STM_raw_t mastergrp_stm; /* ALT_L3_MST_STM */
5289  volatile uint32_t _pad_0x510c_0x5fff[957]; /* *UNDEFINED* */
5290  volatile ALT_L3_MST_LWH2F_raw_t mastergrp_lwhps2fpga; /* ALT_L3_MST_LWH2F */
5291  volatile uint32_t _pad_0x610c_0x7fff[1981]; /* *UNDEFINED* */
5292  volatile ALT_L3_MST_USB1_raw_t mastergrp_usb1; /* ALT_L3_MST_USB1 */
5293  volatile uint32_t _pad_0x8048_0x8fff[1006]; /* *UNDEFINED* */
5294  volatile ALT_L3_MST_NANDDATA_raw_t mastergrp_nanddata; /* ALT_L3_MST_NANDDATA */
5295  volatile uint32_t _pad_0x910c_0x1dfff[21437]; /* *UNDEFINED* */
5296  volatile ALT_L3_MST_USB0_raw_t mastergrp_usb0; /* ALT_L3_MST_USB0 */
5297  volatile uint32_t _pad_0x1e048_0x1efff[1006]; /* *UNDEFINED* */
5298  volatile ALT_L3_MST_NAND_raw_t mastergrp_nandregs; /* ALT_L3_MST_NAND */
5299  volatile uint32_t _pad_0x1f10c_0x1ffff[957]; /* *UNDEFINED* */
5300  volatile ALT_L3_MST_QSPIDATA_raw_t mastergrp_qspidata; /* ALT_L3_MST_QSPIDATA */
5301  volatile uint32_t _pad_0x20048_0x20fff[1006]; /* *UNDEFINED* */
5302  volatile ALT_L3_MST_FPGAMGRDATA_raw_t mastergrp_fpgamgrdata; /* ALT_L3_MST_FPGAMGRDATA */
5303  volatile uint32_t _pad_0x2110c_0x21fff[957]; /* *UNDEFINED* */
5304  volatile ALT_L3_MST_H2F_raw_t mastergrp_hps2fpga; /* ALT_L3_MST_H2F */
5305  volatile uint32_t _pad_0x2210c_0x22fff[957]; /* *UNDEFINED* */
5306  volatile ALT_L3_MST_ACP_raw_t mastergrp_acp; /* ALT_L3_MST_ACP */
5307  volatile uint32_t _pad_0x2310c_0x23fff[957]; /* *UNDEFINED* */
5308  volatile ALT_L3_MST_ROM_raw_t mastergrp_rom; /* ALT_L3_MST_ROM */
5309  volatile uint32_t _pad_0x2410c_0x24fff[957]; /* *UNDEFINED* */
5310  volatile ALT_L3_MST_OCRAM_raw_t mastergrp_ocram; /* ALT_L3_MST_OCRAM */
5311 };
5312 
5313 /* The typedef declaration for the raw register contents of register group ALT_L3_MSTGRP. */
5314 typedef volatile struct ALT_L3_MSTGRP_raw_s ALT_L3_MSTGRP_raw_t;
5315 #endif /* __ASSEMBLY__ */
5316 
5317 
5318 /*
5319  * Register Group : Slave Register Group - ALT_L3_SLVGRP
5320  * Slave Register Group
5321  *
5322  * Registers associated with slave interfaces.
5323  *
5324  */
5325 /*
5326  * Register Group : DAP - ALT_L3_SLV_DAP
5327  * DAP
5328  *
5329  * Registers associated with the DAP slave interface. This slave is used by the DAP
5330  * to access slaves attached to the L3/L4 Interconnect.
5331  *
5332  */
5333 /*
5334  * Register : Functionality Modification 2 Register - fn_mod2
5335  *
5336  * Controls bypass merge of upsizing/downsizing.
5337  *
5338  * Register Layout
5339  *
5340  * Bits | Access | Reset | Description
5341  * :-------|:-------|:------|:-------------
5342  * [0] | RW | 0x0 | Bypass Merge
5343  * [31:1] | ??? | 0x0 | *UNDEFINED*
5344  *
5345  */
5346 /*
5347  * Field : Bypass Merge - bypass_merge
5348  *
5349  * Controls bypass merge of upsizing/downsizing.
5350  *
5351  * Field Enumeration Values:
5352  *
5353  * Enum | Value | Description
5354  * :--------------------------------------|:------|:-------------------------------------------------
5355  * ALT_L3_FN_MOD2_BYPASS_MERGE_E_ALTER | 0x0 | The network can alter transactions.
5356  * ALT_L3_FN_MOD2_BYPASS_MERGE_E_NOALTER | 0x1 | The network does not alter any transactions that
5357  * : | | could pass through the upsizer legally without
5358  * : | | alteration.
5359  *
5360  * Field Access Macros:
5361  *
5362  */
5363 /*
5364  * Enumerated value for register field ALT_L3_FN_MOD2_BYPASS_MERGE
5365  *
5366  * The network can alter transactions.
5367  */
5368 #define ALT_L3_FN_MOD2_BYPASS_MERGE_E_ALTER 0x0
5369 /*
5370  * Enumerated value for register field ALT_L3_FN_MOD2_BYPASS_MERGE
5371  *
5372  * The network does not alter any transactions that could pass through the upsizer
5373  * legally without alteration.
5374  */
5375 #define ALT_L3_FN_MOD2_BYPASS_MERGE_E_NOALTER 0x1
5376 
5377 /* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD2_BYPASS_MERGE register field. */
5378 #define ALT_L3_FN_MOD2_BYPASS_MERGE_LSB 0
5379 /* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD2_BYPASS_MERGE register field. */
5380 #define ALT_L3_FN_MOD2_BYPASS_MERGE_MSB 0
5381 /* The width in bits of the ALT_L3_FN_MOD2_BYPASS_MERGE register field. */
5382 #define ALT_L3_FN_MOD2_BYPASS_MERGE_WIDTH 1
5383 /* The mask used to set the ALT_L3_FN_MOD2_BYPASS_MERGE register field value. */
5384 #define ALT_L3_FN_MOD2_BYPASS_MERGE_SET_MSK 0x00000001
5385 /* The mask used to clear the ALT_L3_FN_MOD2_BYPASS_MERGE register field value. */
5386 #define ALT_L3_FN_MOD2_BYPASS_MERGE_CLR_MSK 0xfffffffe
5387 /* The reset value of the ALT_L3_FN_MOD2_BYPASS_MERGE register field. */
5388 #define ALT_L3_FN_MOD2_BYPASS_MERGE_RESET 0x0
5389 /* Extracts the ALT_L3_FN_MOD2_BYPASS_MERGE field value from a register. */
5390 #define ALT_L3_FN_MOD2_BYPASS_MERGE_GET(value) (((value) & 0x00000001) >> 0)
5391 /* Produces a ALT_L3_FN_MOD2_BYPASS_MERGE register field value suitable for setting the register. */
5392 #define ALT_L3_FN_MOD2_BYPASS_MERGE_SET(value) (((value) << 0) & 0x00000001)
5393 
5394 #ifndef __ASSEMBLY__
5395 /*
5396  * WARNING: The C register and register group struct declarations are provided for
5397  * convenience and illustrative purposes. They should, however, be used with
5398  * caution as the C language standard provides no guarantees about the alignment or
5399  * atomicity of device memory accesses. The recommended practice for writing
5400  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5401  * alt_write_word() functions.
5402  *
5403  * The struct declaration for register ALT_L3_FN_MOD2.
5404  */
5406 {
5407  uint32_t bypass_merge : 1; /* Bypass Merge */
5408  uint32_t : 31; /* *UNDEFINED* */
5409 };
5410 
5411 /* The typedef declaration for register ALT_L3_FN_MOD2. */
5412 typedef volatile struct ALT_L3_FN_MOD2_s ALT_L3_FN_MOD2_t;
5413 #endif /* __ASSEMBLY__ */
5414 
5415 /* The byte offset of the ALT_L3_FN_MOD2 register from the beginning of the component. */
5416 #define ALT_L3_FN_MOD2_OFST 0x24
5417 /* The address of the ALT_L3_FN_MOD2 register. */
5418 #define ALT_L3_FN_MOD2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_FN_MOD2_OFST))
5419 
5420 /*
5421  * Register : Functionality Modification AHB Register - fn_mod_ahb
5422  *
5423  * Controls how AHB-lite burst transactions are converted to AXI tranactions.
5424  *
5425  * Register Layout
5426  *
5427  * Bits | Access | Reset | Description
5428  * :-------|:-------|:------|:-------------------------
5429  * [0] | RW | 0x0 | Read Increment Override
5430  * [1] | RW | 0x0 | Write Increment Override
5431  * [31:2] | ??? | 0x0 | *UNDEFINED*
5432  *
5433  */
5434 /*
5435  * Field : Read Increment Override - rd_incr_override
5436  *
5437  * Controls how AHB-lite read burst transactions are converted to AXI tranactions.
5438  *
5439  * Field Enumeration Values:
5440  *
5441  * Enum | Value | Description
5442  * :---------------------------------------------|:------|:----------------------------------------------
5443  * ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_E_DEFAULT | 0x0 | The L3 Interconnect converts AHB-lite read
5444  * : | | bursts to AXI transactions in accordance with
5445  * : | | the default behavior as specified in the ARM
5446  * : | | NIC-301 documentation.
5447  * ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_E_SINGLES | 0x1 | The L3 Interconnect converts AHB-lite read
5448  * : | | bursts to AXI single transactions.
5449  *
5450  * Field Access Macros:
5451  *
5452  */
5453 /*
5454  * Enumerated value for register field ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE
5455  *
5456  * The L3 Interconnect converts AHB-lite read bursts to AXI transactions in
5457  * accordance with the default behavior as specified in the ARM NIC-301
5458  * documentation.
5459  */
5460 #define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_E_DEFAULT 0x0
5461 /*
5462  * Enumerated value for register field ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE
5463  *
5464  * The L3 Interconnect converts AHB-lite read bursts to AXI single transactions.
5465  */
5466 #define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_E_SINGLES 0x1
5467 
5468 /* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field. */
5469 #define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_LSB 0
5470 /* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field. */
5471 #define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_MSB 0
5472 /* The width in bits of the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field. */
5473 #define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_WIDTH 1
5474 /* The mask used to set the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field value. */
5475 #define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_SET_MSK 0x00000001
5476 /* The mask used to clear the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field value. */
5477 #define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_CLR_MSK 0xfffffffe
5478 /* The reset value of the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field. */
5479 #define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_RESET 0x0
5480 /* Extracts the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE field value from a register. */
5481 #define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_GET(value) (((value) & 0x00000001) >> 0)
5482 /* Produces a ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field value suitable for setting the register. */
5483 #define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_SET(value) (((value) << 0) & 0x00000001)
5484 
5485 /*
5486  * Field : Write Increment Override - wr_incr_override
5487  *
5488  * Controls how AHB-lite write burst transactions are converted to AXI tranactions.
5489  *
5490  * Field Enumeration Values:
5491  *
5492  * Enum | Value | Description
5493  * :---------------------------------------------|:------|:----------------------------------------------
5494  * ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_E_DEFAULT | 0x0 | The L3 Interconnect converts AHB-lite write
5495  * : | | bursts to AXI transactions in accordance with
5496  * : | | the default behavior as specified in the ARM
5497  * : | | NIC-301 documentation.
5498  * ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_E_SINGLES | 0x1 | The L3 Interconnect converts AHB-lite write
5499  * : | | bursts to AXI single transactions.
5500  *
5501  * Field Access Macros:
5502  *
5503  */
5504 /*
5505  * Enumerated value for register field ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE
5506  *
5507  * The L3 Interconnect converts AHB-lite write bursts to AXI transactions in
5508  * accordance with the default behavior as specified in the ARM NIC-301
5509  * documentation.
5510  */
5511 #define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_E_DEFAULT 0x0
5512 /*
5513  * Enumerated value for register field ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE
5514  *
5515  * The L3 Interconnect converts AHB-lite write bursts to AXI single transactions.
5516  */
5517 #define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_E_SINGLES 0x1
5518 
5519 /* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field. */
5520 #define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_LSB 1
5521 /* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field. */
5522 #define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_MSB 1
5523 /* The width in bits of the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field. */
5524 #define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_WIDTH 1
5525 /* The mask used to set the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field value. */
5526 #define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_SET_MSK 0x00000002
5527 /* The mask used to clear the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field value. */
5528 #define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_CLR_MSK 0xfffffffd
5529 /* The reset value of the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field. */
5530 #define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_RESET 0x0
5531 /* Extracts the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE field value from a register. */
5532 #define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_GET(value) (((value) & 0x00000002) >> 1)
5533 /* Produces a ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field value suitable for setting the register. */
5534 #define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_SET(value) (((value) << 1) & 0x00000002)
5535 
5536 #ifndef __ASSEMBLY__
5537 /*
5538  * WARNING: The C register and register group struct declarations are provided for
5539  * convenience and illustrative purposes. They should, however, be used with
5540  * caution as the C language standard provides no guarantees about the alignment or
5541  * atomicity of device memory accesses. The recommended practice for writing
5542  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5543  * alt_write_word() functions.
5544  *
5545  * The struct declaration for register ALT_L3_FN_MOD_AHB.
5546  */
5548 {
5549  uint32_t rd_incr_override : 1; /* Read Increment Override */
5550  uint32_t wr_incr_override : 1; /* Write Increment Override */
5551  uint32_t : 30; /* *UNDEFINED* */
5552 };
5553 
5554 /* The typedef declaration for register ALT_L3_FN_MOD_AHB. */
5555 typedef volatile struct ALT_L3_FN_MOD_AHB_s ALT_L3_FN_MOD_AHB_t;
5556 #endif /* __ASSEMBLY__ */
5557 
5558 /* The byte offset of the ALT_L3_FN_MOD_AHB register from the beginning of the component. */
5559 #define ALT_L3_FN_MOD_AHB_OFST 0x28
5560 /* The address of the ALT_L3_FN_MOD_AHB register. */
5561 #define ALT_L3_FN_MOD_AHB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_FN_MOD_AHB_OFST))
5562 
5563 /*
5564  * Register : Read Channel QoS Value - read_qos
5565  *
5566  * QoS (Quality of Service) value for the read channel.
5567  *
5568  * Register Layout
5569  *
5570  * Bits | Access | Reset | Description
5571  * :-------|:-------|:------|:------------
5572  * [3:0] | RW | 0x0 | Priority
5573  * [31:4] | ??? | 0x0 | *UNDEFINED*
5574  *
5575  */
5576 /*
5577  * Field : Priority - pri
5578  *
5579  * QoS (Quality of Service) value for the read channel. A higher value has a higher
5580  * priority.
5581  *
5582  * Field Access Macros:
5583  *
5584  */
5585 /* The Least Significant Bit (LSB) position of the ALT_L3_RD_QOS_PRI register field. */
5586 #define ALT_L3_RD_QOS_PRI_LSB 0
5587 /* The Most Significant Bit (MSB) position of the ALT_L3_RD_QOS_PRI register field. */
5588 #define ALT_L3_RD_QOS_PRI_MSB 3
5589 /* The width in bits of the ALT_L3_RD_QOS_PRI register field. */
5590 #define ALT_L3_RD_QOS_PRI_WIDTH 4
5591 /* The mask used to set the ALT_L3_RD_QOS_PRI register field value. */
5592 #define ALT_L3_RD_QOS_PRI_SET_MSK 0x0000000f
5593 /* The mask used to clear the ALT_L3_RD_QOS_PRI register field value. */
5594 #define ALT_L3_RD_QOS_PRI_CLR_MSK 0xfffffff0
5595 /* The reset value of the ALT_L3_RD_QOS_PRI register field. */
5596 #define ALT_L3_RD_QOS_PRI_RESET 0x0
5597 /* Extracts the ALT_L3_RD_QOS_PRI field value from a register. */
5598 #define ALT_L3_RD_QOS_PRI_GET(value) (((value) & 0x0000000f) >> 0)
5599 /* Produces a ALT_L3_RD_QOS_PRI register field value suitable for setting the register. */
5600 #define ALT_L3_RD_QOS_PRI_SET(value) (((value) << 0) & 0x0000000f)
5601 
5602 #ifndef __ASSEMBLY__
5603 /*
5604  * WARNING: The C register and register group struct declarations are provided for
5605  * convenience and illustrative purposes. They should, however, be used with
5606  * caution as the C language standard provides no guarantees about the alignment or
5607  * atomicity of device memory accesses. The recommended practice for writing
5608  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5609  * alt_write_word() functions.
5610  *
5611  * The struct declaration for register ALT_L3_RD_QOS.
5612  */
5614 {
5615  uint32_t pri : 4; /* Priority */
5616  uint32_t : 28; /* *UNDEFINED* */
5617 };
5618 
5619 /* The typedef declaration for register ALT_L3_RD_QOS. */
5620 typedef volatile struct ALT_L3_RD_QOS_s ALT_L3_RD_QOS_t;
5621 #endif /* __ASSEMBLY__ */
5622 
5623 /* The byte offset of the ALT_L3_RD_QOS register from the beginning of the component. */
5624 #define ALT_L3_RD_QOS_OFST 0x100
5625 /* The address of the ALT_L3_RD_QOS register. */
5626 #define ALT_L3_RD_QOS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_RD_QOS_OFST))
5627 
5628 /*
5629  * Register : Write Channel QoS Value - write_qos
5630  *
5631  * QoS (Quality of Service) value for the write channel.
5632  *
5633  * Register Layout
5634  *
5635  * Bits | Access | Reset | Description
5636  * :-------|:-------|:------|:------------
5637  * [3:0] | RW | 0x0 | Priority
5638  * [31:4] | ??? | 0x0 | *UNDEFINED*
5639  *
5640  */
5641 /*
5642  * Field : Priority - pri
5643  *
5644  * QoS (Quality of Service) value for the write channel. A higher value has a
5645  * higher priority.
5646  *
5647  * Field Access Macros:
5648  *
5649  */
5650 /* The Least Significant Bit (LSB) position of the ALT_L3_WR_QOS_PRI register field. */
5651 #define ALT_L3_WR_QOS_PRI_LSB 0
5652 /* The Most Significant Bit (MSB) position of the ALT_L3_WR_QOS_PRI register field. */
5653 #define ALT_L3_WR_QOS_PRI_MSB 3
5654 /* The width in bits of the ALT_L3_WR_QOS_PRI register field. */
5655 #define ALT_L3_WR_QOS_PRI_WIDTH 4
5656 /* The mask used to set the ALT_L3_WR_QOS_PRI register field value. */
5657 #define ALT_L3_WR_QOS_PRI_SET_MSK 0x0000000f
5658 /* The mask used to clear the ALT_L3_WR_QOS_PRI register field value. */
5659 #define ALT_L3_WR_QOS_PRI_CLR_MSK 0xfffffff0
5660 /* The reset value of the ALT_L3_WR_QOS_PRI register field. */
5661 #define ALT_L3_WR_QOS_PRI_RESET 0x0
5662 /* Extracts the ALT_L3_WR_QOS_PRI field value from a register. */
5663 #define ALT_L3_WR_QOS_PRI_GET(value) (((value) & 0x0000000f) >> 0)
5664 /* Produces a ALT_L3_WR_QOS_PRI register field value suitable for setting the register. */
5665 #define ALT_L3_WR_QOS_PRI_SET(value) (((value) << 0) & 0x0000000f)
5666 
5667 #ifndef __ASSEMBLY__
5668 /*
5669  * WARNING: The C register and register group struct declarations are provided for
5670  * convenience and illustrative purposes. They should, however, be used with
5671  * caution as the C language standard provides no guarantees about the alignment or
5672  * atomicity of device memory accesses. The recommended practice for writing
5673  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5674  * alt_write_word() functions.
5675  *
5676  * The struct declaration for register ALT_L3_WR_QOS.
5677  */
5679 {
5680  uint32_t pri : 4; /* Priority */
5681  uint32_t : 28; /* *UNDEFINED* */
5682 };
5683 
5684 /* The typedef declaration for register ALT_L3_WR_QOS. */
5685 typedef volatile struct ALT_L3_WR_QOS_s ALT_L3_WR_QOS_t;
5686 #endif /* __ASSEMBLY__ */
5687 
5688 /* The byte offset of the ALT_L3_WR_QOS register from the beginning of the component. */
5689 #define ALT_L3_WR_QOS_OFST 0x104
5690 /* The address of the ALT_L3_WR_QOS register. */
5691 #define ALT_L3_WR_QOS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_WR_QOS_OFST))
5692 
5693 #ifndef __ASSEMBLY__
5694 /*
5695  * WARNING: The C register and register group struct declarations are provided for
5696  * convenience and illustrative purposes. They should, however, be used with
5697  * caution as the C language standard provides no guarantees about the alignment or
5698  * atomicity of device memory accesses. The recommended practice for writing
5699  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5700  * alt_write_word() functions.
5701  *
5702  * The struct declaration for register group ALT_L3_SLV_DAP.
5703  */
5705 {
5706  volatile uint32_t _pad_0x0_0x23[9]; /* *UNDEFINED* */
5707  volatile ALT_L3_FN_MOD2_t fn_mod2; /* ALT_L3_FN_MOD2 */
5708  volatile ALT_L3_FN_MOD_AHB_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */
5709  volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */
5710  volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */
5711  volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */
5712  volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
5713 };
5714 
5715 /* The typedef declaration for register group ALT_L3_SLV_DAP. */
5716 typedef volatile struct ALT_L3_SLV_DAP_s ALT_L3_SLV_DAP_t;
5717 /* The struct declaration for the raw register contents of register group ALT_L3_SLV_DAP. */
5719 {
5720  volatile uint32_t _pad_0x0_0x23[9]; /* *UNDEFINED* */
5721  volatile uint32_t fn_mod2; /* ALT_L3_FN_MOD2 */
5722  volatile uint32_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */
5723  volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */
5724  volatile uint32_t read_qos; /* ALT_L3_RD_QOS */
5725  volatile uint32_t write_qos; /* ALT_L3_WR_QOS */
5726  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
5727 };
5728 
5729 /* The typedef declaration for the raw register contents of register group ALT_L3_SLV_DAP. */
5730 typedef volatile struct ALT_L3_SLV_DAP_raw_s ALT_L3_SLV_DAP_raw_t;
5731 #endif /* __ASSEMBLY__ */
5732 
5733 
5734 /*
5735  * Register Group : MPU - ALT_L3_SLV_MPU
5736  * MPU
5737  *
5738  * Registers associated with the MPU slave interface. This slave is used by the MPU
5739  * to access slaves attached to the L3/L4 Interconnect.
5740  *
5741  */
5742 #ifndef __ASSEMBLY__
5743 /*
5744  * WARNING: The C register and register group struct declarations are provided for
5745  * convenience and illustrative purposes. They should, however, be used with
5746  * caution as the C language standard provides no guarantees about the alignment or
5747  * atomicity of device memory accesses. The recommended practice for writing
5748  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5749  * alt_write_word() functions.
5750  *
5751  * The struct declaration for register group ALT_L3_SLV_MPU.
5752  */
5754 {
5755  volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */
5756  volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */
5757  volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */
5758  volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
5759 };
5760 
5761 /* The typedef declaration for register group ALT_L3_SLV_MPU. */
5762 typedef volatile struct ALT_L3_SLV_MPU_s ALT_L3_SLV_MPU_t;
5763 /* The struct declaration for the raw register contents of register group ALT_L3_SLV_MPU. */
5765 {
5766  volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */
5767  volatile uint32_t read_qos; /* ALT_L3_RD_QOS */
5768  volatile uint32_t write_qos; /* ALT_L3_WR_QOS */
5769  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
5770 };
5771 
5772 /* The typedef declaration for the raw register contents of register group ALT_L3_SLV_MPU. */
5773 typedef volatile struct ALT_L3_SLV_MPU_raw_s ALT_L3_SLV_MPU_raw_t;
5774 #endif /* __ASSEMBLY__ */
5775 
5776 
5777 /*
5778  * Register Group : SDMMC - ALT_L3_SLV_SDMMC
5779  * SDMMC
5780  *
5781  * Registers associated with the SDMMC slave interface. This slave is used by the
5782  * DMA controller built into the SDMMC to access slaves attached to the L3/L4
5783  * Interconnect.
5784  *
5785  */
5786 #ifndef __ASSEMBLY__
5787 /*
5788  * WARNING: The C register and register group struct declarations are provided for
5789  * convenience and illustrative purposes. They should, however, be used with
5790  * caution as the C language standard provides no guarantees about the alignment or
5791  * atomicity of device memory accesses. The recommended practice for writing
5792  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5793  * alt_write_word() functions.
5794  *
5795  * The struct declaration for register group ALT_L3_SLV_SDMMC.
5796  */
5798 {
5799  volatile uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */
5800  volatile ALT_L3_FN_MOD_AHB_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */
5801  volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */
5802  volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */
5803  volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */
5804  volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
5805 };
5806 
5807 /* The typedef declaration for register group ALT_L3_SLV_SDMMC. */
5808 typedef volatile struct ALT_L3_SLV_SDMMC_s ALT_L3_SLV_SDMMC_t;
5809 /* The struct declaration for the raw register contents of register group ALT_L3_SLV_SDMMC. */
5811 {
5812  volatile uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */
5813  volatile uint32_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */
5814  volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */
5815  volatile uint32_t read_qos; /* ALT_L3_RD_QOS */
5816  volatile uint32_t write_qos; /* ALT_L3_WR_QOS */
5817  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
5818 };
5819 
5820 /* The typedef declaration for the raw register contents of register group ALT_L3_SLV_SDMMC. */
5821 typedef volatile struct ALT_L3_SLV_SDMMC_raw_s ALT_L3_SLV_SDMMC_raw_t;
5822 #endif /* __ASSEMBLY__ */
5823 
5824 
5825 /*
5826  * Register Group : DMA - ALT_L3_SLV_DMA
5827  * DMA
5828  *
5829  * Registers associated with the DMA Controller slave interface. This slave is used
5830  * by the DMA Controller to access slaves attached to the L3/L4 Interconnect.
5831  *
5832  */
5833 #ifndef __ASSEMBLY__
5834 /*
5835  * WARNING: The C register and register group struct declarations are provided for
5836  * convenience and illustrative purposes. They should, however, be used with
5837  * caution as the C language standard provides no guarantees about the alignment or
5838  * atomicity of device memory accesses. The recommended practice for writing
5839  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5840  * alt_write_word() functions.
5841  *
5842  * The struct declaration for register group ALT_L3_SLV_DMA.
5843  */
5845 {
5846  volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */
5847  volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */
5848  volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */
5849  volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
5850 };
5851 
5852 /* The typedef declaration for register group ALT_L3_SLV_DMA. */
5853 typedef volatile struct ALT_L3_SLV_DMA_s ALT_L3_SLV_DMA_t;
5854 /* The struct declaration for the raw register contents of register group ALT_L3_SLV_DMA. */
5856 {
5857  volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */
5858  volatile uint32_t read_qos; /* ALT_L3_RD_QOS */
5859  volatile uint32_t write_qos; /* ALT_L3_WR_QOS */
5860  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
5861 };
5862 
5863 /* The typedef declaration for the raw register contents of register group ALT_L3_SLV_DMA. */
5864 typedef volatile struct ALT_L3_SLV_DMA_raw_s ALT_L3_SLV_DMA_raw_t;
5865 #endif /* __ASSEMBLY__ */
5866 
5867 
5868 /*
5869  * Register Group : FPGA2HPS - ALT_L3_SLV_F2H
5870  * FPGA2HPS
5871  *
5872  * Registers associated with the FPGA2HPS AXI Bridge slave interface. This slave is
5873  * used by the FPGA2HPS AXI Bridge to access slaves attached to the L3/L4
5874  * Interconnect.
5875  *
5876  */
5877 #ifndef __ASSEMBLY__
5878 /*
5879  * WARNING: The C register and register group struct declarations are provided for
5880  * convenience and illustrative purposes. They should, however, be used with
5881  * caution as the C language standard provides no guarantees about the alignment or
5882  * atomicity of device memory accesses. The recommended practice for writing
5883  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5884  * alt_write_word() functions.
5885  *
5886  * The struct declaration for register group ALT_L3_SLV_F2H.
5887  */
5889 {
5890  volatile uint32_t _pad_0x0_0x3f[16]; /* *UNDEFINED* */
5891  volatile ALT_L3_WR_TIDEMARK_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */
5892  volatile uint32_t _pad_0x44_0xff[47]; /* *UNDEFINED* */
5893  volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */
5894  volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */
5895  volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
5896 };
5897 
5898 /* The typedef declaration for register group ALT_L3_SLV_F2H. */
5899 typedef volatile struct ALT_L3_SLV_F2H_s ALT_L3_SLV_F2H_t;
5900 /* The struct declaration for the raw register contents of register group ALT_L3_SLV_F2H. */
5902 {
5903  volatile uint32_t _pad_0x0_0x3f[16]; /* *UNDEFINED* */
5904  volatile uint32_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */
5905  volatile uint32_t _pad_0x44_0xff[47]; /* *UNDEFINED* */
5906  volatile uint32_t read_qos; /* ALT_L3_RD_QOS */
5907  volatile uint32_t write_qos; /* ALT_L3_WR_QOS */
5908  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
5909 };
5910 
5911 /* The typedef declaration for the raw register contents of register group ALT_L3_SLV_F2H. */
5912 typedef volatile struct ALT_L3_SLV_F2H_raw_s ALT_L3_SLV_F2H_raw_t;
5913 #endif /* __ASSEMBLY__ */
5914 
5915 
5916 /*
5917  * Register Group : ETR - ALT_L3_SLV_ETR
5918  * ETR
5919  *
5920  * Registers associated with the ETR (TMC) slave interface. This slave is used by
5921  * the ETR to access slaves attached to the L3/L4 Interconnect.
5922  *
5923  */
5924 #ifndef __ASSEMBLY__
5925 /*
5926  * WARNING: The C register and register group struct declarations are provided for
5927  * convenience and illustrative purposes. They should, however, be used with
5928  * caution as the C language standard provides no guarantees about the alignment or
5929  * atomicity of device memory accesses. The recommended practice for writing
5930  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5931  * alt_write_word() functions.
5932  *
5933  * The struct declaration for register group ALT_L3_SLV_ETR.
5934  */
5936 {
5937  volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */
5938  volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */
5939  volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */
5940  volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
5941 };
5942 
5943 /* The typedef declaration for register group ALT_L3_SLV_ETR. */
5944 typedef volatile struct ALT_L3_SLV_ETR_s ALT_L3_SLV_ETR_t;
5945 /* The struct declaration for the raw register contents of register group ALT_L3_SLV_ETR. */
5947 {
5948  volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */
5949  volatile uint32_t read_qos; /* ALT_L3_RD_QOS */
5950  volatile uint32_t write_qos; /* ALT_L3_WR_QOS */
5951  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
5952 };
5953 
5954 /* The typedef declaration for the raw register contents of register group ALT_L3_SLV_ETR. */
5955 typedef volatile struct ALT_L3_SLV_ETR_raw_s ALT_L3_SLV_ETR_raw_t;
5956 #endif /* __ASSEMBLY__ */
5957 
5958 
5959 /*
5960  * Register Group : EMAC0 - ALT_L3_SLV_EMAC0
5961  * EMAC0
5962  *
5963  * Registers associated with the EMAC0 slave interface. This slave is used by the
5964  * DMA controller built into the EMAC0 to access slaves attached to the L3/L4
5965  * Interconnect.
5966  *
5967  */
5968 #ifndef __ASSEMBLY__
5969 /*
5970  * WARNING: The C register and register group struct declarations are provided for
5971  * convenience and illustrative purposes. They should, however, be used with
5972  * caution as the C language standard provides no guarantees about the alignment or
5973  * atomicity of device memory accesses. The recommended practice for writing
5974  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5975  * alt_write_word() functions.
5976  *
5977  * The struct declaration for register group ALT_L3_SLV_EMAC0.
5978  */
5980 {
5981  volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */
5982  volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */
5983  volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */
5984  volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
5985 };
5986 
5987 /* The typedef declaration for register group ALT_L3_SLV_EMAC0. */
5988 typedef volatile struct ALT_L3_SLV_EMAC0_s ALT_L3_SLV_EMAC0_t;
5989 /* The struct declaration for the raw register contents of register group ALT_L3_SLV_EMAC0. */
5991 {
5992  volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */
5993  volatile uint32_t read_qos; /* ALT_L3_RD_QOS */
5994  volatile uint32_t write_qos; /* ALT_L3_WR_QOS */
5995  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
5996 };
5997 
5998 /* The typedef declaration for the raw register contents of register group ALT_L3_SLV_EMAC0. */
5999 typedef volatile struct ALT_L3_SLV_EMAC0_raw_s ALT_L3_SLV_EMAC0_raw_t;
6000 #endif /* __ASSEMBLY__ */
6001 
6002 
6003 /*
6004  * Register Group : EMAC1 - ALT_L3_SLV_EMAC1
6005  * EMAC1
6006  *
6007  * Registers associated with the EMAC1 slave interface. This slave is used by the
6008  * DMA controller built into the EMAC1 to access slaves attached to the L3/L4
6009  * Interconnect.
6010  *
6011  */
6012 #ifndef __ASSEMBLY__
6013 /*
6014  * WARNING: The C register and register group struct declarations are provided for
6015  * convenience and illustrative purposes. They should, however, be used with
6016  * caution as the C language standard provides no guarantees about the alignment or
6017  * atomicity of device memory accesses. The recommended practice for writing
6018  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6019  * alt_write_word() functions.
6020  *
6021  * The struct declaration for register group ALT_L3_SLV_EMAC1.
6022  */
6024 {
6025  volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */
6026  volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */
6027  volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */
6028  volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
6029 };
6030 
6031 /* The typedef declaration for register group ALT_L3_SLV_EMAC1. */
6032 typedef volatile struct ALT_L3_SLV_EMAC1_s ALT_L3_SLV_EMAC1_t;
6033 /* The struct declaration for the raw register contents of register group ALT_L3_SLV_EMAC1. */
6035 {
6036  volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */
6037  volatile uint32_t read_qos; /* ALT_L3_RD_QOS */
6038  volatile uint32_t write_qos; /* ALT_L3_WR_QOS */
6039  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
6040 };
6041 
6042 /* The typedef declaration for the raw register contents of register group ALT_L3_SLV_EMAC1. */
6043 typedef volatile struct ALT_L3_SLV_EMAC1_raw_s ALT_L3_SLV_EMAC1_raw_t;
6044 #endif /* __ASSEMBLY__ */
6045 
6046 
6047 /*
6048  * Register Group : USB0 - ALT_L3_SLV_USB0
6049  * USB0
6050  *
6051  * Registers associated with the USB0 slave interface. This slave is used by the
6052  * DMA controller built into the USB0 to access slaves attached to the L3/L4
6053  * Interconnect.
6054  *
6055  */
6056 #ifndef __ASSEMBLY__
6057 /*
6058  * WARNING: The C register and register group struct declarations are provided for
6059  * convenience and illustrative purposes. They should, however, be used with
6060  * caution as the C language standard provides no guarantees about the alignment or
6061  * atomicity of device memory accesses. The recommended practice for writing
6062  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6063  * alt_write_word() functions.
6064  *
6065  * The struct declaration for register group ALT_L3_SLV_USB0.
6066  */
6068 {
6069  volatile uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */
6070  volatile ALT_L3_FN_MOD_AHB_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */
6071  volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */
6072  volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */
6073  volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */
6074  volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
6075 };
6076 
6077 /* The typedef declaration for register group ALT_L3_SLV_USB0. */
6078 typedef volatile struct ALT_L3_SLV_USB0_s ALT_L3_SLV_USB0_t;
6079 /* The struct declaration for the raw register contents of register group ALT_L3_SLV_USB0. */
6081 {
6082  volatile uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */
6083  volatile uint32_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */
6084  volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */
6085  volatile uint32_t read_qos; /* ALT_L3_RD_QOS */
6086  volatile uint32_t write_qos; /* ALT_L3_WR_QOS */
6087  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
6088 };
6089 
6090 /* The typedef declaration for the raw register contents of register group ALT_L3_SLV_USB0. */
6091 typedef volatile struct ALT_L3_SLV_USB0_raw_s ALT_L3_SLV_USB0_raw_t;
6092 #endif /* __ASSEMBLY__ */
6093 
6094 
6095 /*
6096  * Register Group : NAND - ALT_L3_SLV_NAND
6097  * NAND
6098  *
6099  * Registers associated with the NAND slave interface. This slave is used by the
6100  * DMA controller built into the NAND flash controller to access slaves attached to
6101  * the L3/L4 Interconnect.
6102  *
6103  */
6104 #ifndef __ASSEMBLY__
6105 /*
6106  * WARNING: The C register and register group struct declarations are provided for
6107  * convenience and illustrative purposes. They should, however, be used with
6108  * caution as the C language standard provides no guarantees about the alignment or
6109  * atomicity of device memory accesses. The recommended practice for writing
6110  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6111  * alt_write_word() functions.
6112  *
6113  * The struct declaration for register group ALT_L3_SLV_NAND.
6114  */
6116 {
6117  volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */
6118  volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */
6119  volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */
6120  volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
6121 };
6122 
6123 /* The typedef declaration for register group ALT_L3_SLV_NAND. */
6124 typedef volatile struct ALT_L3_SLV_NAND_s ALT_L3_SLV_NAND_t;
6125 /* The struct declaration for the raw register contents of register group ALT_L3_SLV_NAND. */
6127 {
6128  volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */
6129  volatile uint32_t read_qos; /* ALT_L3_RD_QOS */
6130  volatile uint32_t write_qos; /* ALT_L3_WR_QOS */
6131  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
6132 };
6133 
6134 /* The typedef declaration for the raw register contents of register group ALT_L3_SLV_NAND. */
6135 typedef volatile struct ALT_L3_SLV_NAND_raw_s ALT_L3_SLV_NAND_raw_t;
6136 #endif /* __ASSEMBLY__ */
6137 
6138 
6139 /*
6140  * Register Group : USB1 - ALT_L3_SLV_USB1
6141  * USB1
6142  *
6143  * Registers associated with the USB1 slave interface. This slave is used by the
6144  * DMA controller built into the USB1 to access slaves attached to the L3/L4
6145  * Interconnect.
6146  *
6147  */
6148 #ifndef __ASSEMBLY__
6149 /*
6150  * WARNING: The C register and register group struct declarations are provided for
6151  * convenience and illustrative purposes. They should, however, be used with
6152  * caution as the C language standard provides no guarantees about the alignment or
6153  * atomicity of device memory accesses. The recommended practice for writing
6154  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6155  * alt_write_word() functions.
6156  *
6157  * The struct declaration for register group ALT_L3_SLV_USB1.
6158  */
6160 {
6161  volatile uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */
6162  volatile ALT_L3_FN_MOD_AHB_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */
6163  volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */
6164  volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */
6165  volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */
6166  volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
6167 };
6168 
6169 /* The typedef declaration for register group ALT_L3_SLV_USB1. */
6170 typedef volatile struct ALT_L3_SLV_USB1_s ALT_L3_SLV_USB1_t;
6171 /* The struct declaration for the raw register contents of register group ALT_L3_SLV_USB1. */
6173 {
6174  volatile uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */
6175  volatile uint32_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */
6176  volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */
6177  volatile uint32_t read_qos; /* ALT_L3_RD_QOS */
6178  volatile uint32_t write_qos; /* ALT_L3_WR_QOS */
6179  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
6180 };
6181 
6182 /* The typedef declaration for the raw register contents of register group ALT_L3_SLV_USB1. */
6183 typedef volatile struct ALT_L3_SLV_USB1_raw_s ALT_L3_SLV_USB1_raw_t;
6184 #endif /* __ASSEMBLY__ */
6185 
6186 
6187 #ifndef __ASSEMBLY__
6188 /*
6189  * WARNING: The C register and register group struct declarations are provided for
6190  * convenience and illustrative purposes. They should, however, be used with
6191  * caution as the C language standard provides no guarantees about the alignment or
6192  * atomicity of device memory accesses. The recommended practice for writing
6193  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6194  * alt_write_word() functions.
6195  *
6196  * The struct declaration for register group ALT_L3_SLVGRP.
6197  */
6199 {
6200  volatile ALT_L3_SLV_DAP_t slavegrp_dap; /* ALT_L3_SLV_DAP */
6201  volatile uint32_t _pad_0x10c_0xfff[957]; /* *UNDEFINED* */
6202  volatile ALT_L3_SLV_MPU_t slavegrp_mpu; /* ALT_L3_SLV_MPU */
6203  volatile uint32_t _pad_0x110c_0x1fff[957]; /* *UNDEFINED* */
6204  volatile ALT_L3_SLV_SDMMC_t slavegrp_sdmmc; /* ALT_L3_SLV_SDMMC */
6205  volatile uint32_t _pad_0x210c_0x2fff[957]; /* *UNDEFINED* */
6206  volatile ALT_L3_SLV_DMA_t slavegrp_dma; /* ALT_L3_SLV_DMA */
6207  volatile uint32_t _pad_0x310c_0x3fff[957]; /* *UNDEFINED* */
6208  volatile ALT_L3_SLV_F2H_t slavegrp_fpga2hps; /* ALT_L3_SLV_F2H */
6209  volatile uint32_t _pad_0x410c_0x4fff[957]; /* *UNDEFINED* */
6210  volatile ALT_L3_SLV_ETR_t slavegrp_etr; /* ALT_L3_SLV_ETR */
6211  volatile uint32_t _pad_0x510c_0x5fff[957]; /* *UNDEFINED* */
6212  volatile ALT_L3_SLV_EMAC0_t slavegrp_emac0; /* ALT_L3_SLV_EMAC0 */
6213  volatile uint32_t _pad_0x610c_0x6fff[957]; /* *UNDEFINED* */
6214  volatile ALT_L3_SLV_EMAC1_t slavegrp_emac1; /* ALT_L3_SLV_EMAC1 */
6215  volatile uint32_t _pad_0x710c_0x7fff[957]; /* *UNDEFINED* */
6216  volatile ALT_L3_SLV_USB0_t slavegrp_usb0; /* ALT_L3_SLV_USB0 */
6217  volatile uint32_t _pad_0x810c_0x8fff[957]; /* *UNDEFINED* */
6218  volatile ALT_L3_SLV_NAND_t slavegrp_nand; /* ALT_L3_SLV_NAND */
6219  volatile uint32_t _pad_0x910c_0x9fff[957]; /* *UNDEFINED* */
6220  volatile ALT_L3_SLV_USB1_t slavegrp_usb1; /* ALT_L3_SLV_USB1 */
6221 };
6222 
6223 /* The typedef declaration for register group ALT_L3_SLVGRP. */
6224 typedef volatile struct ALT_L3_SLVGRP_s ALT_L3_SLVGRP_t;
6225 /* The struct declaration for the raw register contents of register group ALT_L3_SLVGRP. */
6227 {
6228  volatile ALT_L3_SLV_DAP_raw_t slavegrp_dap; /* ALT_L3_SLV_DAP */
6229  volatile uint32_t _pad_0x10c_0xfff[957]; /* *UNDEFINED* */
6230  volatile ALT_L3_SLV_MPU_raw_t slavegrp_mpu; /* ALT_L3_SLV_MPU */
6231  volatile uint32_t _pad_0x110c_0x1fff[957]; /* *UNDEFINED* */
6232  volatile ALT_L3_SLV_SDMMC_raw_t slavegrp_sdmmc; /* ALT_L3_SLV_SDMMC */
6233  volatile uint32_t _pad_0x210c_0x2fff[957]; /* *UNDEFINED* */
6234  volatile ALT_L3_SLV_DMA_raw_t slavegrp_dma; /* ALT_L3_SLV_DMA */
6235  volatile uint32_t _pad_0x310c_0x3fff[957]; /* *UNDEFINED* */
6236  volatile ALT_L3_SLV_F2H_raw_t slavegrp_fpga2hps; /* ALT_L3_SLV_F2H */
6237  volatile uint32_t _pad_0x410c_0x4fff[957]; /* *UNDEFINED* */
6238  volatile ALT_L3_SLV_ETR_raw_t slavegrp_etr; /* ALT_L3_SLV_ETR */
6239  volatile uint32_t _pad_0x510c_0x5fff[957]; /* *UNDEFINED* */
6240  volatile ALT_L3_SLV_EMAC0_raw_t slavegrp_emac0; /* ALT_L3_SLV_EMAC0 */
6241  volatile uint32_t _pad_0x610c_0x6fff[957]; /* *UNDEFINED* */
6242  volatile ALT_L3_SLV_EMAC1_raw_t slavegrp_emac1; /* ALT_L3_SLV_EMAC1 */
6243  volatile uint32_t _pad_0x710c_0x7fff[957]; /* *UNDEFINED* */
6244  volatile ALT_L3_SLV_USB0_raw_t slavegrp_usb0; /* ALT_L3_SLV_USB0 */
6245  volatile uint32_t _pad_0x810c_0x8fff[957]; /* *UNDEFINED* */
6246  volatile ALT_L3_SLV_NAND_raw_t slavegrp_nand; /* ALT_L3_SLV_NAND */
6247  volatile uint32_t _pad_0x910c_0x9fff[957]; /* *UNDEFINED* */
6248  volatile ALT_L3_SLV_USB1_raw_t slavegrp_usb1; /* ALT_L3_SLV_USB1 */
6249 };
6250 
6251 /* The typedef declaration for the raw register contents of register group ALT_L3_SLVGRP. */
6252 typedef volatile struct ALT_L3_SLVGRP_raw_s ALT_L3_SLVGRP_raw_t;
6253 #endif /* __ASSEMBLY__ */
6254 
6255 
6256 #ifndef __ASSEMBLY__
6257 /*
6258  * WARNING: The C register and register group struct declarations are provided for
6259  * convenience and illustrative purposes. They should, however, be used with
6260  * caution as the C language standard provides no guarantees about the alignment or
6261  * atomicity of device memory accesses. The recommended practice for writing
6262  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6263  * alt_write_word() functions.
6264  *
6265  * The struct declaration for register group ALT_L3.
6266  */
6267 struct ALT_L3_s
6268 {
6269  volatile ALT_L3_REMAP_t remap; /* ALT_L3_REMAP */
6270  volatile uint32_t _pad_0x4_0x7; /* *UNDEFINED* */
6271  volatile ALT_L3_SECGRP_t secgrp; /* ALT_L3_SECGRP */
6272  volatile uint32_t _pad_0xa4_0xfff[983]; /* *UNDEFINED* */
6273  volatile ALT_L3_IDGRP_t idgrp; /* ALT_L3_IDGRP */
6274  volatile ALT_L3_MSTGRP_t mastergrp; /* ALT_L3_MSTGRP */
6275  volatile uint32_t _pad_0x2710c_0x41fff[27581]; /* *UNDEFINED* */
6276  volatile ALT_L3_SLVGRP_t slavegrp; /* ALT_L3_SLVGRP */
6277  volatile uint32_t _pad_0x4c10c_0x80000[53181]; /* *UNDEFINED* */
6278 };
6279 
6280 /* The typedef declaration for register group ALT_L3. */
6281 typedef volatile struct ALT_L3_s ALT_L3_t;
6282 /* The struct declaration for the raw register contents of register group ALT_L3. */
6284 {
6285  volatile uint32_t remap; /* ALT_L3_REMAP */
6286  volatile uint32_t _pad_0x4_0x7; /* *UNDEFINED* */
6287  volatile ALT_L3_SECGRP_raw_t secgrp; /* ALT_L3_SECGRP */
6288  volatile uint32_t _pad_0xa4_0xfff[983]; /* *UNDEFINED* */
6289  volatile ALT_L3_IDGRP_raw_t idgrp; /* ALT_L3_IDGRP */
6290  volatile ALT_L3_MSTGRP_raw_t mastergrp; /* ALT_L3_MSTGRP */
6291  volatile uint32_t _pad_0x2710c_0x41fff[27581]; /* *UNDEFINED* */
6292  volatile ALT_L3_SLVGRP_raw_t slavegrp; /* ALT_L3_SLVGRP */
6293  volatile uint32_t _pad_0x4c10c_0x80000[53181]; /* *UNDEFINED* */
6294 };
6295 
6296 /* The typedef declaration for the raw register contents of register group ALT_L3. */
6297 typedef volatile struct ALT_L3_raw_s ALT_L3_raw_t;
6298 #endif /* __ASSEMBLY__ */
6299 
6300 
6301 #ifdef __cplusplus
6302 }
6303 #endif /* __cplusplus */
6304 #endif /* __ALTERA_ALT_L3_H__ */
6305 
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