39 #ifndef __ALTERA_ALT_L3_H__ 40 #define __ALTERA_ALT_L3_H__ 105 #define ALT_L3_REMAP_MPUZERO_E_BOOTROM 0x0 113 #define ALT_L3_REMAP_MPUZERO_E_OCRAM 0x1 116 #define ALT_L3_REMAP_MPUZERO_LSB 0 118 #define ALT_L3_REMAP_MPUZERO_MSB 0 120 #define ALT_L3_REMAP_MPUZERO_WIDTH 1 122 #define ALT_L3_REMAP_MPUZERO_SET_MSK 0x00000001 124 #define ALT_L3_REMAP_MPUZERO_CLR_MSK 0xfffffffe 126 #define ALT_L3_REMAP_MPUZERO_RESET 0x0 128 #define ALT_L3_REMAP_MPUZERO_GET(value) (((value) & 0x00000001) >> 0) 130 #define ALT_L3_REMAP_MPUZERO_SET(value) (((value) << 0) & 0x00000001) 160 #define ALT_L3_REMAP_NONMPUZERO_E_SDRAM 0x0 168 #define ALT_L3_REMAP_NONMPUZERO_E_OCRAM 0x1 171 #define ALT_L3_REMAP_NONMPUZERO_LSB 1 173 #define ALT_L3_REMAP_NONMPUZERO_MSB 1 175 #define ALT_L3_REMAP_NONMPUZERO_WIDTH 1 177 #define ALT_L3_REMAP_NONMPUZERO_SET_MSK 0x00000002 179 #define ALT_L3_REMAP_NONMPUZERO_CLR_MSK 0xfffffffd 181 #define ALT_L3_REMAP_NONMPUZERO_RESET 0x0 183 #define ALT_L3_REMAP_NONMPUZERO_GET(value) (((value) & 0x00000002) >> 1) 185 #define ALT_L3_REMAP_NONMPUZERO_SET(value) (((value) << 1) & 0x00000002) 211 #define ALT_L3_REMAP_H2F_E_INVISIBLE 0x0 217 #define ALT_L3_REMAP_H2F_E_VISIBLE 0x1 220 #define ALT_L3_REMAP_H2F_LSB 3 222 #define ALT_L3_REMAP_H2F_MSB 3 224 #define ALT_L3_REMAP_H2F_WIDTH 1 226 #define ALT_L3_REMAP_H2F_SET_MSK 0x00000008 228 #define ALT_L3_REMAP_H2F_CLR_MSK 0xfffffff7 230 #define ALT_L3_REMAP_H2F_RESET 0x0 232 #define ALT_L3_REMAP_H2F_GET(value) (((value) & 0x00000008) >> 3) 234 #define ALT_L3_REMAP_H2F_SET(value) (((value) << 3) & 0x00000008) 261 #define ALT_L3_REMAP_LWH2F_E_INVISIBLE 0x0 267 #define ALT_L3_REMAP_LWH2F_E_VISIBLE 0x1 270 #define ALT_L3_REMAP_LWH2F_LSB 4 272 #define ALT_L3_REMAP_LWH2F_MSB 4 274 #define ALT_L3_REMAP_LWH2F_WIDTH 1 276 #define ALT_L3_REMAP_LWH2F_SET_MSK 0x00000010 278 #define ALT_L3_REMAP_LWH2F_CLR_MSK 0xffffffef 280 #define ALT_L3_REMAP_LWH2F_RESET 0x0 282 #define ALT_L3_REMAP_LWH2F_GET(value) (((value) & 0x00000010) >> 4) 284 #define ALT_L3_REMAP_LWH2F_SET(value) (((value) << 4) & 0x00000010) 299 uint32_t mpuzero : 1;
300 uint32_t nonmpuzero : 1;
302 uint32_t hps2fpga : 1;
303 uint32_t lwhps2fpga : 1;
312 #define ALT_L3_REMAP_OFST 0x0 359 #define ALT_L3_SEC_L4MAIN_SPIS0_E_SECURE 0x0 365 #define ALT_L3_SEC_L4MAIN_SPIS0_E_NONSECURE 0x1 368 #define ALT_L3_SEC_L4MAIN_SPIS0_LSB 0 370 #define ALT_L3_SEC_L4MAIN_SPIS0_MSB 0 372 #define ALT_L3_SEC_L4MAIN_SPIS0_WIDTH 1 374 #define ALT_L3_SEC_L4MAIN_SPIS0_SET_MSK 0x00000001 376 #define ALT_L3_SEC_L4MAIN_SPIS0_CLR_MSK 0xfffffffe 378 #define ALT_L3_SEC_L4MAIN_SPIS0_RESET 0x0 380 #define ALT_L3_SEC_L4MAIN_SPIS0_GET(value) (((value) & 0x00000001) >> 0) 382 #define ALT_L3_SEC_L4MAIN_SPIS0_SET(value) (((value) << 0) & 0x00000001) 406 #define ALT_L3_SEC_L4MAIN_SPIS1_E_SECURE 0x0 412 #define ALT_L3_SEC_L4MAIN_SPIS1_E_NONSECURE 0x1 415 #define ALT_L3_SEC_L4MAIN_SPIS1_LSB 1 417 #define ALT_L3_SEC_L4MAIN_SPIS1_MSB 1 419 #define ALT_L3_SEC_L4MAIN_SPIS1_WIDTH 1 421 #define ALT_L3_SEC_L4MAIN_SPIS1_SET_MSK 0x00000002 423 #define ALT_L3_SEC_L4MAIN_SPIS1_CLR_MSK 0xfffffffd 425 #define ALT_L3_SEC_L4MAIN_SPIS1_RESET 0x0 427 #define ALT_L3_SEC_L4MAIN_SPIS1_GET(value) (((value) & 0x00000002) >> 1) 429 #define ALT_L3_SEC_L4MAIN_SPIS1_SET(value) (((value) << 1) & 0x00000002) 453 #define ALT_L3_SEC_L4MAIN_DMASECURE_E_SECURE 0x0 459 #define ALT_L3_SEC_L4MAIN_DMASECURE_E_NONSECURE 0x1 462 #define ALT_L3_SEC_L4MAIN_DMASECURE_LSB 2 464 #define ALT_L3_SEC_L4MAIN_DMASECURE_MSB 2 466 #define ALT_L3_SEC_L4MAIN_DMASECURE_WIDTH 1 468 #define ALT_L3_SEC_L4MAIN_DMASECURE_SET_MSK 0x00000004 470 #define ALT_L3_SEC_L4MAIN_DMASECURE_CLR_MSK 0xfffffffb 472 #define ALT_L3_SEC_L4MAIN_DMASECURE_RESET 0x0 474 #define ALT_L3_SEC_L4MAIN_DMASECURE_GET(value) (((value) & 0x00000004) >> 2) 476 #define ALT_L3_SEC_L4MAIN_DMASECURE_SET(value) (((value) << 2) & 0x00000004) 501 #define ALT_L3_SEC_L4MAIN_DMANONSECURE_E_SECURE 0x0 507 #define ALT_L3_SEC_L4MAIN_DMANONSECURE_E_NONSECURE 0x1 510 #define ALT_L3_SEC_L4MAIN_DMANONSECURE_LSB 3 512 #define ALT_L3_SEC_L4MAIN_DMANONSECURE_MSB 3 514 #define ALT_L3_SEC_L4MAIN_DMANONSECURE_WIDTH 1 516 #define ALT_L3_SEC_L4MAIN_DMANONSECURE_SET_MSK 0x00000008 518 #define ALT_L3_SEC_L4MAIN_DMANONSECURE_CLR_MSK 0xfffffff7 520 #define ALT_L3_SEC_L4MAIN_DMANONSECURE_RESET 0x0 522 #define ALT_L3_SEC_L4MAIN_DMANONSECURE_GET(value) (((value) & 0x00000008) >> 3) 524 #define ALT_L3_SEC_L4MAIN_DMANONSECURE_SET(value) (((value) << 3) & 0x00000008) 541 uint32_t dmasecure : 1;
542 uint32_t dmanonsecure : 1;
551 #define ALT_L3_SEC_L4MAIN_OFST 0x0 599 #define ALT_L3_SEC_L4SP_SDRREGS_E_SECURE 0x0 605 #define ALT_L3_SEC_L4SP_SDRREGS_E_NONSECURE 0x1 608 #define ALT_L3_SEC_L4SP_SDRREGS_LSB 0 610 #define ALT_L3_SEC_L4SP_SDRREGS_MSB 0 612 #define ALT_L3_SEC_L4SP_SDRREGS_WIDTH 1 614 #define ALT_L3_SEC_L4SP_SDRREGS_SET_MSK 0x00000001 616 #define ALT_L3_SEC_L4SP_SDRREGS_CLR_MSK 0xfffffffe 618 #define ALT_L3_SEC_L4SP_SDRREGS_RESET 0x0 620 #define ALT_L3_SEC_L4SP_SDRREGS_GET(value) (((value) & 0x00000001) >> 0) 622 #define ALT_L3_SEC_L4SP_SDRREGS_SET(value) (((value) << 0) & 0x00000001) 646 #define ALT_L3_SEC_L4SP_SPTMR0_E_SECURE 0x0 652 #define ALT_L3_SEC_L4SP_SPTMR0_E_NONSECURE 0x1 655 #define ALT_L3_SEC_L4SP_SPTMR0_LSB 1 657 #define ALT_L3_SEC_L4SP_SPTMR0_MSB 1 659 #define ALT_L3_SEC_L4SP_SPTMR0_WIDTH 1 661 #define ALT_L3_SEC_L4SP_SPTMR0_SET_MSK 0x00000002 663 #define ALT_L3_SEC_L4SP_SPTMR0_CLR_MSK 0xfffffffd 665 #define ALT_L3_SEC_L4SP_SPTMR0_RESET 0x0 667 #define ALT_L3_SEC_L4SP_SPTMR0_GET(value) (((value) & 0x00000002) >> 1) 669 #define ALT_L3_SEC_L4SP_SPTMR0_SET(value) (((value) << 1) & 0x00000002) 693 #define ALT_L3_SEC_L4SP_I2C0_E_SECURE 0x0 699 #define ALT_L3_SEC_L4SP_I2C0_E_NONSECURE 0x1 702 #define ALT_L3_SEC_L4SP_I2C0_LSB 2 704 #define ALT_L3_SEC_L4SP_I2C0_MSB 2 706 #define ALT_L3_SEC_L4SP_I2C0_WIDTH 1 708 #define ALT_L3_SEC_L4SP_I2C0_SET_MSK 0x00000004 710 #define ALT_L3_SEC_L4SP_I2C0_CLR_MSK 0xfffffffb 712 #define ALT_L3_SEC_L4SP_I2C0_RESET 0x0 714 #define ALT_L3_SEC_L4SP_I2C0_GET(value) (((value) & 0x00000004) >> 2) 716 #define ALT_L3_SEC_L4SP_I2C0_SET(value) (((value) << 2) & 0x00000004) 740 #define ALT_L3_SEC_L4SP_I2C1_E_SECURE 0x0 746 #define ALT_L3_SEC_L4SP_I2C1_E_NONSECURE 0x1 749 #define ALT_L3_SEC_L4SP_I2C1_LSB 3 751 #define ALT_L3_SEC_L4SP_I2C1_MSB 3 753 #define ALT_L3_SEC_L4SP_I2C1_WIDTH 1 755 #define ALT_L3_SEC_L4SP_I2C1_SET_MSK 0x00000008 757 #define ALT_L3_SEC_L4SP_I2C1_CLR_MSK 0xfffffff7 759 #define ALT_L3_SEC_L4SP_I2C1_RESET 0x0 761 #define ALT_L3_SEC_L4SP_I2C1_GET(value) (((value) & 0x00000008) >> 3) 763 #define ALT_L3_SEC_L4SP_I2C1_SET(value) (((value) << 3) & 0x00000008) 788 #define ALT_L3_SEC_L4SP_I2C2_E_SECURE 0x0 794 #define ALT_L3_SEC_L4SP_I2C2_E_NONSECURE 0x1 797 #define ALT_L3_SEC_L4SP_I2C2_LSB 4 799 #define ALT_L3_SEC_L4SP_I2C2_MSB 4 801 #define ALT_L3_SEC_L4SP_I2C2_WIDTH 1 803 #define ALT_L3_SEC_L4SP_I2C2_SET_MSK 0x00000010 805 #define ALT_L3_SEC_L4SP_I2C2_CLR_MSK 0xffffffef 807 #define ALT_L3_SEC_L4SP_I2C2_RESET 0x0 809 #define ALT_L3_SEC_L4SP_I2C2_GET(value) (((value) & 0x00000010) >> 4) 811 #define ALT_L3_SEC_L4SP_I2C2_SET(value) (((value) << 4) & 0x00000010) 836 #define ALT_L3_SEC_L4SP_I2C3_E_SECURE 0x0 842 #define ALT_L3_SEC_L4SP_I2C3_E_NONSECURE 0x1 845 #define ALT_L3_SEC_L4SP_I2C3_LSB 5 847 #define ALT_L3_SEC_L4SP_I2C3_MSB 5 849 #define ALT_L3_SEC_L4SP_I2C3_WIDTH 1 851 #define ALT_L3_SEC_L4SP_I2C3_SET_MSK 0x00000020 853 #define ALT_L3_SEC_L4SP_I2C3_CLR_MSK 0xffffffdf 855 #define ALT_L3_SEC_L4SP_I2C3_RESET 0x0 857 #define ALT_L3_SEC_L4SP_I2C3_GET(value) (((value) & 0x00000020) >> 5) 859 #define ALT_L3_SEC_L4SP_I2C3_SET(value) (((value) << 5) & 0x00000020) 883 #define ALT_L3_SEC_L4SP_UART0_E_SECURE 0x0 889 #define ALT_L3_SEC_L4SP_UART0_E_NONSECURE 0x1 892 #define ALT_L3_SEC_L4SP_UART0_LSB 6 894 #define ALT_L3_SEC_L4SP_UART0_MSB 6 896 #define ALT_L3_SEC_L4SP_UART0_WIDTH 1 898 #define ALT_L3_SEC_L4SP_UART0_SET_MSK 0x00000040 900 #define ALT_L3_SEC_L4SP_UART0_CLR_MSK 0xffffffbf 902 #define ALT_L3_SEC_L4SP_UART0_RESET 0x0 904 #define ALT_L3_SEC_L4SP_UART0_GET(value) (((value) & 0x00000040) >> 6) 906 #define ALT_L3_SEC_L4SP_UART0_SET(value) (((value) << 6) & 0x00000040) 930 #define ALT_L3_SEC_L4SP_UART1_E_SECURE 0x0 936 #define ALT_L3_SEC_L4SP_UART1_E_NONSECURE 0x1 939 #define ALT_L3_SEC_L4SP_UART1_LSB 7 941 #define ALT_L3_SEC_L4SP_UART1_MSB 7 943 #define ALT_L3_SEC_L4SP_UART1_WIDTH 1 945 #define ALT_L3_SEC_L4SP_UART1_SET_MSK 0x00000080 947 #define ALT_L3_SEC_L4SP_UART1_CLR_MSK 0xffffff7f 949 #define ALT_L3_SEC_L4SP_UART1_RESET 0x0 951 #define ALT_L3_SEC_L4SP_UART1_GET(value) (((value) & 0x00000080) >> 7) 953 #define ALT_L3_SEC_L4SP_UART1_SET(value) (((value) << 7) & 0x00000080) 977 #define ALT_L3_SEC_L4SP_CAN0_E_SECURE 0x0 983 #define ALT_L3_SEC_L4SP_CAN0_E_NONSECURE 0x1 986 #define ALT_L3_SEC_L4SP_CAN0_LSB 8 988 #define ALT_L3_SEC_L4SP_CAN0_MSB 8 990 #define ALT_L3_SEC_L4SP_CAN0_WIDTH 1 992 #define ALT_L3_SEC_L4SP_CAN0_SET_MSK 0x00000100 994 #define ALT_L3_SEC_L4SP_CAN0_CLR_MSK 0xfffffeff 996 #define ALT_L3_SEC_L4SP_CAN0_RESET 0x0 998 #define ALT_L3_SEC_L4SP_CAN0_GET(value) (((value) & 0x00000100) >> 8) 1000 #define ALT_L3_SEC_L4SP_CAN0_SET(value) (((value) << 8) & 0x00000100) 1024 #define ALT_L3_SEC_L4SP_CAN1_E_SECURE 0x0 1030 #define ALT_L3_SEC_L4SP_CAN1_E_NONSECURE 0x1 1033 #define ALT_L3_SEC_L4SP_CAN1_LSB 9 1035 #define ALT_L3_SEC_L4SP_CAN1_MSB 9 1037 #define ALT_L3_SEC_L4SP_CAN1_WIDTH 1 1039 #define ALT_L3_SEC_L4SP_CAN1_SET_MSK 0x00000200 1041 #define ALT_L3_SEC_L4SP_CAN1_CLR_MSK 0xfffffdff 1043 #define ALT_L3_SEC_L4SP_CAN1_RESET 0x0 1045 #define ALT_L3_SEC_L4SP_CAN1_GET(value) (((value) & 0x00000200) >> 9) 1047 #define ALT_L3_SEC_L4SP_CAN1_SET(value) (((value) << 9) & 0x00000200) 1071 #define ALT_L3_SEC_L4SP_SPTMR1_E_SECURE 0x0 1077 #define ALT_L3_SEC_L4SP_SPTMR1_E_NONSECURE 0x1 1080 #define ALT_L3_SEC_L4SP_SPTMR1_LSB 10 1082 #define ALT_L3_SEC_L4SP_SPTMR1_MSB 10 1084 #define ALT_L3_SEC_L4SP_SPTMR1_WIDTH 1 1086 #define ALT_L3_SEC_L4SP_SPTMR1_SET_MSK 0x00000400 1088 #define ALT_L3_SEC_L4SP_SPTMR1_CLR_MSK 0xfffffbff 1090 #define ALT_L3_SEC_L4SP_SPTMR1_RESET 0x0 1092 #define ALT_L3_SEC_L4SP_SPTMR1_GET(value) (((value) & 0x00000400) >> 10) 1094 #define ALT_L3_SEC_L4SP_SPTMR1_SET(value) (((value) << 10) & 0x00000400) 1096 #ifndef __ASSEMBLY__ 1109 uint32_t sdrregs : 1;
1110 uint32_t sptimer0 : 1;
1119 uint32_t sptimer1 : 1;
1128 #define ALT_L3_SEC_L4SP_OFST 0x4 1175 #define ALT_L3_SEC_L4MP_FPGAMGR_E_SECURE 0x0 1181 #define ALT_L3_SEC_L4MP_FPGAMGR_E_NONSECURE 0x1 1184 #define ALT_L3_SEC_L4MP_FPGAMGR_LSB 0 1186 #define ALT_L3_SEC_L4MP_FPGAMGR_MSB 0 1188 #define ALT_L3_SEC_L4MP_FPGAMGR_WIDTH 1 1190 #define ALT_L3_SEC_L4MP_FPGAMGR_SET_MSK 0x00000001 1192 #define ALT_L3_SEC_L4MP_FPGAMGR_CLR_MSK 0xfffffffe 1194 #define ALT_L3_SEC_L4MP_FPGAMGR_RESET 0x0 1196 #define ALT_L3_SEC_L4MP_FPGAMGR_GET(value) (((value) & 0x00000001) >> 0) 1198 #define ALT_L3_SEC_L4MP_FPGAMGR_SET(value) (((value) << 0) & 0x00000001) 1222 #define ALT_L3_SEC_L4MP_DAP_E_SECURE 0x0 1228 #define ALT_L3_SEC_L4MP_DAP_E_NONSECURE 0x1 1231 #define ALT_L3_SEC_L4MP_DAP_LSB 1 1233 #define ALT_L3_SEC_L4MP_DAP_MSB 1 1235 #define ALT_L3_SEC_L4MP_DAP_WIDTH 1 1237 #define ALT_L3_SEC_L4MP_DAP_SET_MSK 0x00000002 1239 #define ALT_L3_SEC_L4MP_DAP_CLR_MSK 0xfffffffd 1241 #define ALT_L3_SEC_L4MP_DAP_RESET 0x0 1243 #define ALT_L3_SEC_L4MP_DAP_GET(value) (((value) & 0x00000002) >> 1) 1245 #define ALT_L3_SEC_L4MP_DAP_SET(value) (((value) << 1) & 0x00000002) 1270 #define ALT_L3_SEC_L4MP_QSPI_E_SECURE 0x0 1276 #define ALT_L3_SEC_L4MP_QSPI_E_NONSECURE 0x1 1279 #define ALT_L3_SEC_L4MP_QSPI_LSB 2 1281 #define ALT_L3_SEC_L4MP_QSPI_MSB 2 1283 #define ALT_L3_SEC_L4MP_QSPI_WIDTH 1 1285 #define ALT_L3_SEC_L4MP_QSPI_SET_MSK 0x00000004 1287 #define ALT_L3_SEC_L4MP_QSPI_CLR_MSK 0xfffffffb 1289 #define ALT_L3_SEC_L4MP_QSPI_RESET 0x0 1291 #define ALT_L3_SEC_L4MP_QSPI_GET(value) (((value) & 0x00000004) >> 2) 1293 #define ALT_L3_SEC_L4MP_QSPI_SET(value) (((value) << 2) & 0x00000004) 1317 #define ALT_L3_SEC_L4MP_SDMMC_E_SECURE 0x0 1323 #define ALT_L3_SEC_L4MP_SDMMC_E_NONSECURE 0x1 1326 #define ALT_L3_SEC_L4MP_SDMMC_LSB 3 1328 #define ALT_L3_SEC_L4MP_SDMMC_MSB 3 1330 #define ALT_L3_SEC_L4MP_SDMMC_WIDTH 1 1332 #define ALT_L3_SEC_L4MP_SDMMC_SET_MSK 0x00000008 1334 #define ALT_L3_SEC_L4MP_SDMMC_CLR_MSK 0xfffffff7 1336 #define ALT_L3_SEC_L4MP_SDMMC_RESET 0x0 1338 #define ALT_L3_SEC_L4MP_SDMMC_GET(value) (((value) & 0x00000008) >> 3) 1340 #define ALT_L3_SEC_L4MP_SDMMC_SET(value) (((value) << 3) & 0x00000008) 1364 #define ALT_L3_SEC_L4MP_EMAC0_E_SECURE 0x0 1370 #define ALT_L3_SEC_L4MP_EMAC0_E_NONSECURE 0x1 1373 #define ALT_L3_SEC_L4MP_EMAC0_LSB 4 1375 #define ALT_L3_SEC_L4MP_EMAC0_MSB 4 1377 #define ALT_L3_SEC_L4MP_EMAC0_WIDTH 1 1379 #define ALT_L3_SEC_L4MP_EMAC0_SET_MSK 0x00000010 1381 #define ALT_L3_SEC_L4MP_EMAC0_CLR_MSK 0xffffffef 1383 #define ALT_L3_SEC_L4MP_EMAC0_RESET 0x0 1385 #define ALT_L3_SEC_L4MP_EMAC0_GET(value) (((value) & 0x00000010) >> 4) 1387 #define ALT_L3_SEC_L4MP_EMAC0_SET(value) (((value) << 4) & 0x00000010) 1411 #define ALT_L3_SEC_L4MP_EMAC1_E_SECURE 0x0 1417 #define ALT_L3_SEC_L4MP_EMAC1_E_NONSECURE 0x1 1420 #define ALT_L3_SEC_L4MP_EMAC1_LSB 5 1422 #define ALT_L3_SEC_L4MP_EMAC1_MSB 5 1424 #define ALT_L3_SEC_L4MP_EMAC1_WIDTH 1 1426 #define ALT_L3_SEC_L4MP_EMAC1_SET_MSK 0x00000020 1428 #define ALT_L3_SEC_L4MP_EMAC1_CLR_MSK 0xffffffdf 1430 #define ALT_L3_SEC_L4MP_EMAC1_RESET 0x0 1432 #define ALT_L3_SEC_L4MP_EMAC1_GET(value) (((value) & 0x00000020) >> 5) 1434 #define ALT_L3_SEC_L4MP_EMAC1_SET(value) (((value) << 5) & 0x00000020) 1459 #define ALT_L3_SEC_L4MP_ACPIDMAP_E_SECURE 0x0 1465 #define ALT_L3_SEC_L4MP_ACPIDMAP_E_NONSECURE 0x1 1468 #define ALT_L3_SEC_L4MP_ACPIDMAP_LSB 6 1470 #define ALT_L3_SEC_L4MP_ACPIDMAP_MSB 6 1472 #define ALT_L3_SEC_L4MP_ACPIDMAP_WIDTH 1 1474 #define ALT_L3_SEC_L4MP_ACPIDMAP_SET_MSK 0x00000040 1476 #define ALT_L3_SEC_L4MP_ACPIDMAP_CLR_MSK 0xffffffbf 1478 #define ALT_L3_SEC_L4MP_ACPIDMAP_RESET 0x0 1480 #define ALT_L3_SEC_L4MP_ACPIDMAP_GET(value) (((value) & 0x00000040) >> 6) 1482 #define ALT_L3_SEC_L4MP_ACPIDMAP_SET(value) (((value) << 6) & 0x00000040) 1506 #define ALT_L3_SEC_L4MP_GPIO0_E_SECURE 0x0 1512 #define ALT_L3_SEC_L4MP_GPIO0_E_NONSECURE 0x1 1515 #define ALT_L3_SEC_L4MP_GPIO0_LSB 7 1517 #define ALT_L3_SEC_L4MP_GPIO0_MSB 7 1519 #define ALT_L3_SEC_L4MP_GPIO0_WIDTH 1 1521 #define ALT_L3_SEC_L4MP_GPIO0_SET_MSK 0x00000080 1523 #define ALT_L3_SEC_L4MP_GPIO0_CLR_MSK 0xffffff7f 1525 #define ALT_L3_SEC_L4MP_GPIO0_RESET 0x0 1527 #define ALT_L3_SEC_L4MP_GPIO0_GET(value) (((value) & 0x00000080) >> 7) 1529 #define ALT_L3_SEC_L4MP_GPIO0_SET(value) (((value) << 7) & 0x00000080) 1553 #define ALT_L3_SEC_L4MP_GPIO1_E_SECURE 0x0 1559 #define ALT_L3_SEC_L4MP_GPIO1_E_NONSECURE 0x1 1562 #define ALT_L3_SEC_L4MP_GPIO1_LSB 8 1564 #define ALT_L3_SEC_L4MP_GPIO1_MSB 8 1566 #define ALT_L3_SEC_L4MP_GPIO1_WIDTH 1 1568 #define ALT_L3_SEC_L4MP_GPIO1_SET_MSK 0x00000100 1570 #define ALT_L3_SEC_L4MP_GPIO1_CLR_MSK 0xfffffeff 1572 #define ALT_L3_SEC_L4MP_GPIO1_RESET 0x0 1574 #define ALT_L3_SEC_L4MP_GPIO1_GET(value) (((value) & 0x00000100) >> 8) 1576 #define ALT_L3_SEC_L4MP_GPIO1_SET(value) (((value) << 8) & 0x00000100) 1600 #define ALT_L3_SEC_L4MP_GPIO2_E_SECURE 0x0 1606 #define ALT_L3_SEC_L4MP_GPIO2_E_NONSECURE 0x1 1609 #define ALT_L3_SEC_L4MP_GPIO2_LSB 9 1611 #define ALT_L3_SEC_L4MP_GPIO2_MSB 9 1613 #define ALT_L3_SEC_L4MP_GPIO2_WIDTH 1 1615 #define ALT_L3_SEC_L4MP_GPIO2_SET_MSK 0x00000200 1617 #define ALT_L3_SEC_L4MP_GPIO2_CLR_MSK 0xfffffdff 1619 #define ALT_L3_SEC_L4MP_GPIO2_RESET 0x0 1621 #define ALT_L3_SEC_L4MP_GPIO2_GET(value) (((value) & 0x00000200) >> 9) 1623 #define ALT_L3_SEC_L4MP_GPIO2_SET(value) (((value) << 9) & 0x00000200) 1625 #ifndef __ASSEMBLY__ 1638 uint32_t fpgamgrregs : 1;
1640 uint32_t qspiregs : 1;
1644 uint32_t acpidmap : 1;
1656 #define ALT_L3_SEC_L4MP_OFST 0x8 1700 #define ALT_L3_SEC_L4OSC1_L4WD0_E_SECURE 0x0 1706 #define ALT_L3_SEC_L4OSC1_L4WD0_E_NONSECURE 0x1 1709 #define ALT_L3_SEC_L4OSC1_L4WD0_LSB 0 1711 #define ALT_L3_SEC_L4OSC1_L4WD0_MSB 0 1713 #define ALT_L3_SEC_L4OSC1_L4WD0_WIDTH 1 1715 #define ALT_L3_SEC_L4OSC1_L4WD0_SET_MSK 0x00000001 1717 #define ALT_L3_SEC_L4OSC1_L4WD0_CLR_MSK 0xfffffffe 1719 #define ALT_L3_SEC_L4OSC1_L4WD0_RESET 0x0 1721 #define ALT_L3_SEC_L4OSC1_L4WD0_GET(value) (((value) & 0x00000001) >> 0) 1723 #define ALT_L3_SEC_L4OSC1_L4WD0_SET(value) (((value) << 0) & 0x00000001) 1748 #define ALT_L3_SEC_L4OSC1_L4WD1_E_SECURE 0x0 1754 #define ALT_L3_SEC_L4OSC1_L4WD1_E_NONSECURE 0x1 1757 #define ALT_L3_SEC_L4OSC1_L4WD1_LSB 1 1759 #define ALT_L3_SEC_L4OSC1_L4WD1_MSB 1 1761 #define ALT_L3_SEC_L4OSC1_L4WD1_WIDTH 1 1763 #define ALT_L3_SEC_L4OSC1_L4WD1_SET_MSK 0x00000002 1765 #define ALT_L3_SEC_L4OSC1_L4WD1_CLR_MSK 0xfffffffd 1767 #define ALT_L3_SEC_L4OSC1_L4WD1_RESET 0x0 1769 #define ALT_L3_SEC_L4OSC1_L4WD1_GET(value) (((value) & 0x00000002) >> 1) 1771 #define ALT_L3_SEC_L4OSC1_L4WD1_SET(value) (((value) << 1) & 0x00000002) 1796 #define ALT_L3_SEC_L4OSC1_CLKMGR_E_SECURE 0x0 1802 #define ALT_L3_SEC_L4OSC1_CLKMGR_E_NONSECURE 0x1 1805 #define ALT_L3_SEC_L4OSC1_CLKMGR_LSB 2 1807 #define ALT_L3_SEC_L4OSC1_CLKMGR_MSB 2 1809 #define ALT_L3_SEC_L4OSC1_CLKMGR_WIDTH 1 1811 #define ALT_L3_SEC_L4OSC1_CLKMGR_SET_MSK 0x00000004 1813 #define ALT_L3_SEC_L4OSC1_CLKMGR_CLR_MSK 0xfffffffb 1815 #define ALT_L3_SEC_L4OSC1_CLKMGR_RESET 0x0 1817 #define ALT_L3_SEC_L4OSC1_CLKMGR_GET(value) (((value) & 0x00000004) >> 2) 1819 #define ALT_L3_SEC_L4OSC1_CLKMGR_SET(value) (((value) << 2) & 0x00000004) 1844 #define ALT_L3_SEC_L4OSC1_RSTMGR_E_SECURE 0x0 1850 #define ALT_L3_SEC_L4OSC1_RSTMGR_E_NONSECURE 0x1 1853 #define ALT_L3_SEC_L4OSC1_RSTMGR_LSB 3 1855 #define ALT_L3_SEC_L4OSC1_RSTMGR_MSB 3 1857 #define ALT_L3_SEC_L4OSC1_RSTMGR_WIDTH 1 1859 #define ALT_L3_SEC_L4OSC1_RSTMGR_SET_MSK 0x00000008 1861 #define ALT_L3_SEC_L4OSC1_RSTMGR_CLR_MSK 0xfffffff7 1863 #define ALT_L3_SEC_L4OSC1_RSTMGR_RESET 0x0 1865 #define ALT_L3_SEC_L4OSC1_RSTMGR_GET(value) (((value) & 0x00000008) >> 3) 1867 #define ALT_L3_SEC_L4OSC1_RSTMGR_SET(value) (((value) << 3) & 0x00000008) 1892 #define ALT_L3_SEC_L4OSC1_SYSMGR_E_SECURE 0x0 1898 #define ALT_L3_SEC_L4OSC1_SYSMGR_E_NONSECURE 0x1 1901 #define ALT_L3_SEC_L4OSC1_SYSMGR_LSB 4 1903 #define ALT_L3_SEC_L4OSC1_SYSMGR_MSB 4 1905 #define ALT_L3_SEC_L4OSC1_SYSMGR_WIDTH 1 1907 #define ALT_L3_SEC_L4OSC1_SYSMGR_SET_MSK 0x00000010 1909 #define ALT_L3_SEC_L4OSC1_SYSMGR_CLR_MSK 0xffffffef 1911 #define ALT_L3_SEC_L4OSC1_SYSMGR_RESET 0x0 1913 #define ALT_L3_SEC_L4OSC1_SYSMGR_GET(value) (((value) & 0x00000010) >> 4) 1915 #define ALT_L3_SEC_L4OSC1_SYSMGR_SET(value) (((value) << 4) & 0x00000010) 1939 #define ALT_L3_SEC_L4OSC1_OSC1TMR0_E_SECURE 0x0 1945 #define ALT_L3_SEC_L4OSC1_OSC1TMR0_E_NONSECURE 0x1 1948 #define ALT_L3_SEC_L4OSC1_OSC1TMR0_LSB 5 1950 #define ALT_L3_SEC_L4OSC1_OSC1TMR0_MSB 5 1952 #define ALT_L3_SEC_L4OSC1_OSC1TMR0_WIDTH 1 1954 #define ALT_L3_SEC_L4OSC1_OSC1TMR0_SET_MSK 0x00000020 1956 #define ALT_L3_SEC_L4OSC1_OSC1TMR0_CLR_MSK 0xffffffdf 1958 #define ALT_L3_SEC_L4OSC1_OSC1TMR0_RESET 0x0 1960 #define ALT_L3_SEC_L4OSC1_OSC1TMR0_GET(value) (((value) & 0x00000020) >> 5) 1962 #define ALT_L3_SEC_L4OSC1_OSC1TMR0_SET(value) (((value) << 5) & 0x00000020) 1986 #define ALT_L3_SEC_L4OSC1_OSC1TMR1_E_SECURE 0x0 1992 #define ALT_L3_SEC_L4OSC1_OSC1TMR1_E_NONSECURE 0x1 1995 #define ALT_L3_SEC_L4OSC1_OSC1TMR1_LSB 6 1997 #define ALT_L3_SEC_L4OSC1_OSC1TMR1_MSB 6 1999 #define ALT_L3_SEC_L4OSC1_OSC1TMR1_WIDTH 1 2001 #define ALT_L3_SEC_L4OSC1_OSC1TMR1_SET_MSK 0x00000040 2003 #define ALT_L3_SEC_L4OSC1_OSC1TMR1_CLR_MSK 0xffffffbf 2005 #define ALT_L3_SEC_L4OSC1_OSC1TMR1_RESET 0x0 2007 #define ALT_L3_SEC_L4OSC1_OSC1TMR1_GET(value) (((value) & 0x00000040) >> 6) 2009 #define ALT_L3_SEC_L4OSC1_OSC1TMR1_SET(value) (((value) << 6) & 0x00000040) 2011 #ifndef __ASSEMBLY__ 2026 uint32_t clkmgr : 1;
2027 uint32_t rstmgr : 1;
2028 uint32_t sysmgr : 1;
2029 uint32_t osc1timer0 : 1;
2030 uint32_t osc1timer1 : 1;
2039 #define ALT_L3_SEC_L4OSC1_OFST 0xc 2078 #define ALT_L3_SEC_L4SPIM_SPIM0_E_SECURE 0x0 2084 #define ALT_L3_SEC_L4SPIM_SPIM0_E_NONSECURE 0x1 2087 #define ALT_L3_SEC_L4SPIM_SPIM0_LSB 0 2089 #define ALT_L3_SEC_L4SPIM_SPIM0_MSB 0 2091 #define ALT_L3_SEC_L4SPIM_SPIM0_WIDTH 1 2093 #define ALT_L3_SEC_L4SPIM_SPIM0_SET_MSK 0x00000001 2095 #define ALT_L3_SEC_L4SPIM_SPIM0_CLR_MSK 0xfffffffe 2097 #define ALT_L3_SEC_L4SPIM_SPIM0_RESET 0x0 2099 #define ALT_L3_SEC_L4SPIM_SPIM0_GET(value) (((value) & 0x00000001) >> 0) 2101 #define ALT_L3_SEC_L4SPIM_SPIM0_SET(value) (((value) << 0) & 0x00000001) 2125 #define ALT_L3_SEC_L4SPIM_SPIM1_E_SECURE 0x0 2131 #define ALT_L3_SEC_L4SPIM_SPIM1_E_NONSECURE 0x1 2134 #define ALT_L3_SEC_L4SPIM_SPIM1_LSB 1 2136 #define ALT_L3_SEC_L4SPIM_SPIM1_MSB 1 2138 #define ALT_L3_SEC_L4SPIM_SPIM1_WIDTH 1 2140 #define ALT_L3_SEC_L4SPIM_SPIM1_SET_MSK 0x00000002 2142 #define ALT_L3_SEC_L4SPIM_SPIM1_CLR_MSK 0xfffffffd 2144 #define ALT_L3_SEC_L4SPIM_SPIM1_RESET 0x0 2146 #define ALT_L3_SEC_L4SPIM_SPIM1_GET(value) (((value) & 0x00000002) >> 1) 2148 #define ALT_L3_SEC_L4SPIM_SPIM1_SET(value) (((value) << 1) & 0x00000002) 2172 #define ALT_L3_SEC_L4SPIM_SCANMGR_E_SECURE 0x0 2178 #define ALT_L3_SEC_L4SPIM_SCANMGR_E_NONSECURE 0x1 2181 #define ALT_L3_SEC_L4SPIM_SCANMGR_LSB 2 2183 #define ALT_L3_SEC_L4SPIM_SCANMGR_MSB 2 2185 #define ALT_L3_SEC_L4SPIM_SCANMGR_WIDTH 1 2187 #define ALT_L3_SEC_L4SPIM_SCANMGR_SET_MSK 0x00000004 2189 #define ALT_L3_SEC_L4SPIM_SCANMGR_CLR_MSK 0xfffffffb 2191 #define ALT_L3_SEC_L4SPIM_SCANMGR_RESET 0x0 2193 #define ALT_L3_SEC_L4SPIM_SCANMGR_GET(value) (((value) & 0x00000004) >> 2) 2195 #define ALT_L3_SEC_L4SPIM_SCANMGR_SET(value) (((value) << 2) & 0x00000004) 2197 #ifndef __ASSEMBLY__ 2212 uint32_t scanmgr : 1;
2221 #define ALT_L3_SEC_L4SPIM_OFST 0x10 2258 #define ALT_L3_SEC_STM_S_E_SECURE 0x0 2264 #define ALT_L3_SEC_STM_S_E_NONSECURE 0x1 2267 #define ALT_L3_SEC_STM_S_LSB 0 2269 #define ALT_L3_SEC_STM_S_MSB 0 2271 #define ALT_L3_SEC_STM_S_WIDTH 1 2273 #define ALT_L3_SEC_STM_S_SET_MSK 0x00000001 2275 #define ALT_L3_SEC_STM_S_CLR_MSK 0xfffffffe 2277 #define ALT_L3_SEC_STM_S_RESET 0x0 2279 #define ALT_L3_SEC_STM_S_GET(value) (((value) & 0x00000001) >> 0) 2281 #define ALT_L3_SEC_STM_S_SET(value) (((value) << 0) & 0x00000001) 2283 #ifndef __ASSEMBLY__ 2305 #define ALT_L3_SEC_STM_OFST 0x14 2343 #define ALT_L3_SEC_LWH2F_S_E_SECURE 0x0 2349 #define ALT_L3_SEC_LWH2F_S_E_NONSECURE 0x1 2352 #define ALT_L3_SEC_LWH2F_S_LSB 0 2354 #define ALT_L3_SEC_LWH2F_S_MSB 0 2356 #define ALT_L3_SEC_LWH2F_S_WIDTH 1 2358 #define ALT_L3_SEC_LWH2F_S_SET_MSK 0x00000001 2360 #define ALT_L3_SEC_LWH2F_S_CLR_MSK 0xfffffffe 2362 #define ALT_L3_SEC_LWH2F_S_RESET 0x0 2364 #define ALT_L3_SEC_LWH2F_S_GET(value) (((value) & 0x00000001) >> 0) 2366 #define ALT_L3_SEC_LWH2F_S_SET(value) (((value) << 0) & 0x00000001) 2368 #ifndef __ASSEMBLY__ 2390 #define ALT_L3_SEC_LWH2F_OFST 0x18 2428 #define ALT_L3_SEC_USB1_S_E_SECURE 0x0 2434 #define ALT_L3_SEC_USB1_S_E_NONSECURE 0x1 2437 #define ALT_L3_SEC_USB1_S_LSB 0 2439 #define ALT_L3_SEC_USB1_S_MSB 0 2441 #define ALT_L3_SEC_USB1_S_WIDTH 1 2443 #define ALT_L3_SEC_USB1_S_SET_MSK 0x00000001 2445 #define ALT_L3_SEC_USB1_S_CLR_MSK 0xfffffffe 2447 #define ALT_L3_SEC_USB1_S_RESET 0x0 2449 #define ALT_L3_SEC_USB1_S_GET(value) (((value) & 0x00000001) >> 0) 2451 #define ALT_L3_SEC_USB1_S_SET(value) (((value) << 0) & 0x00000001) 2453 #ifndef __ASSEMBLY__ 2475 #define ALT_L3_SEC_USB1_OFST 0x20 2513 #define ALT_L3_SEC_NANDDATA_S_E_SECURE 0x0 2519 #define ALT_L3_SEC_NANDDATA_S_E_NONSECURE 0x1 2522 #define ALT_L3_SEC_NANDDATA_S_LSB 0 2524 #define ALT_L3_SEC_NANDDATA_S_MSB 0 2526 #define ALT_L3_SEC_NANDDATA_S_WIDTH 1 2528 #define ALT_L3_SEC_NANDDATA_S_SET_MSK 0x00000001 2530 #define ALT_L3_SEC_NANDDATA_S_CLR_MSK 0xfffffffe 2532 #define ALT_L3_SEC_NANDDATA_S_RESET 0x0 2534 #define ALT_L3_SEC_NANDDATA_S_GET(value) (((value) & 0x00000001) >> 0) 2536 #define ALT_L3_SEC_NANDDATA_S_SET(value) (((value) << 0) & 0x00000001) 2538 #ifndef __ASSEMBLY__ 2560 #define ALT_L3_SEC_NANDDATA_OFST 0x24 2598 #define ALT_L3_SEC_USB0_S_E_SECURE 0x0 2604 #define ALT_L3_SEC_USB0_S_E_NONSECURE 0x1 2607 #define ALT_L3_SEC_USB0_S_LSB 0 2609 #define ALT_L3_SEC_USB0_S_MSB 0 2611 #define ALT_L3_SEC_USB0_S_WIDTH 1 2613 #define ALT_L3_SEC_USB0_S_SET_MSK 0x00000001 2615 #define ALT_L3_SEC_USB0_S_CLR_MSK 0xfffffffe 2617 #define ALT_L3_SEC_USB0_S_RESET 0x0 2619 #define ALT_L3_SEC_USB0_S_GET(value) (((value) & 0x00000001) >> 0) 2621 #define ALT_L3_SEC_USB0_S_SET(value) (((value) << 0) & 0x00000001) 2623 #ifndef __ASSEMBLY__ 2645 #define ALT_L3_SEC_USB0_OFST 0x78 2683 #define ALT_L3_SEC_NAND_S_E_SECURE 0x0 2689 #define ALT_L3_SEC_NAND_S_E_NONSECURE 0x1 2692 #define ALT_L3_SEC_NAND_S_LSB 0 2694 #define ALT_L3_SEC_NAND_S_MSB 0 2696 #define ALT_L3_SEC_NAND_S_WIDTH 1 2698 #define ALT_L3_SEC_NAND_S_SET_MSK 0x00000001 2700 #define ALT_L3_SEC_NAND_S_CLR_MSK 0xfffffffe 2702 #define ALT_L3_SEC_NAND_S_RESET 0x0 2704 #define ALT_L3_SEC_NAND_S_GET(value) (((value) & 0x00000001) >> 0) 2706 #define ALT_L3_SEC_NAND_S_SET(value) (((value) << 0) & 0x00000001) 2708 #ifndef __ASSEMBLY__ 2730 #define ALT_L3_SEC_NAND_OFST 0x7c 2768 #define ALT_L3_SEC_QSPIDATA_S_E_SECURE 0x0 2774 #define ALT_L3_SEC_QSPIDATA_S_E_NONSECURE 0x1 2777 #define ALT_L3_SEC_QSPIDATA_S_LSB 0 2779 #define ALT_L3_SEC_QSPIDATA_S_MSB 0 2781 #define ALT_L3_SEC_QSPIDATA_S_WIDTH 1 2783 #define ALT_L3_SEC_QSPIDATA_S_SET_MSK 0x00000001 2785 #define ALT_L3_SEC_QSPIDATA_S_CLR_MSK 0xfffffffe 2787 #define ALT_L3_SEC_QSPIDATA_S_RESET 0x0 2789 #define ALT_L3_SEC_QSPIDATA_S_GET(value) (((value) & 0x00000001) >> 0) 2791 #define ALT_L3_SEC_QSPIDATA_S_SET(value) (((value) << 0) & 0x00000001) 2793 #ifndef __ASSEMBLY__ 2815 #define ALT_L3_SEC_QSPIDATA_OFST 0x80 2853 #define ALT_L3_SEC_FPGAMGRDATA_S_E_SECURE 0x0 2859 #define ALT_L3_SEC_FPGAMGRDATA_S_E_NONSECURE 0x1 2862 #define ALT_L3_SEC_FPGAMGRDATA_S_LSB 0 2864 #define ALT_L3_SEC_FPGAMGRDATA_S_MSB 0 2866 #define ALT_L3_SEC_FPGAMGRDATA_S_WIDTH 1 2868 #define ALT_L3_SEC_FPGAMGRDATA_S_SET_MSK 0x00000001 2870 #define ALT_L3_SEC_FPGAMGRDATA_S_CLR_MSK 0xfffffffe 2872 #define ALT_L3_SEC_FPGAMGRDATA_S_RESET 0x0 2874 #define ALT_L3_SEC_FPGAMGRDATA_S_GET(value) (((value) & 0x00000001) >> 0) 2876 #define ALT_L3_SEC_FPGAMGRDATA_S_SET(value) (((value) << 0) & 0x00000001) 2878 #ifndef __ASSEMBLY__ 2900 #define ALT_L3_SEC_FPGAMGRDATA_OFST 0x84 2938 #define ALT_L3_SEC_H2F_S_E_SECURE 0x0 2944 #define ALT_L3_SEC_H2F_S_E_NONSECURE 0x1 2947 #define ALT_L3_SEC_H2F_S_LSB 0 2949 #define ALT_L3_SEC_H2F_S_MSB 0 2951 #define ALT_L3_SEC_H2F_S_WIDTH 1 2953 #define ALT_L3_SEC_H2F_S_SET_MSK 0x00000001 2955 #define ALT_L3_SEC_H2F_S_CLR_MSK 0xfffffffe 2957 #define ALT_L3_SEC_H2F_S_RESET 0x0 2959 #define ALT_L3_SEC_H2F_S_GET(value) (((value) & 0x00000001) >> 0) 2961 #define ALT_L3_SEC_H2F_S_SET(value) (((value) << 0) & 0x00000001) 2963 #ifndef __ASSEMBLY__ 2985 #define ALT_L3_SEC_H2F_OFST 0x88 3022 #define ALT_L3_SEC_ACP_S_E_SECURE 0x0 3028 #define ALT_L3_SEC_ACP_S_E_NONSECURE 0x1 3031 #define ALT_L3_SEC_ACP_S_LSB 0 3033 #define ALT_L3_SEC_ACP_S_MSB 0 3035 #define ALT_L3_SEC_ACP_S_WIDTH 1 3037 #define ALT_L3_SEC_ACP_S_SET_MSK 0x00000001 3039 #define ALT_L3_SEC_ACP_S_CLR_MSK 0xfffffffe 3041 #define ALT_L3_SEC_ACP_S_RESET 0x0 3043 #define ALT_L3_SEC_ACP_S_GET(value) (((value) & 0x00000001) >> 0) 3045 #define ALT_L3_SEC_ACP_S_SET(value) (((value) << 0) & 0x00000001) 3047 #ifndef __ASSEMBLY__ 3069 #define ALT_L3_SEC_ACP_OFST 0x8c 3106 #define ALT_L3_SEC_ROM_S_E_SECURE 0x0 3112 #define ALT_L3_SEC_ROM_S_E_NONSECURE 0x1 3115 #define ALT_L3_SEC_ROM_S_LSB 0 3117 #define ALT_L3_SEC_ROM_S_MSB 0 3119 #define ALT_L3_SEC_ROM_S_WIDTH 1 3121 #define ALT_L3_SEC_ROM_S_SET_MSK 0x00000001 3123 #define ALT_L3_SEC_ROM_S_CLR_MSK 0xfffffffe 3125 #define ALT_L3_SEC_ROM_S_RESET 0x0 3127 #define ALT_L3_SEC_ROM_S_GET(value) (((value) & 0x00000001) >> 0) 3129 #define ALT_L3_SEC_ROM_S_SET(value) (((value) << 0) & 0x00000001) 3131 #ifndef __ASSEMBLY__ 3153 #define ALT_L3_SEC_ROM_OFST 0x90 3190 #define ALT_L3_SEC_OCRAM_S_E_SECURE 0x0 3196 #define ALT_L3_SEC_OCRAM_S_E_NONSECURE 0x1 3199 #define ALT_L3_SEC_OCRAM_S_LSB 0 3201 #define ALT_L3_SEC_OCRAM_S_MSB 0 3203 #define ALT_L3_SEC_OCRAM_S_WIDTH 1 3205 #define ALT_L3_SEC_OCRAM_S_SET_MSK 0x00000001 3207 #define ALT_L3_SEC_OCRAM_S_CLR_MSK 0xfffffffe 3209 #define ALT_L3_SEC_OCRAM_S_RESET 0x0 3211 #define ALT_L3_SEC_OCRAM_S_GET(value) (((value) & 0x00000001) >> 0) 3213 #define ALT_L3_SEC_OCRAM_S_SET(value) (((value) << 0) & 0x00000001) 3215 #ifndef __ASSEMBLY__ 3237 #define ALT_L3_SEC_OCRAM_OFST 0x94 3274 #define ALT_L3_SEC_SDRDATA_S_E_SECURE 0x0 3280 #define ALT_L3_SEC_SDRDATA_S_E_NONSECURE 0x1 3283 #define ALT_L3_SEC_SDRDATA_S_LSB 0 3285 #define ALT_L3_SEC_SDRDATA_S_MSB 0 3287 #define ALT_L3_SEC_SDRDATA_S_WIDTH 1 3289 #define ALT_L3_SEC_SDRDATA_S_SET_MSK 0x00000001 3291 #define ALT_L3_SEC_SDRDATA_S_CLR_MSK 0xfffffffe 3293 #define ALT_L3_SEC_SDRDATA_S_RESET 0x0 3295 #define ALT_L3_SEC_SDRDATA_S_GET(value) (((value) & 0x00000001) >> 0) 3297 #define ALT_L3_SEC_SDRDATA_S_SET(value) (((value) << 0) & 0x00000001) 3299 #ifndef __ASSEMBLY__ 3321 #define ALT_L3_SEC_SDRDATA_OFST 0x98 3323 #ifndef __ASSEMBLY__ 3336 volatile ALT_L3_SEC_L4MAIN_t l4main;
3337 volatile ALT_L3_SEC_L4SP_t l4sp;
3338 volatile ALT_L3_SEC_L4MP_t l4mp;
3339 volatile ALT_L3_SEC_L4OSC1_t l4osc1;
3340 volatile ALT_L3_SEC_L4SPIM_t l4spim;
3341 volatile ALT_L3_SEC_STM_t stm;
3342 volatile ALT_L3_SEC_LWH2F_t lwhps2fpgaregs;
3343 volatile uint32_t _pad_0x1c_0x1f;
3344 volatile ALT_L3_SEC_USB1_t usb1;
3345 volatile ALT_L3_SEC_NANDDATA_t nanddata;
3346 volatile uint32_t _pad_0x28_0x77[20];
3347 volatile ALT_L3_SEC_USB0_t usb0;
3348 volatile ALT_L3_SEC_NAND_t nandregs;
3349 volatile ALT_L3_SEC_QSPIDATA_t qspidata;
3350 volatile ALT_L3_SEC_FPGAMGRDATA_t fpgamgrdata;
3351 volatile ALT_L3_SEC_H2F_t hps2fpgaregs;
3352 volatile ALT_L3_SEC_ACP_t acp;
3353 volatile ALT_L3_SEC_ROM_t rom;
3354 volatile ALT_L3_SEC_OCRAM_t ocram;
3355 volatile ALT_L3_SEC_SDRDATA_t sdrdata;
3363 volatile uint32_t l4main;
3364 volatile uint32_t l4sp;
3365 volatile uint32_t l4mp;
3366 volatile uint32_t l4osc1;
3367 volatile uint32_t l4spim;
3368 volatile uint32_t stm;
3369 volatile uint32_t lwhps2fpgaregs;
3370 volatile uint32_t _pad_0x1c_0x1f;
3371 volatile uint32_t usb1;
3372 volatile uint32_t nanddata;
3373 volatile uint32_t _pad_0x28_0x77[20];
3374 volatile uint32_t usb0;
3375 volatile uint32_t nandregs;
3376 volatile uint32_t qspidata;
3377 volatile uint32_t fpgamgrdata;
3378 volatile uint32_t hps2fpgaregs;
3379 volatile uint32_t acp;
3380 volatile uint32_t rom;
3381 volatile uint32_t ocram;
3382 volatile uint32_t sdrdata;
3419 #define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_LSB 0 3421 #define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_MSB 7 3423 #define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_WIDTH 8 3425 #define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_SET_MSK 0x000000ff 3427 #define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_CLR_MSK 0xffffff00 3429 #define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_RESET 0x4 3431 #define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_GET(value) (((value) & 0x000000ff) >> 0) 3433 #define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_SET(value) (((value) << 0) & 0x000000ff) 3435 #ifndef __ASSEMBLY__ 3448 const uint32_t periph_id_4 : 8;
3457 #define ALT_L3_ID_PERIPH_ID_4_OFST 0xfd0 3481 #define ALT_L3_ID_PERIPH_ID_0_PN7TO0_LSB 0 3483 #define ALT_L3_ID_PERIPH_ID_0_PN7TO0_MSB 7 3485 #define ALT_L3_ID_PERIPH_ID_0_PN7TO0_WIDTH 8 3487 #define ALT_L3_ID_PERIPH_ID_0_PN7TO0_SET_MSK 0x000000ff 3489 #define ALT_L3_ID_PERIPH_ID_0_PN7TO0_CLR_MSK 0xffffff00 3491 #define ALT_L3_ID_PERIPH_ID_0_PN7TO0_RESET 0x1 3493 #define ALT_L3_ID_PERIPH_ID_0_PN7TO0_GET(value) (((value) & 0x000000ff) >> 0) 3495 #define ALT_L3_ID_PERIPH_ID_0_PN7TO0_SET(value) (((value) << 0) & 0x000000ff) 3497 #ifndef __ASSEMBLY__ 3510 const uint32_t pn7to0 : 8;
3519 #define ALT_L3_ID_PERIPH_ID_0_OFST 0xfe0 3543 #define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_LSB 0 3545 #define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_MSB 7 3547 #define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_WIDTH 8 3549 #define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_SET_MSK 0x000000ff 3551 #define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_CLR_MSK 0xffffff00 3553 #define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_RESET 0xb3 3555 #define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_GET(value) (((value) & 0x000000ff) >> 0) 3557 #define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_SET(value) (((value) << 0) & 0x000000ff) 3559 #ifndef __ASSEMBLY__ 3572 const uint32_t jep3to0_pn11to8 : 8;
3581 #define ALT_L3_ID_PERIPH_ID_1_OFST 0xfe4 3605 #define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_LSB 0 3607 #define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_MSB 7 3609 #define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_WIDTH 8 3611 #define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_SET_MSK 0x000000ff 3613 #define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_CLR_MSK 0xffffff00 3615 #define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_RESET 0x6b 3617 #define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_GET(value) (((value) & 0x000000ff) >> 0) 3619 #define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_SET(value) (((value) << 0) & 0x000000ff) 3621 #ifndef __ASSEMBLY__ 3634 const uint32_t rev_jepcode_jep6to4 : 8;
3643 #define ALT_L3_ID_PERIPH_ID_2_OFST 0xfe8 3668 #define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_LSB 0 3670 #define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_MSB 3 3672 #define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_WIDTH 4 3674 #define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_SET_MSK 0x0000000f 3676 #define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_CLR_MSK 0xfffffff0 3678 #define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_RESET 0x0 3680 #define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_GET(value) (((value) & 0x0000000f) >> 0) 3682 #define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_SET(value) (((value) << 0) & 0x0000000f) 3693 #define ALT_L3_ID_PERIPH_ID_3_REV_AND_LSB 4 3695 #define ALT_L3_ID_PERIPH_ID_3_REV_AND_MSB 7 3697 #define ALT_L3_ID_PERIPH_ID_3_REV_AND_WIDTH 4 3699 #define ALT_L3_ID_PERIPH_ID_3_REV_AND_SET_MSK 0x000000f0 3701 #define ALT_L3_ID_PERIPH_ID_3_REV_AND_CLR_MSK 0xffffff0f 3703 #define ALT_L3_ID_PERIPH_ID_3_REV_AND_RESET 0x0 3705 #define ALT_L3_ID_PERIPH_ID_3_REV_AND_GET(value) (((value) & 0x000000f0) >> 4) 3707 #define ALT_L3_ID_PERIPH_ID_3_REV_AND_SET(value) (((value) << 4) & 0x000000f0) 3709 #ifndef __ASSEMBLY__ 3722 const uint32_t cust_mod_num : 4;
3723 const uint32_t rev_and : 4;
3732 #define ALT_L3_ID_PERIPH_ID_3_OFST 0xfec 3756 #define ALT_L3_ID_COMP_ID_0_PREAMBLE_LSB 0 3758 #define ALT_L3_ID_COMP_ID_0_PREAMBLE_MSB 7 3760 #define ALT_L3_ID_COMP_ID_0_PREAMBLE_WIDTH 8 3762 #define ALT_L3_ID_COMP_ID_0_PREAMBLE_SET_MSK 0x000000ff 3764 #define ALT_L3_ID_COMP_ID_0_PREAMBLE_CLR_MSK 0xffffff00 3766 #define ALT_L3_ID_COMP_ID_0_PREAMBLE_RESET 0xd 3768 #define ALT_L3_ID_COMP_ID_0_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0) 3770 #define ALT_L3_ID_COMP_ID_0_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff) 3772 #ifndef __ASSEMBLY__ 3785 const uint32_t preamble : 8;
3794 #define ALT_L3_ID_COMP_ID_0_OFST 0xff0 3818 #define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_LSB 0 3820 #define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_MSB 7 3822 #define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_WIDTH 8 3824 #define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_SET_MSK 0x000000ff 3826 #define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_CLR_MSK 0xffffff00 3828 #define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_RESET 0xf0 3830 #define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0) 3832 #define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff) 3834 #ifndef __ASSEMBLY__ 3847 const uint32_t genipcompcls_preamble : 8;
3856 #define ALT_L3_ID_COMP_ID_1_OFST 0xff4 3880 #define ALT_L3_ID_COMP_ID_2_PREAMBLE_LSB 0 3882 #define ALT_L3_ID_COMP_ID_2_PREAMBLE_MSB 7 3884 #define ALT_L3_ID_COMP_ID_2_PREAMBLE_WIDTH 8 3886 #define ALT_L3_ID_COMP_ID_2_PREAMBLE_SET_MSK 0x000000ff 3888 #define ALT_L3_ID_COMP_ID_2_PREAMBLE_CLR_MSK 0xffffff00 3890 #define ALT_L3_ID_COMP_ID_2_PREAMBLE_RESET 0x5 3892 #define ALT_L3_ID_COMP_ID_2_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0) 3894 #define ALT_L3_ID_COMP_ID_2_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff) 3896 #ifndef __ASSEMBLY__ 3909 const uint32_t preamble : 8;
3918 #define ALT_L3_ID_COMP_ID_2_OFST 0xff8 3942 #define ALT_L3_ID_COMP_ID_3_PREAMBLE_LSB 0 3944 #define ALT_L3_ID_COMP_ID_3_PREAMBLE_MSB 7 3946 #define ALT_L3_ID_COMP_ID_3_PREAMBLE_WIDTH 8 3948 #define ALT_L3_ID_COMP_ID_3_PREAMBLE_SET_MSK 0x000000ff 3950 #define ALT_L3_ID_COMP_ID_3_PREAMBLE_CLR_MSK 0xffffff00 3952 #define ALT_L3_ID_COMP_ID_3_PREAMBLE_RESET 0xb1 3954 #define ALT_L3_ID_COMP_ID_3_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0) 3956 #define ALT_L3_ID_COMP_ID_3_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff) 3958 #ifndef __ASSEMBLY__ 3971 const uint32_t preamble : 8;
3980 #define ALT_L3_ID_COMP_ID_3_OFST 0xffc 3982 #ifndef __ASSEMBLY__ 3995 volatile uint32_t _pad_0x0_0xfcf[1012];
3996 volatile ALT_L3_ID_PERIPH_ID_4_t periph_id_4;
3997 volatile uint32_t _pad_0xfd4_0xfdf[3];
3998 volatile ALT_L3_ID_PERIPH_ID_0_t periph_id_0;
3999 volatile ALT_L3_ID_PERIPH_ID_1_t periph_id_1;
4000 volatile ALT_L3_ID_PERIPH_ID_2_t periph_id_2;
4001 volatile ALT_L3_ID_PERIPH_ID_3_t periph_id_3;
4002 volatile ALT_L3_ID_COMP_ID_0_t comp_id_0;
4003 volatile ALT_L3_ID_COMP_ID_1_t comp_id_1;
4004 volatile ALT_L3_ID_COMP_ID_2_t comp_id_2;
4005 volatile ALT_L3_ID_COMP_ID_3_t comp_id_3;
4013 volatile uint32_t _pad_0x0_0xfcf[1012];
4014 volatile uint32_t periph_id_4;
4015 volatile uint32_t _pad_0xfd4_0xfdf[3];
4016 volatile uint32_t periph_id_0;
4017 volatile uint32_t periph_id_1;
4018 volatile uint32_t periph_id_2;
4019 volatile uint32_t periph_id_3;
4020 volatile uint32_t comp_id_0;
4021 volatile uint32_t comp_id_1;
4022 volatile uint32_t comp_id_2;
4023 volatile uint32_t comp_id_3;
4080 #define ALT_L3_FN_MOD_BM_ISS_RD_E_MULT 0x0 4086 #define ALT_L3_FN_MOD_BM_ISS_RD_E_SINGLE 0x1 4089 #define ALT_L3_FN_MOD_BM_ISS_RD_LSB 0 4091 #define ALT_L3_FN_MOD_BM_ISS_RD_MSB 0 4093 #define ALT_L3_FN_MOD_BM_ISS_RD_WIDTH 1 4095 #define ALT_L3_FN_MOD_BM_ISS_RD_SET_MSK 0x00000001 4097 #define ALT_L3_FN_MOD_BM_ISS_RD_CLR_MSK 0xfffffffe 4099 #define ALT_L3_FN_MOD_BM_ISS_RD_RESET 0x0 4101 #define ALT_L3_FN_MOD_BM_ISS_RD_GET(value) (((value) & 0x00000001) >> 0) 4103 #define ALT_L3_FN_MOD_BM_ISS_RD_SET(value) (((value) << 0) & 0x00000001) 4123 #define ALT_L3_FN_MOD_BM_ISS_WR_E_MULT 0x0 4129 #define ALT_L3_FN_MOD_BM_ISS_WR_E_SINGLE 0x1 4132 #define ALT_L3_FN_MOD_BM_ISS_WR_LSB 1 4134 #define ALT_L3_FN_MOD_BM_ISS_WR_MSB 1 4136 #define ALT_L3_FN_MOD_BM_ISS_WR_WIDTH 1 4138 #define ALT_L3_FN_MOD_BM_ISS_WR_SET_MSK 0x00000002 4140 #define ALT_L3_FN_MOD_BM_ISS_WR_CLR_MSK 0xfffffffd 4142 #define ALT_L3_FN_MOD_BM_ISS_WR_RESET 0x0 4144 #define ALT_L3_FN_MOD_BM_ISS_WR_GET(value) (((value) & 0x00000002) >> 1) 4146 #define ALT_L3_FN_MOD_BM_ISS_WR_SET(value) (((value) << 1) & 0x00000002) 4148 #ifndef __ASSEMBLY__ 4171 #define ALT_L3_FN_MOD_BM_ISS_OFST 0x8 4173 #define ALT_L3_FN_MOD_BM_ISS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_FN_MOD_BM_ISS_OFST)) 4175 #ifndef __ASSEMBLY__ 4188 volatile uint32_t _pad_0x0_0x7[2];
4189 volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss;
4197 volatile uint32_t _pad_0x0_0x7[2];
4198 volatile uint32_t fn_mod_bm_iss;
4214 #ifndef __ASSEMBLY__ 4227 volatile uint32_t _pad_0x0_0x7[2];
4228 volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss;
4236 volatile uint32_t _pad_0x0_0x7[2];
4237 volatile uint32_t fn_mod_bm_iss;
4253 #ifndef __ASSEMBLY__ 4266 volatile uint32_t _pad_0x0_0x7[2];
4267 volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss;
4275 volatile uint32_t _pad_0x0_0x7[2];
4276 volatile uint32_t fn_mod_bm_iss;
4292 #ifndef __ASSEMBLY__ 4305 volatile uint32_t _pad_0x0_0x7[2];
4306 volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss;
4314 volatile uint32_t _pad_0x0_0x7[2];
4315 volatile uint32_t fn_mod_bm_iss;
4331 #ifndef __ASSEMBLY__ 4344 volatile uint32_t _pad_0x0_0x7[2];
4345 volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss;
4353 volatile uint32_t _pad_0x0_0x7[2];
4354 volatile uint32_t fn_mod_bm_iss;
4403 #define ALT_L3_FN_MOD_RD_E_MULT 0x0 4409 #define ALT_L3_FN_MOD_RD_E_SINGLE 0x1 4412 #define ALT_L3_FN_MOD_RD_LSB 0 4414 #define ALT_L3_FN_MOD_RD_MSB 0 4416 #define ALT_L3_FN_MOD_RD_WIDTH 1 4418 #define ALT_L3_FN_MOD_RD_SET_MSK 0x00000001 4420 #define ALT_L3_FN_MOD_RD_CLR_MSK 0xfffffffe 4422 #define ALT_L3_FN_MOD_RD_RESET 0x0 4424 #define ALT_L3_FN_MOD_RD_GET(value) (((value) & 0x00000001) >> 0) 4426 #define ALT_L3_FN_MOD_RD_SET(value) (((value) << 0) & 0x00000001) 4446 #define ALT_L3_FN_MOD_WR_E_MULT 0x0 4452 #define ALT_L3_FN_MOD_WR_E_SINGLE 0x1 4455 #define ALT_L3_FN_MOD_WR_LSB 1 4457 #define ALT_L3_FN_MOD_WR_MSB 1 4459 #define ALT_L3_FN_MOD_WR_WIDTH 1 4461 #define ALT_L3_FN_MOD_WR_SET_MSK 0x00000002 4463 #define ALT_L3_FN_MOD_WR_CLR_MSK 0xfffffffd 4465 #define ALT_L3_FN_MOD_WR_RESET 0x0 4467 #define ALT_L3_FN_MOD_WR_GET(value) (((value) & 0x00000002) >> 1) 4469 #define ALT_L3_FN_MOD_WR_SET(value) (((value) << 1) & 0x00000002) 4471 #ifndef __ASSEMBLY__ 4494 #define ALT_L3_FN_MOD_OFST 0x108 4496 #define ALT_L3_FN_MOD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_FN_MOD_OFST)) 4498 #ifndef __ASSEMBLY__ 4511 volatile uint32_t _pad_0x0_0x7[2];
4512 volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss;
4513 volatile uint32_t _pad_0xc_0x107[63];
4514 volatile ALT_L3_FN_MOD_t fn_mod;
4522 volatile uint32_t _pad_0x0_0x7[2];
4523 volatile uint32_t fn_mod_bm_iss;
4524 volatile uint32_t _pad_0xc_0x107[63];
4525 volatile uint32_t fn_mod;
4543 #ifndef __ASSEMBLY__ 4556 volatile uint32_t _pad_0x0_0x7[2];
4557 volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss;
4558 volatile uint32_t _pad_0xc_0x107[63];
4559 volatile ALT_L3_FN_MOD_t fn_mod;
4567 volatile uint32_t _pad_0x0_0x7[2];
4568 volatile uint32_t fn_mod_bm_iss;
4569 volatile uint32_t _pad_0xc_0x107[63];
4570 volatile uint32_t fn_mod;
4621 #define ALT_L3_AHB_CNTL_DECERR_EN_E_DIS 0x0 4628 #define ALT_L3_AHB_CNTL_DECERR_EN_E_EN 0x1 4631 #define ALT_L3_AHB_CNTL_DECERR_EN_LSB 0 4633 #define ALT_L3_AHB_CNTL_DECERR_EN_MSB 0 4635 #define ALT_L3_AHB_CNTL_DECERR_EN_WIDTH 1 4637 #define ALT_L3_AHB_CNTL_DECERR_EN_SET_MSK 0x00000001 4639 #define ALT_L3_AHB_CNTL_DECERR_EN_CLR_MSK 0xfffffffe 4641 #define ALT_L3_AHB_CNTL_DECERR_EN_RESET 0x0 4643 #define ALT_L3_AHB_CNTL_DECERR_EN_GET(value) (((value) & 0x00000001) >> 0) 4645 #define ALT_L3_AHB_CNTL_DECERR_EN_SET(value) (((value) << 0) & 0x00000001) 4669 #define ALT_L3_AHB_CNTL_FORCE_INCR_E_DIS 0x0 4677 #define ALT_L3_AHB_CNTL_FORCE_INCR_E_EN 0x1 4680 #define ALT_L3_AHB_CNTL_FORCE_INCR_LSB 1 4682 #define ALT_L3_AHB_CNTL_FORCE_INCR_MSB 1 4684 #define ALT_L3_AHB_CNTL_FORCE_INCR_WIDTH 1 4686 #define ALT_L3_AHB_CNTL_FORCE_INCR_SET_MSK 0x00000002 4688 #define ALT_L3_AHB_CNTL_FORCE_INCR_CLR_MSK 0xfffffffd 4690 #define ALT_L3_AHB_CNTL_FORCE_INCR_RESET 0x0 4692 #define ALT_L3_AHB_CNTL_FORCE_INCR_GET(value) (((value) & 0x00000002) >> 1) 4694 #define ALT_L3_AHB_CNTL_FORCE_INCR_SET(value) (((value) << 1) & 0x00000002) 4696 #ifndef __ASSEMBLY__ 4709 uint32_t decerr_en : 1;
4710 uint32_t force_incr : 1;
4719 #define ALT_L3_AHB_CNTL_OFST 0x44 4721 #define ALT_L3_AHB_CNTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_AHB_CNTL_OFST)) 4723 #ifndef __ASSEMBLY__ 4736 volatile uint32_t _pad_0x0_0x7[2];
4737 volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss;
4738 volatile uint32_t _pad_0xc_0x43[14];
4739 volatile ALT_L3_AHB_CNTL_t ahb_cntl;
4747 volatile uint32_t _pad_0x0_0x7[2];
4748 volatile uint32_t fn_mod_bm_iss;
4749 volatile uint32_t _pad_0xc_0x43[14];
4750 volatile uint32_t ahb_cntl;
4766 #ifndef __ASSEMBLY__ 4779 volatile uint32_t _pad_0x0_0x7[2];
4780 volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss;
4781 volatile uint32_t _pad_0xc_0x107[63];
4782 volatile ALT_L3_FN_MOD_t fn_mod;
4790 volatile uint32_t _pad_0x0_0x7[2];
4791 volatile uint32_t fn_mod_bm_iss;
4792 volatile uint32_t _pad_0xc_0x107[63];
4793 volatile uint32_t fn_mod;
4809 #ifndef __ASSEMBLY__ 4822 volatile uint32_t _pad_0x0_0x7[2];
4823 volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss;
4824 volatile uint32_t _pad_0xc_0x43[14];
4825 volatile ALT_L3_AHB_CNTL_t ahb_cntl;
4833 volatile uint32_t _pad_0x0_0x7[2];
4834 volatile uint32_t fn_mod_bm_iss;
4835 volatile uint32_t _pad_0xc_0x43[14];
4836 volatile uint32_t ahb_cntl;
4852 #ifndef __ASSEMBLY__ 4865 volatile uint32_t _pad_0x0_0x7[2];
4866 volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss;
4867 volatile uint32_t _pad_0xc_0x107[63];
4868 volatile ALT_L3_FN_MOD_t fn_mod;
4876 volatile uint32_t _pad_0x0_0x7[2];
4877 volatile uint32_t fn_mod_bm_iss;
4878 volatile uint32_t _pad_0xc_0x107[63];
4879 volatile uint32_t fn_mod;
4895 #ifndef __ASSEMBLY__ 4908 volatile uint32_t _pad_0x0_0x7[2];
4909 volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss;
4910 volatile uint32_t _pad_0xc_0x43[14];
4911 volatile ALT_L3_AHB_CNTL_t ahb_cntl;
4919 volatile uint32_t _pad_0x0_0x7[2];
4920 volatile uint32_t fn_mod_bm_iss;
4921 volatile uint32_t _pad_0xc_0x43[14];
4922 volatile uint32_t ahb_cntl;
4963 #define ALT_L3_WR_TIDEMARK_LEVEL_LSB 0 4965 #define ALT_L3_WR_TIDEMARK_LEVEL_MSB 3 4967 #define ALT_L3_WR_TIDEMARK_LEVEL_WIDTH 4 4969 #define ALT_L3_WR_TIDEMARK_LEVEL_SET_MSK 0x0000000f 4971 #define ALT_L3_WR_TIDEMARK_LEVEL_CLR_MSK 0xfffffff0 4973 #define ALT_L3_WR_TIDEMARK_LEVEL_RESET 0x4 4975 #define ALT_L3_WR_TIDEMARK_LEVEL_GET(value) (((value) & 0x0000000f) >> 0) 4977 #define ALT_L3_WR_TIDEMARK_LEVEL_SET(value) (((value) << 0) & 0x0000000f) 4979 #ifndef __ASSEMBLY__ 5001 #define ALT_L3_WR_TIDEMARK_OFST 0x40 5003 #define ALT_L3_WR_TIDEMARK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_WR_TIDEMARK_OFST)) 5005 #ifndef __ASSEMBLY__ 5018 volatile uint32_t _pad_0x0_0x7[2];
5019 volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss;
5020 volatile uint32_t _pad_0xc_0x3f[13];
5021 volatile ALT_L3_WR_TIDEMARK_t wr_tidemark;
5022 volatile uint32_t _pad_0x44_0x107[49];
5023 volatile ALT_L3_FN_MOD_t fn_mod;
5031 volatile uint32_t _pad_0x0_0x7[2];
5032 volatile uint32_t fn_mod_bm_iss;
5033 volatile uint32_t _pad_0xc_0x3f[13];
5034 volatile uint32_t wr_tidemark;
5035 volatile uint32_t _pad_0x44_0x107[49];
5036 volatile uint32_t fn_mod;
5053 #ifndef __ASSEMBLY__ 5066 volatile uint32_t _pad_0x0_0x7[2];
5067 volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss;
5068 volatile uint32_t _pad_0xc_0x3f[13];
5069 volatile ALT_L3_WR_TIDEMARK_t wr_tidemark;
5070 volatile uint32_t _pad_0x44_0x107[49];
5071 volatile ALT_L3_FN_MOD_t fn_mod;
5079 volatile uint32_t _pad_0x0_0x7[2];
5080 volatile uint32_t fn_mod_bm_iss;
5081 volatile uint32_t _pad_0xc_0x3f[13];
5082 volatile uint32_t wr_tidemark;
5083 volatile uint32_t _pad_0x44_0x107[49];
5084 volatile uint32_t fn_mod;
5100 #ifndef __ASSEMBLY__ 5113 volatile uint32_t _pad_0x0_0x7[2];
5114 volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss;
5115 volatile uint32_t _pad_0xc_0x107[63];
5116 volatile ALT_L3_FN_MOD_t fn_mod;
5124 volatile uint32_t _pad_0x0_0x7[2];
5125 volatile uint32_t fn_mod_bm_iss;
5126 volatile uint32_t _pad_0xc_0x107[63];
5127 volatile uint32_t fn_mod;
5143 #ifndef __ASSEMBLY__ 5156 volatile uint32_t _pad_0x0_0x7[2];
5157 volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss;
5158 volatile uint32_t _pad_0xc_0x107[63];
5159 volatile ALT_L3_FN_MOD_t fn_mod;
5167 volatile uint32_t _pad_0x0_0x7[2];
5168 volatile uint32_t fn_mod_bm_iss;
5169 volatile uint32_t _pad_0xc_0x107[63];
5170 volatile uint32_t fn_mod;
5186 #ifndef __ASSEMBLY__ 5199 volatile uint32_t _pad_0x0_0x7[2];
5200 volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss;
5201 volatile uint32_t _pad_0xc_0x3f[13];
5202 volatile ALT_L3_WR_TIDEMARK_t wr_tidemark;
5203 volatile uint32_t _pad_0x44_0x107[49];
5204 volatile ALT_L3_FN_MOD_t fn_mod;
5212 volatile uint32_t _pad_0x0_0x7[2];
5213 volatile uint32_t fn_mod_bm_iss;
5214 volatile uint32_t _pad_0xc_0x3f[13];
5215 volatile uint32_t wr_tidemark;
5216 volatile uint32_t _pad_0x44_0x107[49];
5217 volatile uint32_t fn_mod;
5225 #ifndef __ASSEMBLY__ 5238 volatile ALT_L3_MST_L4MAIN_t mastergrp_l4main;
5239 volatile uint32_t _pad_0xc_0xfff[1021];
5240 volatile ALT_L3_MST_L4SP_t mastergrp_l4sp;
5241 volatile uint32_t _pad_0x100c_0x1fff[1021];
5242 volatile ALT_L3_MST_L4MP_t mastergrp_l4mp;
5243 volatile uint32_t _pad_0x200c_0x2fff[1021];
5244 volatile ALT_L3_MST_L4OSC1_t mastergrp_l4osc1;
5245 volatile uint32_t _pad_0x300c_0x3fff[1021];
5246 volatile ALT_L3_MST_L4SPIM_t mastergrp_l4spim;
5247 volatile uint32_t _pad_0x400c_0x4fff[1021];
5248 volatile ALT_L3_MST_STM_t mastergrp_stm;
5249 volatile uint32_t _pad_0x510c_0x5fff[957];
5250 volatile ALT_L3_MST_LWH2F_t mastergrp_lwhps2fpga;
5251 volatile uint32_t _pad_0x610c_0x7fff[1981];
5252 volatile ALT_L3_MST_USB1_t mastergrp_usb1;
5253 volatile uint32_t _pad_0x8048_0x8fff[1006];
5254 volatile ALT_L3_MST_NANDDATA_t mastergrp_nanddata;
5255 volatile uint32_t _pad_0x910c_0x1dfff[21437];
5256 volatile ALT_L3_MST_USB0_t mastergrp_usb0;
5257 volatile uint32_t _pad_0x1e048_0x1efff[1006];
5258 volatile ALT_L3_MST_NAND_t mastergrp_nandregs;
5259 volatile uint32_t _pad_0x1f10c_0x1ffff[957];
5260 volatile ALT_L3_MST_QSPIDATA_t mastergrp_qspidata;
5261 volatile uint32_t _pad_0x20048_0x20fff[1006];
5262 volatile ALT_L3_MST_FPGAMGRDATA_t mastergrp_fpgamgrdata;
5263 volatile uint32_t _pad_0x2110c_0x21fff[957];
5264 volatile ALT_L3_MST_H2F_t mastergrp_hps2fpga;
5265 volatile uint32_t _pad_0x2210c_0x22fff[957];
5266 volatile ALT_L3_MST_ACP_t mastergrp_acp;
5267 volatile uint32_t _pad_0x2310c_0x23fff[957];
5268 volatile ALT_L3_MST_ROM_t mastergrp_rom;
5269 volatile uint32_t _pad_0x2410c_0x24fff[957];
5270 volatile ALT_L3_MST_OCRAM_t mastergrp_ocram;
5278 volatile ALT_L3_MST_L4MAIN_raw_t mastergrp_l4main;
5279 volatile uint32_t _pad_0xc_0xfff[1021];
5280 volatile ALT_L3_MST_L4SP_raw_t mastergrp_l4sp;
5281 volatile uint32_t _pad_0x100c_0x1fff[1021];
5282 volatile ALT_L3_MST_L4MP_raw_t mastergrp_l4mp;
5283 volatile uint32_t _pad_0x200c_0x2fff[1021];
5284 volatile ALT_L3_MST_L4OSC1_raw_t mastergrp_l4osc1;
5285 volatile uint32_t _pad_0x300c_0x3fff[1021];
5286 volatile ALT_L3_MST_L4SPIM_raw_t mastergrp_l4spim;
5287 volatile uint32_t _pad_0x400c_0x4fff[1021];
5288 volatile ALT_L3_MST_STM_raw_t mastergrp_stm;
5289 volatile uint32_t _pad_0x510c_0x5fff[957];
5290 volatile ALT_L3_MST_LWH2F_raw_t mastergrp_lwhps2fpga;
5291 volatile uint32_t _pad_0x610c_0x7fff[1981];
5292 volatile ALT_L3_MST_USB1_raw_t mastergrp_usb1;
5293 volatile uint32_t _pad_0x8048_0x8fff[1006];
5294 volatile ALT_L3_MST_NANDDATA_raw_t mastergrp_nanddata;
5295 volatile uint32_t _pad_0x910c_0x1dfff[21437];
5296 volatile ALT_L3_MST_USB0_raw_t mastergrp_usb0;
5297 volatile uint32_t _pad_0x1e048_0x1efff[1006];
5298 volatile ALT_L3_MST_NAND_raw_t mastergrp_nandregs;
5299 volatile uint32_t _pad_0x1f10c_0x1ffff[957];
5300 volatile ALT_L3_MST_QSPIDATA_raw_t mastergrp_qspidata;
5301 volatile uint32_t _pad_0x20048_0x20fff[1006];
5302 volatile ALT_L3_MST_FPGAMGRDATA_raw_t mastergrp_fpgamgrdata;
5303 volatile uint32_t _pad_0x2110c_0x21fff[957];
5304 volatile ALT_L3_MST_H2F_raw_t mastergrp_hps2fpga;
5305 volatile uint32_t _pad_0x2210c_0x22fff[957];
5306 volatile ALT_L3_MST_ACP_raw_t mastergrp_acp;
5307 volatile uint32_t _pad_0x2310c_0x23fff[957];
5308 volatile ALT_L3_MST_ROM_raw_t mastergrp_rom;
5309 volatile uint32_t _pad_0x2410c_0x24fff[957];
5310 volatile ALT_L3_MST_OCRAM_raw_t mastergrp_ocram;
5368 #define ALT_L3_FN_MOD2_BYPASS_MERGE_E_ALTER 0x0 5375 #define ALT_L3_FN_MOD2_BYPASS_MERGE_E_NOALTER 0x1 5378 #define ALT_L3_FN_MOD2_BYPASS_MERGE_LSB 0 5380 #define ALT_L3_FN_MOD2_BYPASS_MERGE_MSB 0 5382 #define ALT_L3_FN_MOD2_BYPASS_MERGE_WIDTH 1 5384 #define ALT_L3_FN_MOD2_BYPASS_MERGE_SET_MSK 0x00000001 5386 #define ALT_L3_FN_MOD2_BYPASS_MERGE_CLR_MSK 0xfffffffe 5388 #define ALT_L3_FN_MOD2_BYPASS_MERGE_RESET 0x0 5390 #define ALT_L3_FN_MOD2_BYPASS_MERGE_GET(value) (((value) & 0x00000001) >> 0) 5392 #define ALT_L3_FN_MOD2_BYPASS_MERGE_SET(value) (((value) << 0) & 0x00000001) 5394 #ifndef __ASSEMBLY__ 5407 uint32_t bypass_merge : 1;
5416 #define ALT_L3_FN_MOD2_OFST 0x24 5418 #define ALT_L3_FN_MOD2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_FN_MOD2_OFST)) 5460 #define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_E_DEFAULT 0x0 5466 #define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_E_SINGLES 0x1 5469 #define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_LSB 0 5471 #define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_MSB 0 5473 #define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_WIDTH 1 5475 #define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_SET_MSK 0x00000001 5477 #define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_CLR_MSK 0xfffffffe 5479 #define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_RESET 0x0 5481 #define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_GET(value) (((value) & 0x00000001) >> 0) 5483 #define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_SET(value) (((value) << 0) & 0x00000001) 5511 #define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_E_DEFAULT 0x0 5517 #define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_E_SINGLES 0x1 5520 #define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_LSB 1 5522 #define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_MSB 1 5524 #define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_WIDTH 1 5526 #define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_SET_MSK 0x00000002 5528 #define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_CLR_MSK 0xfffffffd 5530 #define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_RESET 0x0 5532 #define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_GET(value) (((value) & 0x00000002) >> 1) 5534 #define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_SET(value) (((value) << 1) & 0x00000002) 5536 #ifndef __ASSEMBLY__ 5549 uint32_t rd_incr_override : 1;
5550 uint32_t wr_incr_override : 1;
5559 #define ALT_L3_FN_MOD_AHB_OFST 0x28 5561 #define ALT_L3_FN_MOD_AHB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_FN_MOD_AHB_OFST)) 5586 #define ALT_L3_RD_QOS_PRI_LSB 0 5588 #define ALT_L3_RD_QOS_PRI_MSB 3 5590 #define ALT_L3_RD_QOS_PRI_WIDTH 4 5592 #define ALT_L3_RD_QOS_PRI_SET_MSK 0x0000000f 5594 #define ALT_L3_RD_QOS_PRI_CLR_MSK 0xfffffff0 5596 #define ALT_L3_RD_QOS_PRI_RESET 0x0 5598 #define ALT_L3_RD_QOS_PRI_GET(value) (((value) & 0x0000000f) >> 0) 5600 #define ALT_L3_RD_QOS_PRI_SET(value) (((value) << 0) & 0x0000000f) 5602 #ifndef __ASSEMBLY__ 5624 #define ALT_L3_RD_QOS_OFST 0x100 5626 #define ALT_L3_RD_QOS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_RD_QOS_OFST)) 5651 #define ALT_L3_WR_QOS_PRI_LSB 0 5653 #define ALT_L3_WR_QOS_PRI_MSB 3 5655 #define ALT_L3_WR_QOS_PRI_WIDTH 4 5657 #define ALT_L3_WR_QOS_PRI_SET_MSK 0x0000000f 5659 #define ALT_L3_WR_QOS_PRI_CLR_MSK 0xfffffff0 5661 #define ALT_L3_WR_QOS_PRI_RESET 0x0 5663 #define ALT_L3_WR_QOS_PRI_GET(value) (((value) & 0x0000000f) >> 0) 5665 #define ALT_L3_WR_QOS_PRI_SET(value) (((value) << 0) & 0x0000000f) 5667 #ifndef __ASSEMBLY__ 5689 #define ALT_L3_WR_QOS_OFST 0x104 5691 #define ALT_L3_WR_QOS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_WR_QOS_OFST)) 5693 #ifndef __ASSEMBLY__ 5706 volatile uint32_t _pad_0x0_0x23[9];
5707 volatile ALT_L3_FN_MOD2_t fn_mod2;
5708 volatile ALT_L3_FN_MOD_AHB_t fn_mod_ahb;
5709 volatile uint32_t _pad_0x2c_0xff[53];
5710 volatile ALT_L3_RD_QOS_t read_qos;
5711 volatile ALT_L3_WR_QOS_t write_qos;
5712 volatile ALT_L3_FN_MOD_t fn_mod;
5720 volatile uint32_t _pad_0x0_0x23[9];
5721 volatile uint32_t fn_mod2;
5722 volatile uint32_t fn_mod_ahb;
5723 volatile uint32_t _pad_0x2c_0xff[53];
5724 volatile uint32_t read_qos;
5725 volatile uint32_t write_qos;
5726 volatile uint32_t fn_mod;
5742 #ifndef __ASSEMBLY__ 5755 volatile uint32_t _pad_0x0_0xff[64];
5756 volatile ALT_L3_RD_QOS_t read_qos;
5757 volatile ALT_L3_WR_QOS_t write_qos;
5758 volatile ALT_L3_FN_MOD_t fn_mod;
5766 volatile uint32_t _pad_0x0_0xff[64];
5767 volatile uint32_t read_qos;
5768 volatile uint32_t write_qos;
5769 volatile uint32_t fn_mod;
5786 #ifndef __ASSEMBLY__ 5799 volatile uint32_t _pad_0x0_0x27[10];
5800 volatile ALT_L3_FN_MOD_AHB_t fn_mod_ahb;
5801 volatile uint32_t _pad_0x2c_0xff[53];
5802 volatile ALT_L3_RD_QOS_t read_qos;
5803 volatile ALT_L3_WR_QOS_t write_qos;
5804 volatile ALT_L3_FN_MOD_t fn_mod;
5812 volatile uint32_t _pad_0x0_0x27[10];
5813 volatile uint32_t fn_mod_ahb;
5814 volatile uint32_t _pad_0x2c_0xff[53];
5815 volatile uint32_t read_qos;
5816 volatile uint32_t write_qos;
5817 volatile uint32_t fn_mod;
5833 #ifndef __ASSEMBLY__ 5846 volatile uint32_t _pad_0x0_0xff[64];
5847 volatile ALT_L3_RD_QOS_t read_qos;
5848 volatile ALT_L3_WR_QOS_t write_qos;
5849 volatile ALT_L3_FN_MOD_t fn_mod;
5857 volatile uint32_t _pad_0x0_0xff[64];
5858 volatile uint32_t read_qos;
5859 volatile uint32_t write_qos;
5860 volatile uint32_t fn_mod;
5877 #ifndef __ASSEMBLY__ 5890 volatile uint32_t _pad_0x0_0x3f[16];
5891 volatile ALT_L3_WR_TIDEMARK_t wr_tidemark;
5892 volatile uint32_t _pad_0x44_0xff[47];
5893 volatile ALT_L3_RD_QOS_t read_qos;
5894 volatile ALT_L3_WR_QOS_t write_qos;
5895 volatile ALT_L3_FN_MOD_t fn_mod;
5903 volatile uint32_t _pad_0x0_0x3f[16];
5904 volatile uint32_t wr_tidemark;
5905 volatile uint32_t _pad_0x44_0xff[47];
5906 volatile uint32_t read_qos;
5907 volatile uint32_t write_qos;
5908 volatile uint32_t fn_mod;
5924 #ifndef __ASSEMBLY__ 5937 volatile uint32_t _pad_0x0_0xff[64];
5938 volatile ALT_L3_RD_QOS_t read_qos;
5939 volatile ALT_L3_WR_QOS_t write_qos;
5940 volatile ALT_L3_FN_MOD_t fn_mod;
5948 volatile uint32_t _pad_0x0_0xff[64];
5949 volatile uint32_t read_qos;
5950 volatile uint32_t write_qos;
5951 volatile uint32_t fn_mod;
5968 #ifndef __ASSEMBLY__ 5981 volatile uint32_t _pad_0x0_0xff[64];
5982 volatile ALT_L3_RD_QOS_t read_qos;
5983 volatile ALT_L3_WR_QOS_t write_qos;
5984 volatile ALT_L3_FN_MOD_t fn_mod;
5992 volatile uint32_t _pad_0x0_0xff[64];
5993 volatile uint32_t read_qos;
5994 volatile uint32_t write_qos;
5995 volatile uint32_t fn_mod;
6012 #ifndef __ASSEMBLY__ 6025 volatile uint32_t _pad_0x0_0xff[64];
6026 volatile ALT_L3_RD_QOS_t read_qos;
6027 volatile ALT_L3_WR_QOS_t write_qos;
6028 volatile ALT_L3_FN_MOD_t fn_mod;
6036 volatile uint32_t _pad_0x0_0xff[64];
6037 volatile uint32_t read_qos;
6038 volatile uint32_t write_qos;
6039 volatile uint32_t fn_mod;
6056 #ifndef __ASSEMBLY__ 6069 volatile uint32_t _pad_0x0_0x27[10];
6070 volatile ALT_L3_FN_MOD_AHB_t fn_mod_ahb;
6071 volatile uint32_t _pad_0x2c_0xff[53];
6072 volatile ALT_L3_RD_QOS_t read_qos;
6073 volatile ALT_L3_WR_QOS_t write_qos;
6074 volatile ALT_L3_FN_MOD_t fn_mod;
6082 volatile uint32_t _pad_0x0_0x27[10];
6083 volatile uint32_t fn_mod_ahb;
6084 volatile uint32_t _pad_0x2c_0xff[53];
6085 volatile uint32_t read_qos;
6086 volatile uint32_t write_qos;
6087 volatile uint32_t fn_mod;
6104 #ifndef __ASSEMBLY__ 6117 volatile uint32_t _pad_0x0_0xff[64];
6118 volatile ALT_L3_RD_QOS_t read_qos;
6119 volatile ALT_L3_WR_QOS_t write_qos;
6120 volatile ALT_L3_FN_MOD_t fn_mod;
6128 volatile uint32_t _pad_0x0_0xff[64];
6129 volatile uint32_t read_qos;
6130 volatile uint32_t write_qos;
6131 volatile uint32_t fn_mod;
6148 #ifndef __ASSEMBLY__ 6161 volatile uint32_t _pad_0x0_0x27[10];
6162 volatile ALT_L3_FN_MOD_AHB_t fn_mod_ahb;
6163 volatile uint32_t _pad_0x2c_0xff[53];
6164 volatile ALT_L3_RD_QOS_t read_qos;
6165 volatile ALT_L3_WR_QOS_t write_qos;
6166 volatile ALT_L3_FN_MOD_t fn_mod;
6174 volatile uint32_t _pad_0x0_0x27[10];
6175 volatile uint32_t fn_mod_ahb;
6176 volatile uint32_t _pad_0x2c_0xff[53];
6177 volatile uint32_t read_qos;
6178 volatile uint32_t write_qos;
6179 volatile uint32_t fn_mod;
6187 #ifndef __ASSEMBLY__ 6200 volatile ALT_L3_SLV_DAP_t slavegrp_dap;
6201 volatile uint32_t _pad_0x10c_0xfff[957];
6202 volatile ALT_L3_SLV_MPU_t slavegrp_mpu;
6203 volatile uint32_t _pad_0x110c_0x1fff[957];
6204 volatile ALT_L3_SLV_SDMMC_t slavegrp_sdmmc;
6205 volatile uint32_t _pad_0x210c_0x2fff[957];
6206 volatile ALT_L3_SLV_DMA_t slavegrp_dma;
6207 volatile uint32_t _pad_0x310c_0x3fff[957];
6208 volatile ALT_L3_SLV_F2H_t slavegrp_fpga2hps;
6209 volatile uint32_t _pad_0x410c_0x4fff[957];
6210 volatile ALT_L3_SLV_ETR_t slavegrp_etr;
6211 volatile uint32_t _pad_0x510c_0x5fff[957];
6212 volatile ALT_L3_SLV_EMAC0_t slavegrp_emac0;
6213 volatile uint32_t _pad_0x610c_0x6fff[957];
6214 volatile ALT_L3_SLV_EMAC1_t slavegrp_emac1;
6215 volatile uint32_t _pad_0x710c_0x7fff[957];
6216 volatile ALT_L3_SLV_USB0_t slavegrp_usb0;
6217 volatile uint32_t _pad_0x810c_0x8fff[957];
6218 volatile ALT_L3_SLV_NAND_t slavegrp_nand;
6219 volatile uint32_t _pad_0x910c_0x9fff[957];
6220 volatile ALT_L3_SLV_USB1_t slavegrp_usb1;
6228 volatile ALT_L3_SLV_DAP_raw_t slavegrp_dap;
6229 volatile uint32_t _pad_0x10c_0xfff[957];
6230 volatile ALT_L3_SLV_MPU_raw_t slavegrp_mpu;
6231 volatile uint32_t _pad_0x110c_0x1fff[957];
6232 volatile ALT_L3_SLV_SDMMC_raw_t slavegrp_sdmmc;
6233 volatile uint32_t _pad_0x210c_0x2fff[957];
6234 volatile ALT_L3_SLV_DMA_raw_t slavegrp_dma;
6235 volatile uint32_t _pad_0x310c_0x3fff[957];
6236 volatile ALT_L3_SLV_F2H_raw_t slavegrp_fpga2hps;
6237 volatile uint32_t _pad_0x410c_0x4fff[957];
6238 volatile ALT_L3_SLV_ETR_raw_t slavegrp_etr;
6239 volatile uint32_t _pad_0x510c_0x5fff[957];
6240 volatile ALT_L3_SLV_EMAC0_raw_t slavegrp_emac0;
6241 volatile uint32_t _pad_0x610c_0x6fff[957];
6242 volatile ALT_L3_SLV_EMAC1_raw_t slavegrp_emac1;
6243 volatile uint32_t _pad_0x710c_0x7fff[957];
6244 volatile ALT_L3_SLV_USB0_raw_t slavegrp_usb0;
6245 volatile uint32_t _pad_0x810c_0x8fff[957];
6246 volatile ALT_L3_SLV_NAND_raw_t slavegrp_nand;
6247 volatile uint32_t _pad_0x910c_0x9fff[957];
6248 volatile ALT_L3_SLV_USB1_raw_t slavegrp_usb1;
6256 #ifndef __ASSEMBLY__ 6269 volatile ALT_L3_REMAP_t remap;
6270 volatile uint32_t _pad_0x4_0x7;
6271 volatile ALT_L3_SECGRP_t secgrp;
6272 volatile uint32_t _pad_0xa4_0xfff[983];
6273 volatile ALT_L3_IDGRP_t idgrp;
6274 volatile ALT_L3_MSTGRP_t mastergrp;
6275 volatile uint32_t _pad_0x2710c_0x41fff[27581];
6276 volatile ALT_L3_SLVGRP_t slavegrp;
6277 volatile uint32_t _pad_0x4c10c_0x80000[53181];
6281 typedef volatile struct ALT_L3_s ALT_L3_t;
6285 volatile uint32_t remap;
6286 volatile uint32_t _pad_0x4_0x7;
6287 volatile ALT_L3_SECGRP_raw_t secgrp;
6288 volatile uint32_t _pad_0xa4_0xfff[983];
6289 volatile ALT_L3_IDGRP_raw_t idgrp;
6290 volatile ALT_L3_MSTGRP_raw_t mastergrp;
6291 volatile uint32_t _pad_0x2710c_0x41fff[27581];
6292 volatile ALT_L3_SLVGRP_raw_t slavegrp;
6293 volatile uint32_t _pad_0x4c10c_0x80000[53181];
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