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#define | MIN(a, b) ((a) > (b) ? (b) : (a)) |
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#define | ARRAY_COUNT(array) (sizeof(array) / sizeof(array[0])) |
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#define | dprintf(...) |
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#define | ALT_DMA_DSR_OFST 0x0 |
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#define | ALT_DMA_DSR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_DSR_OFST)) |
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#define | ALT_DMA_DSR_DMASTATUS_SET_MSK 0x0000000f |
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#define | ALT_DMA_DSR_DMASTATUS_GET(value) ((value) & 0x0000000f) |
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#define | ALT_DMA_DPC_OFST 0x4 |
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#define | ALT_DMA_DPC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_DPC_OFST)) |
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#define | ALT_DMA_INTEN_OFST 0x20 |
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#define | ALT_DMA_INTEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_INTEN_OFST)) |
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#define | ALT_DMA_INT_EVENT_RIS_OFST 0x24 |
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#define | ALT_DMA_INT_EVENT_RIS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_INT_EVENT_RIS_OFST)) |
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#define | ALT_DMA_INTMIS_OFST 0x28 |
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#define | ALT_DMA_INTMIS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_INTMIS_OFST)) |
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#define | ALT_DMA_INTCLR_OFST 0x2c |
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#define | ALT_DMA_INTCLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_INTCLR_OFST)) |
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#define | ALT_DMA_FSRD_OFST 0x30 |
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#define | ALT_DMA_FSRD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_FSRD_OFST)) |
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#define | ALT_DMA_FSRC_OFST 0x34 |
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#define | ALT_DMA_FSRC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_FSRC_OFST)) |
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#define | ALT_DMA_FTRD_OFST 0x38 |
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#define | ALT_DMA_FTRD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_FSRD_OFST)) |
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#define | ALT_DMA_FTRx_OFST(channel) (0x40 + 0x4 * (channel)) |
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#define | ALT_DMA_FTRx_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_FTRx_OFST(channel))) |
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#define | ALT_DMA_CSRx_OFST(channel) (0x100 + 0x8 * (channel)) |
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#define | ALT_DMA_CSRx_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CSRx_OFST(channel))) |
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#define | ALT_DMA_CSRx_CHANNELSTATUS_SET_MSK 0x0000000f |
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#define | ALT_DMA_CSRx_CHANNELSTATUS_GET(value) ((value) & 0x0000000f) |
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#define | ALT_DMA_CPCx_OFST(channel) (0x104 + 0x8 * (channel)) |
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#define | ALT_DMA_CPCx_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CPCx_OFST(channel))) |
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#define | ALT_DMA_SARx_OFST(channel) (0x400 + 0x20 * (channel)) |
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#define | ALT_DMA_SARx_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_SARx_OFST(channel))) |
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#define | ALT_DMA_DARx_OFST(channel) (0x404 + 0x20 * (channel)) |
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#define | ALT_DMA_DARx_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_DARx_OFST(channel))) |
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#define | ALT_DMA_CCRx_OFST(channel) (0x408 + 0x20 * (channel)) |
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#define | ALT_DMA_CCRx_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CCRx_OFST(channel))) |
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#define | ALT_DMA_LC0_x_OFST(channel) (0x40c + 0x20 * (channel)) |
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#define | ALT_DMA_LC0_x_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_LC0_x_OFST(channel))) |
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#define | ALT_DMA_LC1_x_OFST(channel) (0x410 + 0x20 * (channel)) |
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#define | ALT_DMA_LC1_x_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_LC1_x_OFST(channel))) |
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#define | ALT_DMA_DBGSTATUS_OFST 0xd00 |
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#define | ALT_DMA_DBGSTATUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_DBGSTATUS_OFST)) |
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#define | ALT_DMA_DBGCMD_OFST 0xd04 |
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#define | ALT_DMA_DBGCMD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_DBGCMD_OFST)) |
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#define | ALT_DMA_DBGINST0_OFST 0xd08 |
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#define | ALT_DMA_DBGINST0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_DBGINST0_OFST)) |
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#define | ALT_DMA_DBGINST0_CHANNELNUMBER_SET(value) (((value) & 0x7) << 8) |
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#define | ALT_DMA_DBGINST0_DEBUGTHREAD_SET(value) ((value) & 0x1) |
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#define | ALT_DMA_DBGINST0_DEBUGTHREAD_E_MANAGER 0 |
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#define | ALT_DMA_DBGINST0_DEBUGTHREAD_E_CHANNEL 1 |
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#define | ALT_DMA_DBGINST0_INSTRUCTIONBYTE0_SET(value) (((value) & 0xff) << 16) |
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#define | ALT_DMA_DBGINST0_INSTRUCTIONBYTE1_SET(value) (((value) & 0xff) << 24) |
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#define | ALT_DMA_DBGINST1_OFST 0xd0c |
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#define | ALT_DMA_DBGINST1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_DBGINST1_OFST)) |
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#define | ALT_DMA_CR0_OFST 0xe00 |
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#define | ALT_DMA_CR1_OFST 0xe04 |
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#define | ALT_DMA_CR2_OFST 0xe08 |
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#define | ALT_DMA_CR3_OFST 0xe0c |
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#define | ALT_DMA_CR4_OFST 0xe10 |
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#define | ALT_DMA_CR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CR0_OFST)) |
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#define | ALT_DMA_CR1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CR1_OFST)) |
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#define | ALT_DMA_CR2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CR2_OFST)) |
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#define | ALT_DMA_CR3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CR3_OFST)) |
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#define | ALT_DMA_CR4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CR4_OFST)) |
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#define | ALT_DMA_CRD_OFST 0xe14 |
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#define | ALT_DMA_CRD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CRD_OFST)) |
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#define | ALT_DMA_WD_OFST 0xe80 |
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#define | ALT_DMA_WD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_WD_OFST)) |
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#define | ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED (1 << 0) |
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ALT_STATUS_CODE | alt_dma_init (const ALT_DMA_CFG_t *dma_cfg) |
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ALT_STATUS_CODE | alt_dma_uninit (void) |
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ALT_STATUS_CODE | alt_dma_channel_alloc (ALT_DMA_CHANNEL_t channel) |
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ALT_STATUS_CODE | alt_dma_channel_alloc_any (ALT_DMA_CHANNEL_t *allocated) |
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ALT_STATUS_CODE | alt_dma_channel_free (ALT_DMA_CHANNEL_t channel) |
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ALT_STATUS_CODE | alt_dma_channel_exec (ALT_DMA_CHANNEL_t channel, ALT_DMA_PROGRAM_t *pgm) |
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ALT_STATUS_CODE | alt_dma_channel_kill (ALT_DMA_CHANNEL_t channel) |
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ALT_STATUS_CODE | alt_dma_channel_reg_get (ALT_DMA_CHANNEL_t channel, ALT_DMA_PROGRAM_REG_t reg, uint32_t *val) |
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ALT_STATUS_CODE | alt_dma_send_event (ALT_DMA_EVENT_t evt_num) |
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ALT_STATUS_CODE | alt_dma_manager_state_get (ALT_DMA_MANAGER_STATE_t *state) |
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ALT_STATUS_CODE | alt_dma_channel_state_get (ALT_DMA_CHANNEL_t channel, ALT_DMA_CHANNEL_STATE_t *state) |
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ALT_STATUS_CODE | alt_dma_manager_fault_status_get (ALT_DMA_MANAGER_FAULT_t *fault) |
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ALT_STATUS_CODE | alt_dma_channel_fault_status_get (ALT_DMA_CHANNEL_t channel, ALT_DMA_CHANNEL_FAULT_t *fault) |
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ALT_STATUS_CODE | alt_dma_event_int_select (ALT_DMA_EVENT_t evt_num, ALT_DMA_EVENT_SELECT_t opt) |
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ALT_STATUS_CODE | alt_dma_event_int_status_get_raw (ALT_DMA_EVENT_t evt_num) |
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ALT_STATUS_CODE | alt_dma_int_status_get (ALT_DMA_EVENT_t irq_num) |
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ALT_STATUS_CODE | alt_dma_int_clear (ALT_DMA_EVENT_t irq_num) |
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ALT_STATUS_CODE | alt_dma_memory_to_memory (ALT_DMA_CHANNEL_t channel, ALT_DMA_PROGRAM_t *program, void *dst, const void *src, size_t size, bool send_evt, ALT_DMA_EVENT_t evt) |
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ALT_STATUS_CODE | alt_dma_zero_to_memory (ALT_DMA_CHANNEL_t channel, ALT_DMA_PROGRAM_t *program, void *buf, size_t size, bool send_evt, ALT_DMA_EVENT_t evt) |
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ALT_STATUS_CODE | alt_dma_memory_to_register (ALT_DMA_CHANNEL_t channel, ALT_DMA_PROGRAM_t *program, void *dst_reg, const void *src_buf, size_t count, uint32_t register_width_bits, bool send_evt, ALT_DMA_EVENT_t evt) |
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ALT_STATUS_CODE | alt_dma_register_to_memory (ALT_DMA_CHANNEL_t channel, ALT_DMA_PROGRAM_t *program, void *dst_buf, const void *src_reg, size_t count, uint32_t register_width_bits, bool send_evt, ALT_DMA_EVENT_t evt) |
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ALT_STATUS_CODE | alt_dma_memory_to_periph (ALT_DMA_CHANNEL_t channel, ALT_DMA_PROGRAM_t *program, ALT_DMA_PERIPH_t dstp, const void *src, size_t size, void *periph_info, bool send_evt, ALT_DMA_EVENT_t evt) |
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ALT_STATUS_CODE | alt_dma_periph_to_memory (ALT_DMA_CHANNEL_t channel, ALT_DMA_PROGRAM_t *program, void *dst, ALT_DMA_PERIPH_t srcp, size_t size, void *periph_info, bool send_evt, ALT_DMA_EVENT_t evt) |
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ALT_STATUS_CODE | alt_dma_ecc_start (void *block, size_t size) |
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