RTEMS  5.0.0
alt_clkmgr.h
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36 
37 /* Altera - ALT_CLKMGR */
38 
39 #ifndef __ALTERA_ALT_CLKMGR_H__
40 #define __ALTERA_ALT_CLKMGR_H__
41 
42 #ifdef __cplusplus
43 extern "C"
44 {
45 #endif /* __cplusplus */
46 
47 /*
48  * Component : Clock Manager Module - ALT_CLKMGR
49  * Clock Manager Module
50  *
51  * Registers in the Clock Manager module
52  *
53  */
54 /*
55  * Register : Control Register - ctrl
56  *
57  * Contains fields that control the entire Clock Manager.
58  *
59  * Register Layout
60  *
61  * Bits | Access | Reset | Description
62  * :-------|:-------|:------|:------------------------------
63  * [0] | RW | 0x1 | Safe Mode
64  * [1] | ??? | 0x0 | *UNDEFINED*
65  * [2] | RW | 0x1 | Enable SafeMode on Warm Reset
66  * [31:3] | ??? | 0x0 | *UNDEFINED*
67  *
68  */
69 /*
70  * Field : Safe Mode - safemode
71  *
72  * When set the Clock Manager is in Safe Mode.
73  *
74  * In Safe Mode Clock Manager register settings defining clock behavior are ignored
75  * and clocks are set to a Safe Mode state.In Safe Mode all clocks with the
76  * optional exception of debug clocks, are directly generated from the EOSC1 clock
77  * input, all PLLs are bypassed, all programmable dividers are set to 1 and all
78  * clocks are enabled.
79  *
80  * This bit should only be cleared when clocks have been correctly configured
81  *
82  * This field is set on a cold reset and optionally on a warm reset and may not be
83  * set by SW.
84  *
85  * Field Access Macros:
86  *
87  */
88 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CTL_SAFEMOD register field. */
89 #define ALT_CLKMGR_CTL_SAFEMOD_LSB 0
90 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CTL_SAFEMOD register field. */
91 #define ALT_CLKMGR_CTL_SAFEMOD_MSB 0
92 /* The width in bits of the ALT_CLKMGR_CTL_SAFEMOD register field. */
93 #define ALT_CLKMGR_CTL_SAFEMOD_WIDTH 1
94 /* The mask used to set the ALT_CLKMGR_CTL_SAFEMOD register field value. */
95 #define ALT_CLKMGR_CTL_SAFEMOD_SET_MSK 0x00000001
96 /* The mask used to clear the ALT_CLKMGR_CTL_SAFEMOD register field value. */
97 #define ALT_CLKMGR_CTL_SAFEMOD_CLR_MSK 0xfffffffe
98 /* The reset value of the ALT_CLKMGR_CTL_SAFEMOD register field. */
99 #define ALT_CLKMGR_CTL_SAFEMOD_RESET 0x1
100 /* Extracts the ALT_CLKMGR_CTL_SAFEMOD field value from a register. */
101 #define ALT_CLKMGR_CTL_SAFEMOD_GET(value) (((value) & 0x00000001) >> 0)
102 /* Produces a ALT_CLKMGR_CTL_SAFEMOD register field value suitable for setting the register. */
103 #define ALT_CLKMGR_CTL_SAFEMOD_SET(value) (((value) << 0) & 0x00000001)
104 
105 /*
106  * Field : Enable SafeMode on Warm Reset - ensfmdwr
107  *
108  * When set the Clock Manager will respond to a Safe Mode request from the Reset
109  * Manager on a warm reset by setting the Safe Mode bit. When clear the clock
110  * manager will not set the the Safe Mode bit on a warm reset This bit is cleared
111  * on a cold reset. Warm reset has no affect on this bit.
112  *
113  * Field Access Macros:
114  *
115  */
116 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CTL_ENSFMDWR register field. */
117 #define ALT_CLKMGR_CTL_ENSFMDWR_LSB 2
118 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CTL_ENSFMDWR register field. */
119 #define ALT_CLKMGR_CTL_ENSFMDWR_MSB 2
120 /* The width in bits of the ALT_CLKMGR_CTL_ENSFMDWR register field. */
121 #define ALT_CLKMGR_CTL_ENSFMDWR_WIDTH 1
122 /* The mask used to set the ALT_CLKMGR_CTL_ENSFMDWR register field value. */
123 #define ALT_CLKMGR_CTL_ENSFMDWR_SET_MSK 0x00000004
124 /* The mask used to clear the ALT_CLKMGR_CTL_ENSFMDWR register field value. */
125 #define ALT_CLKMGR_CTL_ENSFMDWR_CLR_MSK 0xfffffffb
126 /* The reset value of the ALT_CLKMGR_CTL_ENSFMDWR register field. */
127 #define ALT_CLKMGR_CTL_ENSFMDWR_RESET 0x1
128 /* Extracts the ALT_CLKMGR_CTL_ENSFMDWR field value from a register. */
129 #define ALT_CLKMGR_CTL_ENSFMDWR_GET(value) (((value) & 0x00000004) >> 2)
130 /* Produces a ALT_CLKMGR_CTL_ENSFMDWR register field value suitable for setting the register. */
131 #define ALT_CLKMGR_CTL_ENSFMDWR_SET(value) (((value) << 2) & 0x00000004)
132 
133 #ifndef __ASSEMBLY__
134 /*
135  * WARNING: The C register and register group struct declarations are provided for
136  * convenience and illustrative purposes. They should, however, be used with
137  * caution as the C language standard provides no guarantees about the alignment or
138  * atomicity of device memory accesses. The recommended practice for writing
139  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
140  * alt_write_word() functions.
141  *
142  * The struct declaration for register ALT_CLKMGR_CTL.
143  */
145 {
146  uint32_t safemode : 1; /* Safe Mode */
147  uint32_t : 1; /* *UNDEFINED* */
148  uint32_t ensfmdwr : 1; /* Enable SafeMode on Warm Reset */
149  uint32_t : 29; /* *UNDEFINED* */
150 };
151 
152 /* The typedef declaration for register ALT_CLKMGR_CTL. */
153 typedef volatile struct ALT_CLKMGR_CTL_s ALT_CLKMGR_CTL_t;
154 #endif /* __ASSEMBLY__ */
155 
156 /* The byte offset of the ALT_CLKMGR_CTL register from the beginning of the component. */
157 #define ALT_CLKMGR_CTL_OFST 0x0
158 
159 /*
160  * Register : PLL Bypass Register - bypass
161  *
162  * Contains fields that control bypassing each PLL.
163  *
164  * Register Layout
165  *
166  * Bits | Access | Reset | Description
167  * :-------|:-------|:------|:-----------------------------
168  * [0] | RW | 0x1 | Main PLL Bypass
169  * [1] | RW | 0x1 | SDRAM PLL Bypass
170  * [2] | RW | 0x0 | SDRAM PLL Bypass Source
171  * [3] | RW | 0x1 | Peripheral PLL Bypass
172  * [4] | RW | 0x0 | Peripheral PLL Bypass Source
173  * [31:5] | ??? | 0x0 | *UNDEFINED*
174  *
175  */
176 /*
177  * Field : Main PLL Bypass - mainpll
178  *
179  * When set, causes the Main PLL VCO and counters to be bypassed so that all clocks
180  * generated by the Main PLL are directly driven from the Main PLL input clock. The
181  * bypass source for Main PLL is the external eosc1_clk.
182  *
183  * The reset value for this bit is applied on a cold reset. Warm reset has no
184  * affect on this bit.
185  *
186  * Field Access Macros:
187  *
188  */
189 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_BYPASS_MAINPLL register field. */
190 #define ALT_CLKMGR_BYPASS_MAINPLL_LSB 0
191 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_BYPASS_MAINPLL register field. */
192 #define ALT_CLKMGR_BYPASS_MAINPLL_MSB 0
193 /* The width in bits of the ALT_CLKMGR_BYPASS_MAINPLL register field. */
194 #define ALT_CLKMGR_BYPASS_MAINPLL_WIDTH 1
195 /* The mask used to set the ALT_CLKMGR_BYPASS_MAINPLL register field value. */
196 #define ALT_CLKMGR_BYPASS_MAINPLL_SET_MSK 0x00000001
197 /* The mask used to clear the ALT_CLKMGR_BYPASS_MAINPLL register field value. */
198 #define ALT_CLKMGR_BYPASS_MAINPLL_CLR_MSK 0xfffffffe
199 /* The reset value of the ALT_CLKMGR_BYPASS_MAINPLL register field. */
200 #define ALT_CLKMGR_BYPASS_MAINPLL_RESET 0x1
201 /* Extracts the ALT_CLKMGR_BYPASS_MAINPLL field value from a register. */
202 #define ALT_CLKMGR_BYPASS_MAINPLL_GET(value) (((value) & 0x00000001) >> 0)
203 /* Produces a ALT_CLKMGR_BYPASS_MAINPLL register field value suitable for setting the register. */
204 #define ALT_CLKMGR_BYPASS_MAINPLL_SET(value) (((value) << 0) & 0x00000001)
205 
206 /*
207  * Field : SDRAM PLL Bypass - sdrpll
208  *
209  * When set, causes the SDRAM PLL VCO and counters to be bypassed so that all
210  * clocks generated by the SDRAM PLL are directly driven from either eosc1_clk or
211  * the SDRAM PLL input clock.
212  *
213  * The bypass clock source for SDRAM PLL is determined by the SDRAM PLL Bypass
214  * Source Register bit.
215  *
216  * The reset value for this bit is applied on a cold reset. Warm reset has no
217  * affect on this bit.
218  *
219  * Field Access Macros:
220  *
221  */
222 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_BYPASS_SDRPLL register field. */
223 #define ALT_CLKMGR_BYPASS_SDRPLL_LSB 1
224 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_BYPASS_SDRPLL register field. */
225 #define ALT_CLKMGR_BYPASS_SDRPLL_MSB 1
226 /* The width in bits of the ALT_CLKMGR_BYPASS_SDRPLL register field. */
227 #define ALT_CLKMGR_BYPASS_SDRPLL_WIDTH 1
228 /* The mask used to set the ALT_CLKMGR_BYPASS_SDRPLL register field value. */
229 #define ALT_CLKMGR_BYPASS_SDRPLL_SET_MSK 0x00000002
230 /* The mask used to clear the ALT_CLKMGR_BYPASS_SDRPLL register field value. */
231 #define ALT_CLKMGR_BYPASS_SDRPLL_CLR_MSK 0xfffffffd
232 /* The reset value of the ALT_CLKMGR_BYPASS_SDRPLL register field. */
233 #define ALT_CLKMGR_BYPASS_SDRPLL_RESET 0x1
234 /* Extracts the ALT_CLKMGR_BYPASS_SDRPLL field value from a register. */
235 #define ALT_CLKMGR_BYPASS_SDRPLL_GET(value) (((value) & 0x00000002) >> 1)
236 /* Produces a ALT_CLKMGR_BYPASS_SDRPLL register field value suitable for setting the register. */
237 #define ALT_CLKMGR_BYPASS_SDRPLL_SET(value) (((value) << 1) & 0x00000002)
238 
239 /*
240  * Field : SDRAM PLL Bypass Source - sdrpllsrc
241  *
242  * This bit defines the bypass source forSDRAM PLL.
243  *
244  * When changing fields that affect VCO lock the PLL must be bypassed and this bit
245  * must be set to OSC1_CLK.
246  *
247  * The reset value for this bit is applied on a cold reset. Warm reset has no
248  * affect on this bit.
249  *
250  * Field Enumeration Values:
251  *
252  * Enum | Value | Description
253  * :-----------------------------------------------|:------|:---------------------
254  * ALT_CLKMGR_BYPASS_SDRPLLSRC_E_SELECT_EOSC1 | 0x0 | Select EOSC1
255  * ALT_CLKMGR_BYPASS_SDRPLLSRC_E_SELECT_INPUT_MUX | 0x1 | Select PLL Input Mux
256  *
257  * Field Access Macros:
258  *
259  */
260 /*
261  * Enumerated value for register field ALT_CLKMGR_BYPASS_SDRPLLSRC
262  *
263  * Select EOSC1
264  */
265 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_E_SELECT_EOSC1 0x0
266 /*
267  * Enumerated value for register field ALT_CLKMGR_BYPASS_SDRPLLSRC
268  *
269  * Select PLL Input Mux
270  */
271 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_E_SELECT_INPUT_MUX 0x1
272 
273 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_BYPASS_SDRPLLSRC register field. */
274 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_LSB 2
275 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_BYPASS_SDRPLLSRC register field. */
276 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_MSB 2
277 /* The width in bits of the ALT_CLKMGR_BYPASS_SDRPLLSRC register field. */
278 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_WIDTH 1
279 /* The mask used to set the ALT_CLKMGR_BYPASS_SDRPLLSRC register field value. */
280 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_SET_MSK 0x00000004
281 /* The mask used to clear the ALT_CLKMGR_BYPASS_SDRPLLSRC register field value. */
282 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_CLR_MSK 0xfffffffb
283 /* The reset value of the ALT_CLKMGR_BYPASS_SDRPLLSRC register field. */
284 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_RESET 0x0
285 /* Extracts the ALT_CLKMGR_BYPASS_SDRPLLSRC field value from a register. */
286 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_GET(value) (((value) & 0x00000004) >> 2)
287 /* Produces a ALT_CLKMGR_BYPASS_SDRPLLSRC register field value suitable for setting the register. */
288 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_SET(value) (((value) << 2) & 0x00000004)
289 
290 /*
291  * Field : Peripheral PLL Bypass - perpll
292  *
293  * When set, causes the Peripheral PLL VCO and counters to be bypassed so that all
294  * clocks generated by the Peripheral PLL are directly driven from either eosc1_clk
295  * or the Peripheral PLL input clock.
296  *
297  * The bypass clock source for Peripheral PLL is determined by the Peripheral PLL
298  * Bypass Source Register bit.
299  *
300  * The reset value for this bit is applied on a cold reset. Warm reset has no
301  * affect on this bit.
302  *
303  * Field Access Macros:
304  *
305  */
306 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_BYPASS_PERPLL register field. */
307 #define ALT_CLKMGR_BYPASS_PERPLL_LSB 3
308 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_BYPASS_PERPLL register field. */
309 #define ALT_CLKMGR_BYPASS_PERPLL_MSB 3
310 /* The width in bits of the ALT_CLKMGR_BYPASS_PERPLL register field. */
311 #define ALT_CLKMGR_BYPASS_PERPLL_WIDTH 1
312 /* The mask used to set the ALT_CLKMGR_BYPASS_PERPLL register field value. */
313 #define ALT_CLKMGR_BYPASS_PERPLL_SET_MSK 0x00000008
314 /* The mask used to clear the ALT_CLKMGR_BYPASS_PERPLL register field value. */
315 #define ALT_CLKMGR_BYPASS_PERPLL_CLR_MSK 0xfffffff7
316 /* The reset value of the ALT_CLKMGR_BYPASS_PERPLL register field. */
317 #define ALT_CLKMGR_BYPASS_PERPLL_RESET 0x1
318 /* Extracts the ALT_CLKMGR_BYPASS_PERPLL field value from a register. */
319 #define ALT_CLKMGR_BYPASS_PERPLL_GET(value) (((value) & 0x00000008) >> 3)
320 /* Produces a ALT_CLKMGR_BYPASS_PERPLL register field value suitable for setting the register. */
321 #define ALT_CLKMGR_BYPASS_PERPLL_SET(value) (((value) << 3) & 0x00000008)
322 
323 /*
324  * Field : Peripheral PLL Bypass Source - perpllsrc
325  *
326  * This bit defines the bypass source forPeripheral PLL.
327  *
328  * When changing fields that affect VCO lock the PLL must be bypassed and this bit
329  * must be set to OSC1_CLK.
330  *
331  * The reset value for this bit is applied on a cold reset. Warm reset has no
332  * affect on this bit.
333  *
334  * Field Enumeration Values:
335  *
336  * Enum | Value | Description
337  * :-----------------------------------------------|:------|:---------------------
338  * ALT_CLKMGR_BYPASS_PERPLLSRC_E_SELECT_EOSC1 | 0x0 | Select EOSC1
339  * ALT_CLKMGR_BYPASS_PERPLLSRC_E_SELECT_INPUT_MUX | 0x1 | Select PLL Input Mux
340  *
341  * Field Access Macros:
342  *
343  */
344 /*
345  * Enumerated value for register field ALT_CLKMGR_BYPASS_PERPLLSRC
346  *
347  * Select EOSC1
348  */
349 #define ALT_CLKMGR_BYPASS_PERPLLSRC_E_SELECT_EOSC1 0x0
350 /*
351  * Enumerated value for register field ALT_CLKMGR_BYPASS_PERPLLSRC
352  *
353  * Select PLL Input Mux
354  */
355 #define ALT_CLKMGR_BYPASS_PERPLLSRC_E_SELECT_INPUT_MUX 0x1
356 
357 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_BYPASS_PERPLLSRC register field. */
358 #define ALT_CLKMGR_BYPASS_PERPLLSRC_LSB 4
359 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_BYPASS_PERPLLSRC register field. */
360 #define ALT_CLKMGR_BYPASS_PERPLLSRC_MSB 4
361 /* The width in bits of the ALT_CLKMGR_BYPASS_PERPLLSRC register field. */
362 #define ALT_CLKMGR_BYPASS_PERPLLSRC_WIDTH 1
363 /* The mask used to set the ALT_CLKMGR_BYPASS_PERPLLSRC register field value. */
364 #define ALT_CLKMGR_BYPASS_PERPLLSRC_SET_MSK 0x00000010
365 /* The mask used to clear the ALT_CLKMGR_BYPASS_PERPLLSRC register field value. */
366 #define ALT_CLKMGR_BYPASS_PERPLLSRC_CLR_MSK 0xffffffef
367 /* The reset value of the ALT_CLKMGR_BYPASS_PERPLLSRC register field. */
368 #define ALT_CLKMGR_BYPASS_PERPLLSRC_RESET 0x0
369 /* Extracts the ALT_CLKMGR_BYPASS_PERPLLSRC field value from a register. */
370 #define ALT_CLKMGR_BYPASS_PERPLLSRC_GET(value) (((value) & 0x00000010) >> 4)
371 /* Produces a ALT_CLKMGR_BYPASS_PERPLLSRC register field value suitable for setting the register. */
372 #define ALT_CLKMGR_BYPASS_PERPLLSRC_SET(value) (((value) << 4) & 0x00000010)
373 
374 #ifndef __ASSEMBLY__
375 /*
376  * WARNING: The C register and register group struct declarations are provided for
377  * convenience and illustrative purposes. They should, however, be used with
378  * caution as the C language standard provides no guarantees about the alignment or
379  * atomicity of device memory accesses. The recommended practice for writing
380  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
381  * alt_write_word() functions.
382  *
383  * The struct declaration for register ALT_CLKMGR_BYPASS.
384  */
386 {
387  uint32_t mainpll : 1; /* Main PLL Bypass */
388  uint32_t sdrpll : 1; /* SDRAM PLL Bypass */
389  uint32_t sdrpllsrc : 1; /* SDRAM PLL Bypass Source */
390  uint32_t perpll : 1; /* Peripheral PLL Bypass */
391  uint32_t perpllsrc : 1; /* Peripheral PLL Bypass Source */
392  uint32_t : 27; /* *UNDEFINED* */
393 };
394 
395 /* The typedef declaration for register ALT_CLKMGR_BYPASS. */
396 typedef volatile struct ALT_CLKMGR_BYPASS_s ALT_CLKMGR_BYPASS_t;
397 #endif /* __ASSEMBLY__ */
398 
399 /* The byte offset of the ALT_CLKMGR_BYPASS register from the beginning of the component. */
400 #define ALT_CLKMGR_BYPASS_OFST 0x4
401 
402 /*
403  * Register : Interrupt Status Register - inter
404  *
405  * Contains fields that indicate the PLL lock status.
406  *
407  * Fields are only reset by a cold reset.
408  *
409  * Register Layout
410  *
411  * Bits | Access | Reset | Description
412  * :-------|:-------|:--------|:-----------------------------------
413  * [0] | RW | 0x0 | Main PLL Achieved Lock
414  * [1] | RW | 0x0 | Peripheral PLL Achieved Lock
415  * [2] | RW | 0x0 | SDRAM PLL Achieved Lock
416  * [3] | RW | 0x0 | Main PLL Lost Lock
417  * [4] | RW | 0x0 | Peripheral PLL Lost Lock
418  * [5] | RW | 0x0 | SDRAM PLL Lost Lock
419  * [6] | R | Unknown | Main PLL Current Lock Status
420  * [7] | R | Unknown | Peripheral PLL Current Lock Status
421  * [8] | R | Unknown | SDRAM PLL Current Lock Status
422  * [31:9] | ??? | 0x0 | *UNDEFINED*
423  *
424  */
425 /*
426  * Field : Main PLL Achieved Lock - mainpllachieved
427  *
428  * If 1, the Main PLL has achieved lock at least once since this bit was cleared.
429  * If 0, the Main PLL has not achieved lock since this bit was cleared.
430  *
431  * Field Access Macros:
432  *
433  */
434 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field. */
435 #define ALT_CLKMGR_INTER_MAINPLLACHIEVED_LSB 0
436 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field. */
437 #define ALT_CLKMGR_INTER_MAINPLLACHIEVED_MSB 0
438 /* The width in bits of the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field. */
439 #define ALT_CLKMGR_INTER_MAINPLLACHIEVED_WIDTH 1
440 /* The mask used to set the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field value. */
441 #define ALT_CLKMGR_INTER_MAINPLLACHIEVED_SET_MSK 0x00000001
442 /* The mask used to clear the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field value. */
443 #define ALT_CLKMGR_INTER_MAINPLLACHIEVED_CLR_MSK 0xfffffffe
444 /* The reset value of the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field. */
445 #define ALT_CLKMGR_INTER_MAINPLLACHIEVED_RESET 0x0
446 /* Extracts the ALT_CLKMGR_INTER_MAINPLLACHIEVED field value from a register. */
447 #define ALT_CLKMGR_INTER_MAINPLLACHIEVED_GET(value) (((value) & 0x00000001) >> 0)
448 /* Produces a ALT_CLKMGR_INTER_MAINPLLACHIEVED register field value suitable for setting the register. */
449 #define ALT_CLKMGR_INTER_MAINPLLACHIEVED_SET(value) (((value) << 0) & 0x00000001)
450 
451 /*
452  * Field : Peripheral PLL Achieved Lock - perpllachieved
453  *
454  * If 1, the Peripheral PLL has achieved lock at least once since this bit was
455  * cleared. If 0, the Peripheral PLL has not achieved lock since this bit was
456  * cleared.
457  *
458  * Field Access Macros:
459  *
460  */
461 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_PERPLLACHIEVED register field. */
462 #define ALT_CLKMGR_INTER_PERPLLACHIEVED_LSB 1
463 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_PERPLLACHIEVED register field. */
464 #define ALT_CLKMGR_INTER_PERPLLACHIEVED_MSB 1
465 /* The width in bits of the ALT_CLKMGR_INTER_PERPLLACHIEVED register field. */
466 #define ALT_CLKMGR_INTER_PERPLLACHIEVED_WIDTH 1
467 /* The mask used to set the ALT_CLKMGR_INTER_PERPLLACHIEVED register field value. */
468 #define ALT_CLKMGR_INTER_PERPLLACHIEVED_SET_MSK 0x00000002
469 /* The mask used to clear the ALT_CLKMGR_INTER_PERPLLACHIEVED register field value. */
470 #define ALT_CLKMGR_INTER_PERPLLACHIEVED_CLR_MSK 0xfffffffd
471 /* The reset value of the ALT_CLKMGR_INTER_PERPLLACHIEVED register field. */
472 #define ALT_CLKMGR_INTER_PERPLLACHIEVED_RESET 0x0
473 /* Extracts the ALT_CLKMGR_INTER_PERPLLACHIEVED field value from a register. */
474 #define ALT_CLKMGR_INTER_PERPLLACHIEVED_GET(value) (((value) & 0x00000002) >> 1)
475 /* Produces a ALT_CLKMGR_INTER_PERPLLACHIEVED register field value suitable for setting the register. */
476 #define ALT_CLKMGR_INTER_PERPLLACHIEVED_SET(value) (((value) << 1) & 0x00000002)
477 
478 /*
479  * Field : SDRAM PLL Achieved Lock - sdrpllachieved
480  *
481  * If 1, the SDRAM PLL has achieved lock at least once since this bit was cleared.
482  * If 0, the SDRAM PLL has not achieved lock since this bit was cleared.
483  *
484  * Field Access Macros:
485  *
486  */
487 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field. */
488 #define ALT_CLKMGR_INTER_SDRPLLACHIEVED_LSB 2
489 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field. */
490 #define ALT_CLKMGR_INTER_SDRPLLACHIEVED_MSB 2
491 /* The width in bits of the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field. */
492 #define ALT_CLKMGR_INTER_SDRPLLACHIEVED_WIDTH 1
493 /* The mask used to set the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field value. */
494 #define ALT_CLKMGR_INTER_SDRPLLACHIEVED_SET_MSK 0x00000004
495 /* The mask used to clear the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field value. */
496 #define ALT_CLKMGR_INTER_SDRPLLACHIEVED_CLR_MSK 0xfffffffb
497 /* The reset value of the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field. */
498 #define ALT_CLKMGR_INTER_SDRPLLACHIEVED_RESET 0x0
499 /* Extracts the ALT_CLKMGR_INTER_SDRPLLACHIEVED field value from a register. */
500 #define ALT_CLKMGR_INTER_SDRPLLACHIEVED_GET(value) (((value) & 0x00000004) >> 2)
501 /* Produces a ALT_CLKMGR_INTER_SDRPLLACHIEVED register field value suitable for setting the register. */
502 #define ALT_CLKMGR_INTER_SDRPLLACHIEVED_SET(value) (((value) << 2) & 0x00000004)
503 
504 /*
505  * Field : Main PLL Lost Lock - mainplllost
506  *
507  * If 1, the Main PLL has lost lock at least once since this bit was cleared. If 0,
508  * the Main PLL has not lost lock since this bit was cleared.
509  *
510  * Field Access Macros:
511  *
512  */
513 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_MAINPLLLOST register field. */
514 #define ALT_CLKMGR_INTER_MAINPLLLOST_LSB 3
515 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_MAINPLLLOST register field. */
516 #define ALT_CLKMGR_INTER_MAINPLLLOST_MSB 3
517 /* The width in bits of the ALT_CLKMGR_INTER_MAINPLLLOST register field. */
518 #define ALT_CLKMGR_INTER_MAINPLLLOST_WIDTH 1
519 /* The mask used to set the ALT_CLKMGR_INTER_MAINPLLLOST register field value. */
520 #define ALT_CLKMGR_INTER_MAINPLLLOST_SET_MSK 0x00000008
521 /* The mask used to clear the ALT_CLKMGR_INTER_MAINPLLLOST register field value. */
522 #define ALT_CLKMGR_INTER_MAINPLLLOST_CLR_MSK 0xfffffff7
523 /* The reset value of the ALT_CLKMGR_INTER_MAINPLLLOST register field. */
524 #define ALT_CLKMGR_INTER_MAINPLLLOST_RESET 0x0
525 /* Extracts the ALT_CLKMGR_INTER_MAINPLLLOST field value from a register. */
526 #define ALT_CLKMGR_INTER_MAINPLLLOST_GET(value) (((value) & 0x00000008) >> 3)
527 /* Produces a ALT_CLKMGR_INTER_MAINPLLLOST register field value suitable for setting the register. */
528 #define ALT_CLKMGR_INTER_MAINPLLLOST_SET(value) (((value) << 3) & 0x00000008)
529 
530 /*
531  * Field : Peripheral PLL Lost Lock - perplllost
532  *
533  * If 1, the Peripheral PLL has lost lock at least once since this bit was cleared.
534  * If 0, the Peripheral PLL has not lost lock since this bit was cleared.
535  *
536  * Field Access Macros:
537  *
538  */
539 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_PERPLLLOST register field. */
540 #define ALT_CLKMGR_INTER_PERPLLLOST_LSB 4
541 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_PERPLLLOST register field. */
542 #define ALT_CLKMGR_INTER_PERPLLLOST_MSB 4
543 /* The width in bits of the ALT_CLKMGR_INTER_PERPLLLOST register field. */
544 #define ALT_CLKMGR_INTER_PERPLLLOST_WIDTH 1
545 /* The mask used to set the ALT_CLKMGR_INTER_PERPLLLOST register field value. */
546 #define ALT_CLKMGR_INTER_PERPLLLOST_SET_MSK 0x00000010
547 /* The mask used to clear the ALT_CLKMGR_INTER_PERPLLLOST register field value. */
548 #define ALT_CLKMGR_INTER_PERPLLLOST_CLR_MSK 0xffffffef
549 /* The reset value of the ALT_CLKMGR_INTER_PERPLLLOST register field. */
550 #define ALT_CLKMGR_INTER_PERPLLLOST_RESET 0x0
551 /* Extracts the ALT_CLKMGR_INTER_PERPLLLOST field value from a register. */
552 #define ALT_CLKMGR_INTER_PERPLLLOST_GET(value) (((value) & 0x00000010) >> 4)
553 /* Produces a ALT_CLKMGR_INTER_PERPLLLOST register field value suitable for setting the register. */
554 #define ALT_CLKMGR_INTER_PERPLLLOST_SET(value) (((value) << 4) & 0x00000010)
555 
556 /*
557  * Field : SDRAM PLL Lost Lock - sdrplllost
558  *
559  * If 1, the SDRAM PLL has lost lock at least once since this bit was cleared. If
560  * 0, the SDRAM PLL has not lost lock since this bit was cleared.
561  *
562  * Field Access Macros:
563  *
564  */
565 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_SDRPLLLOST register field. */
566 #define ALT_CLKMGR_INTER_SDRPLLLOST_LSB 5
567 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_SDRPLLLOST register field. */
568 #define ALT_CLKMGR_INTER_SDRPLLLOST_MSB 5
569 /* The width in bits of the ALT_CLKMGR_INTER_SDRPLLLOST register field. */
570 #define ALT_CLKMGR_INTER_SDRPLLLOST_WIDTH 1
571 /* The mask used to set the ALT_CLKMGR_INTER_SDRPLLLOST register field value. */
572 #define ALT_CLKMGR_INTER_SDRPLLLOST_SET_MSK 0x00000020
573 /* The mask used to clear the ALT_CLKMGR_INTER_SDRPLLLOST register field value. */
574 #define ALT_CLKMGR_INTER_SDRPLLLOST_CLR_MSK 0xffffffdf
575 /* The reset value of the ALT_CLKMGR_INTER_SDRPLLLOST register field. */
576 #define ALT_CLKMGR_INTER_SDRPLLLOST_RESET 0x0
577 /* Extracts the ALT_CLKMGR_INTER_SDRPLLLOST field value from a register. */
578 #define ALT_CLKMGR_INTER_SDRPLLLOST_GET(value) (((value) & 0x00000020) >> 5)
579 /* Produces a ALT_CLKMGR_INTER_SDRPLLLOST register field value suitable for setting the register. */
580 #define ALT_CLKMGR_INTER_SDRPLLLOST_SET(value) (((value) << 5) & 0x00000020)
581 
582 /*
583  * Field : Main PLL Current Lock Status - mainplllocked
584  *
585  * If 1, the Main PLL is currently locked. If 0, the Main PLL is currently not
586  * locked.
587  *
588  * Field Access Macros:
589  *
590  */
591 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_MAINPLLLOCKED register field. */
592 #define ALT_CLKMGR_INTER_MAINPLLLOCKED_LSB 6
593 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_MAINPLLLOCKED register field. */
594 #define ALT_CLKMGR_INTER_MAINPLLLOCKED_MSB 6
595 /* The width in bits of the ALT_CLKMGR_INTER_MAINPLLLOCKED register field. */
596 #define ALT_CLKMGR_INTER_MAINPLLLOCKED_WIDTH 1
597 /* The mask used to set the ALT_CLKMGR_INTER_MAINPLLLOCKED register field value. */
598 #define ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK 0x00000040
599 /* The mask used to clear the ALT_CLKMGR_INTER_MAINPLLLOCKED register field value. */
600 #define ALT_CLKMGR_INTER_MAINPLLLOCKED_CLR_MSK 0xffffffbf
601 /* The reset value of the ALT_CLKMGR_INTER_MAINPLLLOCKED register field is UNKNOWN. */
602 #define ALT_CLKMGR_INTER_MAINPLLLOCKED_RESET 0x0
603 /* Extracts the ALT_CLKMGR_INTER_MAINPLLLOCKED field value from a register. */
604 #define ALT_CLKMGR_INTER_MAINPLLLOCKED_GET(value) (((value) & 0x00000040) >> 6)
605 /* Produces a ALT_CLKMGR_INTER_MAINPLLLOCKED register field value suitable for setting the register. */
606 #define ALT_CLKMGR_INTER_MAINPLLLOCKED_SET(value) (((value) << 6) & 0x00000040)
607 
608 /*
609  * Field : Peripheral PLL Current Lock Status - perplllocked
610  *
611  * If 1, the Peripheral PLL is currently locked. If 0, the Peripheral PLL is
612  * currently not locked.
613  *
614  * Field Access Macros:
615  *
616  */
617 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_PERPLLLOCKED register field. */
618 #define ALT_CLKMGR_INTER_PERPLLLOCKED_LSB 7
619 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_PERPLLLOCKED register field. */
620 #define ALT_CLKMGR_INTER_PERPLLLOCKED_MSB 7
621 /* The width in bits of the ALT_CLKMGR_INTER_PERPLLLOCKED register field. */
622 #define ALT_CLKMGR_INTER_PERPLLLOCKED_WIDTH 1
623 /* The mask used to set the ALT_CLKMGR_INTER_PERPLLLOCKED register field value. */
624 #define ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK 0x00000080
625 /* The mask used to clear the ALT_CLKMGR_INTER_PERPLLLOCKED register field value. */
626 #define ALT_CLKMGR_INTER_PERPLLLOCKED_CLR_MSK 0xffffff7f
627 /* The reset value of the ALT_CLKMGR_INTER_PERPLLLOCKED register field is UNKNOWN. */
628 #define ALT_CLKMGR_INTER_PERPLLLOCKED_RESET 0x0
629 /* Extracts the ALT_CLKMGR_INTER_PERPLLLOCKED field value from a register. */
630 #define ALT_CLKMGR_INTER_PERPLLLOCKED_GET(value) (((value) & 0x00000080) >> 7)
631 /* Produces a ALT_CLKMGR_INTER_PERPLLLOCKED register field value suitable for setting the register. */
632 #define ALT_CLKMGR_INTER_PERPLLLOCKED_SET(value) (((value) << 7) & 0x00000080)
633 
634 /*
635  * Field : SDRAM PLL Current Lock Status - sdrplllocked
636  *
637  * If 1, the SDRAM PLL is currently locked. If 0, the SDRAM PLL is currently not
638  * locked.
639  *
640  * Field Access Macros:
641  *
642  */
643 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_SDRPLLLOCKED register field. */
644 #define ALT_CLKMGR_INTER_SDRPLLLOCKED_LSB 8
645 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_SDRPLLLOCKED register field. */
646 #define ALT_CLKMGR_INTER_SDRPLLLOCKED_MSB 8
647 /* The width in bits of the ALT_CLKMGR_INTER_SDRPLLLOCKED register field. */
648 #define ALT_CLKMGR_INTER_SDRPLLLOCKED_WIDTH 1
649 /* The mask used to set the ALT_CLKMGR_INTER_SDRPLLLOCKED register field value. */
650 #define ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK 0x00000100
651 /* The mask used to clear the ALT_CLKMGR_INTER_SDRPLLLOCKED register field value. */
652 #define ALT_CLKMGR_INTER_SDRPLLLOCKED_CLR_MSK 0xfffffeff
653 /* The reset value of the ALT_CLKMGR_INTER_SDRPLLLOCKED register field is UNKNOWN. */
654 #define ALT_CLKMGR_INTER_SDRPLLLOCKED_RESET 0x0
655 /* Extracts the ALT_CLKMGR_INTER_SDRPLLLOCKED field value from a register. */
656 #define ALT_CLKMGR_INTER_SDRPLLLOCKED_GET(value) (((value) & 0x00000100) >> 8)
657 /* Produces a ALT_CLKMGR_INTER_SDRPLLLOCKED register field value suitable for setting the register. */
658 #define ALT_CLKMGR_INTER_SDRPLLLOCKED_SET(value) (((value) << 8) & 0x00000100)
659 
660 #ifndef __ASSEMBLY__
661 /*
662  * WARNING: The C register and register group struct declarations are provided for
663  * convenience and illustrative purposes. They should, however, be used with
664  * caution as the C language standard provides no guarantees about the alignment or
665  * atomicity of device memory accesses. The recommended practice for writing
666  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
667  * alt_write_word() functions.
668  *
669  * The struct declaration for register ALT_CLKMGR_INTER.
670  */
672 {
673  uint32_t mainpllachieved : 1; /* Main PLL Achieved Lock */
674  uint32_t perpllachieved : 1; /* Peripheral PLL Achieved Lock */
675  uint32_t sdrpllachieved : 1; /* SDRAM PLL Achieved Lock */
676  uint32_t mainplllost : 1; /* Main PLL Lost Lock */
677  uint32_t perplllost : 1; /* Peripheral PLL Lost Lock */
678  uint32_t sdrplllost : 1; /* SDRAM PLL Lost Lock */
679  const uint32_t mainplllocked : 1; /* Main PLL Current Lock Status */
680  const uint32_t perplllocked : 1; /* Peripheral PLL Current Lock Status */
681  const uint32_t sdrplllocked : 1; /* SDRAM PLL Current Lock Status */
682  uint32_t : 23; /* *UNDEFINED* */
683 };
684 
685 /* The typedef declaration for register ALT_CLKMGR_INTER. */
686 typedef volatile struct ALT_CLKMGR_INTER_s ALT_CLKMGR_INTER_t;
687 #endif /* __ASSEMBLY__ */
688 
689 /* The byte offset of the ALT_CLKMGR_INTER register from the beginning of the component. */
690 #define ALT_CLKMGR_INTER_OFST 0x8
691 
692 /*
693  * Register : Interrupt Enable Register - intren
694  *
695  * Contain fields that enable the interrupt.
696  *
697  * Fields are only reset by a cold reset.
698  *
699  * Register Layout
700  *
701  * Bits | Access | Reset | Description
702  * :-------|:-------|:------|:----------------------------------------------
703  * [0] | RW | 0x0 | Main PLL Achieved Lock Interrupt Enable
704  * [1] | RW | 0x0 | Peripheral PLL Achieved Lock Interrupt Enable
705  * [2] | RW | 0x0 | SDRAM PLL Achieved Lock Interrupt Enable
706  * [3] | RW | 0x0 | Main PLL Achieved Lock Interrupt Enable
707  * [4] | RW | 0x0 | Peripheral PLL Achieved Lock Interrupt Enable
708  * [5] | RW | 0x0 | SDRAM PLL Achieved Lock Interrupt Enable
709  * [31:6] | ??? | 0x0 | *UNDEFINED*
710  *
711  */
712 /*
713  * Field : Main PLL Achieved Lock Interrupt Enable - mainpllachieved
714  *
715  * When set to 1, the Main PLL achieved lock bit is ORed into the Clock Manager
716  * interrupt output. When set to 0 the Main PLL achieved lock bit is not ORed into
717  * the Clock Manager interrupt output.
718  *
719  * Field Access Macros:
720  *
721  */
722 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field. */
723 #define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_LSB 0
724 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field. */
725 #define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_MSB 0
726 /* The width in bits of the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field. */
727 #define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_WIDTH 1
728 /* The mask used to set the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field value. */
729 #define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_SET_MSK 0x00000001
730 /* The mask used to clear the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field value. */
731 #define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_CLR_MSK 0xfffffffe
732 /* The reset value of the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field. */
733 #define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_RESET 0x0
734 /* Extracts the ALT_CLKMGR_INTREN_MAINPLLACHIEVED field value from a register. */
735 #define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_GET(value) (((value) & 0x00000001) >> 0)
736 /* Produces a ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field value suitable for setting the register. */
737 #define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_SET(value) (((value) << 0) & 0x00000001)
738 
739 /*
740  * Field : Peripheral PLL Achieved Lock Interrupt Enable - perpllachieved
741  *
742  * When set to 1, the Peripheral PLL achieved lock bit is ORed into the Clock
743  * Manager interrupt output. When set to 0 the Peripheral PLL achieved lock bit is
744  * not ORed into the Clock Manager interrupt output.
745  *
746  * Field Access Macros:
747  *
748  */
749 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field. */
750 #define ALT_CLKMGR_INTREN_PERPLLACHIEVED_LSB 1
751 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field. */
752 #define ALT_CLKMGR_INTREN_PERPLLACHIEVED_MSB 1
753 /* The width in bits of the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field. */
754 #define ALT_CLKMGR_INTREN_PERPLLACHIEVED_WIDTH 1
755 /* The mask used to set the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field value. */
756 #define ALT_CLKMGR_INTREN_PERPLLACHIEVED_SET_MSK 0x00000002
757 /* The mask used to clear the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field value. */
758 #define ALT_CLKMGR_INTREN_PERPLLACHIEVED_CLR_MSK 0xfffffffd
759 /* The reset value of the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field. */
760 #define ALT_CLKMGR_INTREN_PERPLLACHIEVED_RESET 0x0
761 /* Extracts the ALT_CLKMGR_INTREN_PERPLLACHIEVED field value from a register. */
762 #define ALT_CLKMGR_INTREN_PERPLLACHIEVED_GET(value) (((value) & 0x00000002) >> 1)
763 /* Produces a ALT_CLKMGR_INTREN_PERPLLACHIEVED register field value suitable for setting the register. */
764 #define ALT_CLKMGR_INTREN_PERPLLACHIEVED_SET(value) (((value) << 1) & 0x00000002)
765 
766 /*
767  * Field : SDRAM PLL Achieved Lock Interrupt Enable - sdrpllachieved
768  *
769  * When set to 1, the SDRAM PLL achieved lock bit is ORed into the Clock Manager
770  * interrupt output. When set to 0 the SDRAM PLL achieved lock bit is not ORed
771  * into the Clock Manager interrupt output.
772  *
773  * Field Access Macros:
774  *
775  */
776 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field. */
777 #define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_LSB 2
778 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field. */
779 #define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_MSB 2
780 /* The width in bits of the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field. */
781 #define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_WIDTH 1
782 /* The mask used to set the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field value. */
783 #define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_SET_MSK 0x00000004
784 /* The mask used to clear the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field value. */
785 #define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_CLR_MSK 0xfffffffb
786 /* The reset value of the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field. */
787 #define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_RESET 0x0
788 /* Extracts the ALT_CLKMGR_INTREN_SDRPLLACHIEVED field value from a register. */
789 #define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_GET(value) (((value) & 0x00000004) >> 2)
790 /* Produces a ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field value suitable for setting the register. */
791 #define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_SET(value) (((value) << 2) & 0x00000004)
792 
793 /*
794  * Field : Main PLL Achieved Lock Interrupt Enable - mainplllost
795  *
796  * When set to 1, the Main PLL lost lock bit is ORed into the Clock Manager
797  * interrupt output. When set to 0 the Main PLL lost lock bit is not ORed into the
798  * Clock Manager interrupt output.
799  *
800  * Field Access Macros:
801  *
802  */
803 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_MAINPLLLOST register field. */
804 #define ALT_CLKMGR_INTREN_MAINPLLLOST_LSB 3
805 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_MAINPLLLOST register field. */
806 #define ALT_CLKMGR_INTREN_MAINPLLLOST_MSB 3
807 /* The width in bits of the ALT_CLKMGR_INTREN_MAINPLLLOST register field. */
808 #define ALT_CLKMGR_INTREN_MAINPLLLOST_WIDTH 1
809 /* The mask used to set the ALT_CLKMGR_INTREN_MAINPLLLOST register field value. */
810 #define ALT_CLKMGR_INTREN_MAINPLLLOST_SET_MSK 0x00000008
811 /* The mask used to clear the ALT_CLKMGR_INTREN_MAINPLLLOST register field value. */
812 #define ALT_CLKMGR_INTREN_MAINPLLLOST_CLR_MSK 0xfffffff7
813 /* The reset value of the ALT_CLKMGR_INTREN_MAINPLLLOST register field. */
814 #define ALT_CLKMGR_INTREN_MAINPLLLOST_RESET 0x0
815 /* Extracts the ALT_CLKMGR_INTREN_MAINPLLLOST field value from a register. */
816 #define ALT_CLKMGR_INTREN_MAINPLLLOST_GET(value) (((value) & 0x00000008) >> 3)
817 /* Produces a ALT_CLKMGR_INTREN_MAINPLLLOST register field value suitable for setting the register. */
818 #define ALT_CLKMGR_INTREN_MAINPLLLOST_SET(value) (((value) << 3) & 0x00000008)
819 
820 /*
821  * Field : Peripheral PLL Achieved Lock Interrupt Enable - perplllost
822  *
823  * When set to 1, the Peripheral PLL lost lock bit is ORed into the Clock Manager
824  * interrupt output. When set to 0 the Peripheral PLL lost lock bit is not ORed
825  * into the Clock Manager interrupt output.
826  *
827  * Field Access Macros:
828  *
829  */
830 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_PERPLLLOST register field. */
831 #define ALT_CLKMGR_INTREN_PERPLLLOST_LSB 4
832 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_PERPLLLOST register field. */
833 #define ALT_CLKMGR_INTREN_PERPLLLOST_MSB 4
834 /* The width in bits of the ALT_CLKMGR_INTREN_PERPLLLOST register field. */
835 #define ALT_CLKMGR_INTREN_PERPLLLOST_WIDTH 1
836 /* The mask used to set the ALT_CLKMGR_INTREN_PERPLLLOST register field value. */
837 #define ALT_CLKMGR_INTREN_PERPLLLOST_SET_MSK 0x00000010
838 /* The mask used to clear the ALT_CLKMGR_INTREN_PERPLLLOST register field value. */
839 #define ALT_CLKMGR_INTREN_PERPLLLOST_CLR_MSK 0xffffffef
840 /* The reset value of the ALT_CLKMGR_INTREN_PERPLLLOST register field. */
841 #define ALT_CLKMGR_INTREN_PERPLLLOST_RESET 0x0
842 /* Extracts the ALT_CLKMGR_INTREN_PERPLLLOST field value from a register. */
843 #define ALT_CLKMGR_INTREN_PERPLLLOST_GET(value) (((value) & 0x00000010) >> 4)
844 /* Produces a ALT_CLKMGR_INTREN_PERPLLLOST register field value suitable for setting the register. */
845 #define ALT_CLKMGR_INTREN_PERPLLLOST_SET(value) (((value) << 4) & 0x00000010)
846 
847 /*
848  * Field : SDRAM PLL Achieved Lock Interrupt Enable - sdrplllost
849  *
850  * When set to 1, the SDRAM PLL lost lock bit is ORed into the Clock Manager
851  * interrupt output. When set to 0 the SDRAM PLL lost lock bit is not ORed into
852  * the Clock Manager interrupt output.
853  *
854  * Field Access Macros:
855  *
856  */
857 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_SDRPLLLOST register field. */
858 #define ALT_CLKMGR_INTREN_SDRPLLLOST_LSB 5
859 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_SDRPLLLOST register field. */
860 #define ALT_CLKMGR_INTREN_SDRPLLLOST_MSB 5
861 /* The width in bits of the ALT_CLKMGR_INTREN_SDRPLLLOST register field. */
862 #define ALT_CLKMGR_INTREN_SDRPLLLOST_WIDTH 1
863 /* The mask used to set the ALT_CLKMGR_INTREN_SDRPLLLOST register field value. */
864 #define ALT_CLKMGR_INTREN_SDRPLLLOST_SET_MSK 0x00000020
865 /* The mask used to clear the ALT_CLKMGR_INTREN_SDRPLLLOST register field value. */
866 #define ALT_CLKMGR_INTREN_SDRPLLLOST_CLR_MSK 0xffffffdf
867 /* The reset value of the ALT_CLKMGR_INTREN_SDRPLLLOST register field. */
868 #define ALT_CLKMGR_INTREN_SDRPLLLOST_RESET 0x0
869 /* Extracts the ALT_CLKMGR_INTREN_SDRPLLLOST field value from a register. */
870 #define ALT_CLKMGR_INTREN_SDRPLLLOST_GET(value) (((value) & 0x00000020) >> 5)
871 /* Produces a ALT_CLKMGR_INTREN_SDRPLLLOST register field value suitable for setting the register. */
872 #define ALT_CLKMGR_INTREN_SDRPLLLOST_SET(value) (((value) << 5) & 0x00000020)
873 
874 #ifndef __ASSEMBLY__
875 /*
876  * WARNING: The C register and register group struct declarations are provided for
877  * convenience and illustrative purposes. They should, however, be used with
878  * caution as the C language standard provides no guarantees about the alignment or
879  * atomicity of device memory accesses. The recommended practice for writing
880  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
881  * alt_write_word() functions.
882  *
883  * The struct declaration for register ALT_CLKMGR_INTREN.
884  */
886 {
887  uint32_t mainpllachieved : 1; /* Main PLL Achieved Lock Interrupt Enable */
888  uint32_t perpllachieved : 1; /* Peripheral PLL Achieved Lock Interrupt Enable */
889  uint32_t sdrpllachieved : 1; /* SDRAM PLL Achieved Lock Interrupt Enable */
890  uint32_t mainplllost : 1; /* Main PLL Achieved Lock Interrupt Enable */
891  uint32_t perplllost : 1; /* Peripheral PLL Achieved Lock Interrupt Enable */
892  uint32_t sdrplllost : 1; /* SDRAM PLL Achieved Lock Interrupt Enable */
893  uint32_t : 26; /* *UNDEFINED* */
894 };
895 
896 /* The typedef declaration for register ALT_CLKMGR_INTREN. */
897 typedef volatile struct ALT_CLKMGR_INTREN_s ALT_CLKMGR_INTREN_t;
898 #endif /* __ASSEMBLY__ */
899 
900 /* The byte offset of the ALT_CLKMGR_INTREN register from the beginning of the component. */
901 #define ALT_CLKMGR_INTREN_OFST 0xc
902 
903 /*
904  * Register : Debug clock Control Register - dbctrl
905  *
906  * Contains fields that control the debug clocks.
907  *
908  * Register Layout
909  *
910  * Bits | Access | Reset | Description
911  * :-------|:-------|:------|:-------------------------------
912  * [0] | RW | 0x1 | Debug Clocks Stay on EOSC1_CLK
913  * [1] | RW | 0x1 | Debug Clocks Enable Safe Mode
914  * [31:2] | ??? | 0x0 | *UNDEFINED*
915  *
916  */
917 /*
918  * Field : Debug Clocks Stay on EOSC1_CLK - stayosc1
919  *
920  * When this bit is set the debug root clock (Main PLL C2 output) will always be
921  * bypassed to the EOSC1_clk independent of any other clock manager settings.
922  * When clear the debug source will be a function of register settings in the clock
923  * manager. Clocks affected by this bit are dbg_at_clk, dbg_clk, dbg_trace_clk,
924  * and dbg_timer_clk.
925  *
926  * The reset value for this bit is applied on a cold reset. Warm reset has no
927  * affect on this bit.
928  *
929  * Field Access Macros:
930  *
931  */
932 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_DBCTL_STAYOSC1 register field. */
933 #define ALT_CLKMGR_DBCTL_STAYOSC1_LSB 0
934 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_DBCTL_STAYOSC1 register field. */
935 #define ALT_CLKMGR_DBCTL_STAYOSC1_MSB 0
936 /* The width in bits of the ALT_CLKMGR_DBCTL_STAYOSC1 register field. */
937 #define ALT_CLKMGR_DBCTL_STAYOSC1_WIDTH 1
938 /* The mask used to set the ALT_CLKMGR_DBCTL_STAYOSC1 register field value. */
939 #define ALT_CLKMGR_DBCTL_STAYOSC1_SET_MSK 0x00000001
940 /* The mask used to clear the ALT_CLKMGR_DBCTL_STAYOSC1 register field value. */
941 #define ALT_CLKMGR_DBCTL_STAYOSC1_CLR_MSK 0xfffffffe
942 /* The reset value of the ALT_CLKMGR_DBCTL_STAYOSC1 register field. */
943 #define ALT_CLKMGR_DBCTL_STAYOSC1_RESET 0x1
944 /* Extracts the ALT_CLKMGR_DBCTL_STAYOSC1 field value from a register. */
945 #define ALT_CLKMGR_DBCTL_STAYOSC1_GET(value) (((value) & 0x00000001) >> 0)
946 /* Produces a ALT_CLKMGR_DBCTL_STAYOSC1 register field value suitable for setting the register. */
947 #define ALT_CLKMGR_DBCTL_STAYOSC1_SET(value) (((value) << 0) & 0x00000001)
948 
949 /*
950  * Field : Debug Clocks Enable Safe Mode - ensfmdwr
951  *
952  * When this bit is set the debug clocks will be affected by the assertion of Safe
953  * Mode on a warm reset if Stay OSC1 is not set.
954  *
955  * When this bit is clear the debug clocks will not be affected by the assertion of
956  * Safe Mode on a warm reset.
957  *
958  * If Debug Clocks are in Safe Mode they are taken out of Safe Mode when the Safe
959  * Mode bit is cleared independent of this bit.The reset value of this bit is
960  * applied on a cold reset; warm reset has no affect on this bit.
961  *
962  * Field Access Macros:
963  *
964  */
965 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_DBCTL_ENSFMDWR register field. */
966 #define ALT_CLKMGR_DBCTL_ENSFMDWR_LSB 1
967 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_DBCTL_ENSFMDWR register field. */
968 #define ALT_CLKMGR_DBCTL_ENSFMDWR_MSB 1
969 /* The width in bits of the ALT_CLKMGR_DBCTL_ENSFMDWR register field. */
970 #define ALT_CLKMGR_DBCTL_ENSFMDWR_WIDTH 1
971 /* The mask used to set the ALT_CLKMGR_DBCTL_ENSFMDWR register field value. */
972 #define ALT_CLKMGR_DBCTL_ENSFMDWR_SET_MSK 0x00000002
973 /* The mask used to clear the ALT_CLKMGR_DBCTL_ENSFMDWR register field value. */
974 #define ALT_CLKMGR_DBCTL_ENSFMDWR_CLR_MSK 0xfffffffd
975 /* The reset value of the ALT_CLKMGR_DBCTL_ENSFMDWR register field. */
976 #define ALT_CLKMGR_DBCTL_ENSFMDWR_RESET 0x1
977 /* Extracts the ALT_CLKMGR_DBCTL_ENSFMDWR field value from a register. */
978 #define ALT_CLKMGR_DBCTL_ENSFMDWR_GET(value) (((value) & 0x00000002) >> 1)
979 /* Produces a ALT_CLKMGR_DBCTL_ENSFMDWR register field value suitable for setting the register. */
980 #define ALT_CLKMGR_DBCTL_ENSFMDWR_SET(value) (((value) << 1) & 0x00000002)
981 
982 #ifndef __ASSEMBLY__
983 /*
984  * WARNING: The C register and register group struct declarations are provided for
985  * convenience and illustrative purposes. They should, however, be used with
986  * caution as the C language standard provides no guarantees about the alignment or
987  * atomicity of device memory accesses. The recommended practice for writing
988  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
989  * alt_write_word() functions.
990  *
991  * The struct declaration for register ALT_CLKMGR_DBCTL.
992  */
994 {
995  uint32_t stayosc1 : 1; /* Debug Clocks Stay on EOSC1_CLK */
996  uint32_t ensfmdwr : 1; /* Debug Clocks Enable Safe Mode */
997  uint32_t : 30; /* *UNDEFINED* */
998 };
999 
1000 /* The typedef declaration for register ALT_CLKMGR_DBCTL. */
1001 typedef volatile struct ALT_CLKMGR_DBCTL_s ALT_CLKMGR_DBCTL_t;
1002 #endif /* __ASSEMBLY__ */
1003 
1004 /* The byte offset of the ALT_CLKMGR_DBCTL register from the beginning of the component. */
1005 #define ALT_CLKMGR_DBCTL_OFST 0x10
1006 
1007 /*
1008  * Register : Status Register - stat
1009  *
1010  * Provides status of Hardware Managed Clock transition State Machine.
1011  *
1012  * Register Layout
1013  *
1014  * Bits | Access | Reset | Description
1015  * :-------|:-------|:------|:-----------------------
1016  * [0] | R | 0x0 | HW Managed Clocks BUSY
1017  * [31:1] | ??? | 0x0 | *UNDEFINED*
1018  *
1019  */
1020 /*
1021  * Field : HW Managed Clocks BUSY - busy
1022  *
1023  * This read only bit indicates that the Hardware Managed clock's state machine is
1024  * active. If the state machine is active, then the clocks are in transition.
1025  * Software should poll this bit after changing the source of internal clocks when
1026  * writing to the BYPASS, CTRL or DBCTRL registers. Immediately following writes
1027  * to any of these registers, SW should wait until this bit is IDLE before
1028  * proceeding with any other register writes in the Clock Manager.
1029  *
1030  * The reset value of this bit is applied on a cold reset; warm reset has no affect
1031  * on this bit.
1032  *
1033  * Field Enumeration Values:
1034  *
1035  * Enum | Value | Description
1036  * :----------------------------|:------|:---------------------
1037  * ALT_CLKMGR_STAT_BUSY_E_IDLE | 0x0 | Clocks stable
1038  * ALT_CLKMGR_STAT_BUSY_E_BUSY | 0x1 | Clocks in transition
1039  *
1040  * Field Access Macros:
1041  *
1042  */
1043 /*
1044  * Enumerated value for register field ALT_CLKMGR_STAT_BUSY
1045  *
1046  * Clocks stable
1047  */
1048 #define ALT_CLKMGR_STAT_BUSY_E_IDLE 0x0
1049 /*
1050  * Enumerated value for register field ALT_CLKMGR_STAT_BUSY
1051  *
1052  * Clocks in transition
1053  */
1054 #define ALT_CLKMGR_STAT_BUSY_E_BUSY 0x1
1055 
1056 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_STAT_BUSY register field. */
1057 #define ALT_CLKMGR_STAT_BUSY_LSB 0
1058 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_STAT_BUSY register field. */
1059 #define ALT_CLKMGR_STAT_BUSY_MSB 0
1060 /* The width in bits of the ALT_CLKMGR_STAT_BUSY register field. */
1061 #define ALT_CLKMGR_STAT_BUSY_WIDTH 1
1062 /* The mask used to set the ALT_CLKMGR_STAT_BUSY register field value. */
1063 #define ALT_CLKMGR_STAT_BUSY_SET_MSK 0x00000001
1064 /* The mask used to clear the ALT_CLKMGR_STAT_BUSY register field value. */
1065 #define ALT_CLKMGR_STAT_BUSY_CLR_MSK 0xfffffffe
1066 /* The reset value of the ALT_CLKMGR_STAT_BUSY register field. */
1067 #define ALT_CLKMGR_STAT_BUSY_RESET 0x0
1068 /* Extracts the ALT_CLKMGR_STAT_BUSY field value from a register. */
1069 #define ALT_CLKMGR_STAT_BUSY_GET(value) (((value) & 0x00000001) >> 0)
1070 /* Produces a ALT_CLKMGR_STAT_BUSY register field value suitable for setting the register. */
1071 #define ALT_CLKMGR_STAT_BUSY_SET(value) (((value) << 0) & 0x00000001)
1072 
1073 #ifndef __ASSEMBLY__
1074 /*
1075  * WARNING: The C register and register group struct declarations are provided for
1076  * convenience and illustrative purposes. They should, however, be used with
1077  * caution as the C language standard provides no guarantees about the alignment or
1078  * atomicity of device memory accesses. The recommended practice for writing
1079  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1080  * alt_write_word() functions.
1081  *
1082  * The struct declaration for register ALT_CLKMGR_STAT.
1083  */
1085 {
1086  const uint32_t busy : 1; /* HW Managed Clocks BUSY */
1087  uint32_t : 31; /* *UNDEFINED* */
1088 };
1089 
1090 /* The typedef declaration for register ALT_CLKMGR_STAT. */
1091 typedef volatile struct ALT_CLKMGR_STAT_s ALT_CLKMGR_STAT_t;
1092 #endif /* __ASSEMBLY__ */
1093 
1094 /* The byte offset of the ALT_CLKMGR_STAT register from the beginning of the component. */
1095 #define ALT_CLKMGR_STAT_OFST 0x14
1096 
1097 /*
1098  * Register Group : Main PLL Group - ALT_CLKMGR_MAINPLL
1099  * Main PLL Group
1100  *
1101  * Contains registers with settings for the Main PLL.
1102  *
1103  */
1104 /*
1105  * Register : Main PLL VCO Control Register - vco
1106  *
1107  * Contains settings that control the Main PLL VCO. The VCO output frequency is the
1108  * input frequency multiplied by the numerator (M+1) and divided by the denominator
1109  * (N+1). The VCO input clock source is always eosc1_clk.
1110  *
1111  * Fields are only reset by a cold reset.
1112  *
1113  * Register Layout
1114  *
1115  * Bits | Access | Reset | Description
1116  * :--------|:-------|:------|:--------------------------------
1117  * [0] | RW | 0x1 | BG PWRDN
1118  * [1] | RW | 0x0 | Enable
1119  * [2] | RW | 0x1 | Power down
1120  * [15:3] | RW | 0x1 | Numerator (M)
1121  * [21:16] | RW | 0x1 | Denominator (N)
1122  * [23:22] | ??? | 0x0 | *UNDEFINED*
1123  * [24] | RW | 0x0 | All Output Counter Reset
1124  * [30:25] | RW | 0x0 | Output Counter Reset
1125  * [31] | RW | 0x1 | External Regulator Input Select
1126  *
1127  */
1128 /*
1129  * Field : BG PWRDN - bgpwrdn
1130  *
1131  * If '1', powers down bandgap. If '0', bandgap is not power down.
1132  *
1133  * Field Access Macros:
1134  *
1135  */
1136 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field. */
1137 #define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_LSB 0
1138 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field. */
1139 #define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_MSB 0
1140 /* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field. */
1141 #define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_WIDTH 1
1142 /* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field value. */
1143 #define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_SET_MSK 0x00000001
1144 /* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field value. */
1145 #define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_CLR_MSK 0xfffffffe
1146 /* The reset value of the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field. */
1147 #define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_RESET 0x1
1148 /* Extracts the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN field value from a register. */
1149 #define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0)
1150 /* Produces a ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field value suitable for setting the register. */
1151 #define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_SET(value) (((value) << 0) & 0x00000001)
1152 
1153 /*
1154  * Field : Enable - en
1155  *
1156  * If '1', VCO is enabled. If '0', VCO is in reset.
1157  *
1158  * Field Access Macros:
1159  *
1160  */
1161 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_EN register field. */
1162 #define ALT_CLKMGR_MAINPLL_VCO_EN_LSB 1
1163 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_EN register field. */
1164 #define ALT_CLKMGR_MAINPLL_VCO_EN_MSB 1
1165 /* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_EN register field. */
1166 #define ALT_CLKMGR_MAINPLL_VCO_EN_WIDTH 1
1167 /* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_EN register field value. */
1168 #define ALT_CLKMGR_MAINPLL_VCO_EN_SET_MSK 0x00000002
1169 /* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_EN register field value. */
1170 #define ALT_CLKMGR_MAINPLL_VCO_EN_CLR_MSK 0xfffffffd
1171 /* The reset value of the ALT_CLKMGR_MAINPLL_VCO_EN register field. */
1172 #define ALT_CLKMGR_MAINPLL_VCO_EN_RESET 0x0
1173 /* Extracts the ALT_CLKMGR_MAINPLL_VCO_EN field value from a register. */
1174 #define ALT_CLKMGR_MAINPLL_VCO_EN_GET(value) (((value) & 0x00000002) >> 1)
1175 /* Produces a ALT_CLKMGR_MAINPLL_VCO_EN register field value suitable for setting the register. */
1176 #define ALT_CLKMGR_MAINPLL_VCO_EN_SET(value) (((value) << 1) & 0x00000002)
1177 
1178 /*
1179  * Field : Power down - pwrdn
1180  *
1181  * If '1', power down analog circuitry. If '0', analog circuitry not powered down.
1182  *
1183  * Field Access Macros:
1184  *
1185  */
1186 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field. */
1187 #define ALT_CLKMGR_MAINPLL_VCO_PWRDN_LSB 2
1188 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field. */
1189 #define ALT_CLKMGR_MAINPLL_VCO_PWRDN_MSB 2
1190 /* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field. */
1191 #define ALT_CLKMGR_MAINPLL_VCO_PWRDN_WIDTH 1
1192 /* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field value. */
1193 #define ALT_CLKMGR_MAINPLL_VCO_PWRDN_SET_MSK 0x00000004
1194 /* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field value. */
1195 #define ALT_CLKMGR_MAINPLL_VCO_PWRDN_CLR_MSK 0xfffffffb
1196 /* The reset value of the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field. */
1197 #define ALT_CLKMGR_MAINPLL_VCO_PWRDN_RESET 0x1
1198 /* Extracts the ALT_CLKMGR_MAINPLL_VCO_PWRDN field value from a register. */
1199 #define ALT_CLKMGR_MAINPLL_VCO_PWRDN_GET(value) (((value) & 0x00000004) >> 2)
1200 /* Produces a ALT_CLKMGR_MAINPLL_VCO_PWRDN register field value suitable for setting the register. */
1201 #define ALT_CLKMGR_MAINPLL_VCO_PWRDN_SET(value) (((value) << 2) & 0x00000004)
1202 
1203 /*
1204  * Field : Numerator (M) - numer
1205  *
1206  * Numerator in VCO output frequency equation. For incremental frequency change, if
1207  * the new value lead to less than 20% of the frequency change, this value can be
1208  * changed without resetting the PLL. The Numerator and Denominator can not be
1209  * changed at the same time for incremental frequency changed.
1210  *
1211  * Field Access Macros:
1212  *
1213  */
1214 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_NUMER register field. */
1215 #define ALT_CLKMGR_MAINPLL_VCO_NUMER_LSB 3
1216 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_NUMER register field. */
1217 #define ALT_CLKMGR_MAINPLL_VCO_NUMER_MSB 15
1218 /* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_NUMER register field. */
1219 #define ALT_CLKMGR_MAINPLL_VCO_NUMER_WIDTH 13
1220 /* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_NUMER register field value. */
1221 #define ALT_CLKMGR_MAINPLL_VCO_NUMER_SET_MSK 0x0000fff8
1222 /* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_NUMER register field value. */
1223 #define ALT_CLKMGR_MAINPLL_VCO_NUMER_CLR_MSK 0xffff0007
1224 /* The reset value of the ALT_CLKMGR_MAINPLL_VCO_NUMER register field. */
1225 #define ALT_CLKMGR_MAINPLL_VCO_NUMER_RESET 0x1
1226 /* Extracts the ALT_CLKMGR_MAINPLL_VCO_NUMER field value from a register. */
1227 #define ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(value) (((value) & 0x0000fff8) >> 3)
1228 /* Produces a ALT_CLKMGR_MAINPLL_VCO_NUMER register field value suitable for setting the register. */
1229 #define ALT_CLKMGR_MAINPLL_VCO_NUMER_SET(value) (((value) << 3) & 0x0000fff8)
1230 
1231 /*
1232  * Field : Denominator (N) - denom
1233  *
1234  * Denominator in VCO output frequency equation. For incremental frequency change,
1235  * if the new value lead to less than 20% of the frequency change, this value can
1236  * be changed without resetting the PLL. The Numerator and Denominator can not be
1237  * changed at the same time for incremental frequency changed.
1238  *
1239  * Field Access Macros:
1240  *
1241  */
1242 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_DENOM register field. */
1243 #define ALT_CLKMGR_MAINPLL_VCO_DENOM_LSB 16
1244 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_DENOM register field. */
1245 #define ALT_CLKMGR_MAINPLL_VCO_DENOM_MSB 21
1246 /* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_DENOM register field. */
1247 #define ALT_CLKMGR_MAINPLL_VCO_DENOM_WIDTH 6
1248 /* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_DENOM register field value. */
1249 #define ALT_CLKMGR_MAINPLL_VCO_DENOM_SET_MSK 0x003f0000
1250 /* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_DENOM register field value. */
1251 #define ALT_CLKMGR_MAINPLL_VCO_DENOM_CLR_MSK 0xffc0ffff
1252 /* The reset value of the ALT_CLKMGR_MAINPLL_VCO_DENOM register field. */
1253 #define ALT_CLKMGR_MAINPLL_VCO_DENOM_RESET 0x1
1254 /* Extracts the ALT_CLKMGR_MAINPLL_VCO_DENOM field value from a register. */
1255 #define ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(value) (((value) & 0x003f0000) >> 16)
1256 /* Produces a ALT_CLKMGR_MAINPLL_VCO_DENOM register field value suitable for setting the register. */
1257 #define ALT_CLKMGR_MAINPLL_VCO_DENOM_SET(value) (((value) << 16) & 0x003f0000)
1258 
1259 /*
1260  * Field : All Output Counter Reset - outresetall
1261  *
1262  * Before releasing Bypass, All Output Counter Reset must be set and cleared by
1263  * software for correct clock operation.
1264  *
1265  * If '1', Reset phase multiplexer and all output counter state. So that after the
1266  * assertion all the clocks output are start from rising edge align.
1267  *
1268  * If '0', phase multiplexer and output counter state not reset and no change to
1269  * the phase of the clock outputs.
1270  *
1271  * Field Access Macros:
1272  *
1273  */
1274 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field. */
1275 #define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_LSB 24
1276 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field. */
1277 #define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_MSB 24
1278 /* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field. */
1279 #define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_WIDTH 1
1280 /* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field value. */
1281 #define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_SET_MSK 0x01000000
1282 /* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field value. */
1283 #define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_CLR_MSK 0xfeffffff
1284 /* The reset value of the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field. */
1285 #define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_RESET 0x0
1286 /* Extracts the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL field value from a register. */
1287 #define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_GET(value) (((value) & 0x01000000) >> 24)
1288 /* Produces a ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field value suitable for setting the register. */
1289 #define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_SET(value) (((value) << 24) & 0x01000000)
1290 
1291 /*
1292  * Field : Output Counter Reset - outreset
1293  *
1294  * Resets the individual PLL output counter.
1295  *
1296  * For software to change the PLL output counter without producing glitches on the
1297  * respective clock, SW must set the VCO register respective Output Counter Reset
1298  * bit. Software then polls the respective Output Counter Reset Acknowledge bit in
1299  * the Output Counter Reset Ack Status Register. Software then writes the
1300  * appropriate counter register, and then clears the respective VCO register Output
1301  * Counter Reset bit.
1302  *
1303  * LSB 'outreset[0]' corresponds to PLL output clock C0, etc.
1304  *
1305  * If set to '1', reset output divider, no clock output from counter.
1306  *
1307  * If set to '0', counter is not reset.
1308  *
1309  * The reset value of this bit is applied on a cold reset; warm reset has no affect
1310  * on this bit.
1311  *
1312  * Field Access Macros:
1313  *
1314  */
1315 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field. */
1316 #define ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB 25
1317 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field. */
1318 #define ALT_CLKMGR_MAINPLL_VCO_OUTRST_MSB 30
1319 /* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field. */
1320 #define ALT_CLKMGR_MAINPLL_VCO_OUTRST_WIDTH 6
1321 /* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field value. */
1322 #define ALT_CLKMGR_MAINPLL_VCO_OUTRST_SET_MSK 0x7e000000
1323 /* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field value. */
1324 #define ALT_CLKMGR_MAINPLL_VCO_OUTRST_CLR_MSK 0x81ffffff
1325 /* The reset value of the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field. */
1326 #define ALT_CLKMGR_MAINPLL_VCO_OUTRST_RESET 0x0
1327 /* Extracts the ALT_CLKMGR_MAINPLL_VCO_OUTRST field value from a register. */
1328 #define ALT_CLKMGR_MAINPLL_VCO_OUTRST_GET(value) (((value) & 0x7e000000) >> 25)
1329 /* Produces a ALT_CLKMGR_MAINPLL_VCO_OUTRST register field value suitable for setting the register. */
1330 #define ALT_CLKMGR_MAINPLL_VCO_OUTRST_SET(value) (((value) << 25) & 0x7e000000)
1331 
1332 /*
1333  * Field : External Regulator Input Select - regextsel
1334  *
1335  * If set to '1', the external regulator is selected for the PLL.
1336  *
1337  * If set to '0', the internal regulator is slected.
1338  *
1339  * It is strongly recommended to select the external regulator while the PLL is not
1340  * enabled (in reset), and then disable the external regulater once the PLL
1341  * becomes enabled. Software should simulateously update the 'Enable' bit and the
1342  * 'External Regulator Input Select' in the same write access to the VCO register.
1343  * When the 'Enable' bit is clear, the 'External Regulator Input Select' should be
1344  * set, and vice versa.
1345  *
1346  * The reset value of this bit is applied on a cold reset; warm reset has no affect
1347  * on this bit.
1348  *
1349  * Field Access Macros:
1350  *
1351  */
1352 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field. */
1353 #define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_LSB 31
1354 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field. */
1355 #define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_MSB 31
1356 /* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field. */
1357 #define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_WIDTH 1
1358 /* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field value. */
1359 #define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_SET_MSK 0x80000000
1360 /* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field value. */
1361 #define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_CLR_MSK 0x7fffffff
1362 /* The reset value of the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field. */
1363 #define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_RESET 0x1
1364 /* Extracts the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL field value from a register. */
1365 #define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_GET(value) (((value) & 0x80000000) >> 31)
1366 /* Produces a ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field value suitable for setting the register. */
1367 #define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_SET(value) (((value) << 31) & 0x80000000)
1368 
1369 #ifndef __ASSEMBLY__
1370 /*
1371  * WARNING: The C register and register group struct declarations are provided for
1372  * convenience and illustrative purposes. They should, however, be used with
1373  * caution as the C language standard provides no guarantees about the alignment or
1374  * atomicity of device memory accesses. The recommended practice for writing
1375  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1376  * alt_write_word() functions.
1377  *
1378  * The struct declaration for register ALT_CLKMGR_MAINPLL_VCO.
1379  */
1381 {
1382  uint32_t bgpwrdn : 1; /* BG PWRDN */
1383  uint32_t en : 1; /* Enable */
1384  uint32_t pwrdn : 1; /* Power down */
1385  uint32_t numer : 13; /* Numerator (M) */
1386  uint32_t denom : 6; /* Denominator (N) */
1387  uint32_t : 2; /* *UNDEFINED* */
1388  uint32_t outresetall : 1; /* All Output Counter Reset */
1389  uint32_t outreset : 6; /* Output Counter Reset */
1390  uint32_t regextsel : 1; /* External Regulator Input Select */
1391 };
1392 
1393 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_VCO. */
1394 typedef volatile struct ALT_CLKMGR_MAINPLL_VCO_s ALT_CLKMGR_MAINPLL_VCO_t;
1395 #endif /* __ASSEMBLY__ */
1396 
1397 /* The byte offset of the ALT_CLKMGR_MAINPLL_VCO register from the beginning of the component. */
1398 #define ALT_CLKMGR_MAINPLL_VCO_OFST 0x0
1399 
1400 /*
1401  * Register : Main PLL VCO Advanced Control Register - misc
1402  *
1403  * Contains VCO control signals and other PLL control signals need to be
1404  * controllable through register.
1405  *
1406  * Fields are only reset by a cold reset.
1407  *
1408  * Register Layout
1409  *
1410  * Bits | Access | Reset | Description
1411  * :--------|:-------|:------|:------------------------------
1412  * [0] | RW | 0x0 | Loop Bandwidth Adjust Enabled
1413  * [12:1] | RW | 0x1 | Loop Bandwidth Adjust
1414  * [13] | RW | 0x0 | Fast Locking Enable
1415  * [14] | RW | 0x1 | Saturation Enable
1416  * [31:15] | ??? | 0x0 | *UNDEFINED*
1417  *
1418  */
1419 /*
1420  * Field : Loop Bandwidth Adjust Enabled - bwadjen
1421  *
1422  * If set to 1, the Loop Bandwidth Adjust value comes from the Loop Bandwidth
1423  * Adjust field.
1424  *
1425  * If set to 0, the Loop Bandwidth Adjust value equals the M field divided by 2
1426  * value of the VCO Control Register. The M divided by 2 is the upper 12 bits
1427  * (12:1) of the M field in the VCO register.
1428  *
1429  * Field Access Macros:
1430  *
1431  */
1432 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field. */
1433 #define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_LSB 0
1434 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field. */
1435 #define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_MSB 0
1436 /* The width in bits of the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field. */
1437 #define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_WIDTH 1
1438 /* The mask used to set the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field value. */
1439 #define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_SET_MSK 0x00000001
1440 /* The mask used to clear the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field value. */
1441 #define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_CLR_MSK 0xfffffffe
1442 /* The reset value of the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field. */
1443 #define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_RESET 0x0
1444 /* Extracts the ALT_CLKMGR_MAINPLL_MISC_BWADJEN field value from a register. */
1445 #define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_GET(value) (((value) & 0x00000001) >> 0)
1446 /* Produces a ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field value suitable for setting the register. */
1447 #define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_SET(value) (((value) << 0) & 0x00000001)
1448 
1449 /*
1450  * Field : Loop Bandwidth Adjust - bwadj
1451  *
1452  * Provides Loop Bandwidth Adjust value.
1453  *
1454  * Field Access Macros:
1455  *
1456  */
1457 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field. */
1458 #define ALT_CLKMGR_MAINPLL_MISC_BWADJ_LSB 1
1459 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field. */
1460 #define ALT_CLKMGR_MAINPLL_MISC_BWADJ_MSB 12
1461 /* The width in bits of the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field. */
1462 #define ALT_CLKMGR_MAINPLL_MISC_BWADJ_WIDTH 12
1463 /* The mask used to set the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field value. */
1464 #define ALT_CLKMGR_MAINPLL_MISC_BWADJ_SET_MSK 0x00001ffe
1465 /* The mask used to clear the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field value. */
1466 #define ALT_CLKMGR_MAINPLL_MISC_BWADJ_CLR_MSK 0xffffe001
1467 /* The reset value of the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field. */
1468 #define ALT_CLKMGR_MAINPLL_MISC_BWADJ_RESET 0x1
1469 /* Extracts the ALT_CLKMGR_MAINPLL_MISC_BWADJ field value from a register. */
1470 #define ALT_CLKMGR_MAINPLL_MISC_BWADJ_GET(value) (((value) & 0x00001ffe) >> 1)
1471 /* Produces a ALT_CLKMGR_MAINPLL_MISC_BWADJ register field value suitable for setting the register. */
1472 #define ALT_CLKMGR_MAINPLL_MISC_BWADJ_SET(value) (((value) << 1) & 0x00001ffe)
1473 
1474 /*
1475  * Field : Fast Locking Enable - fasten
1476  *
1477  * Enables fast locking circuit.
1478  *
1479  * Field Access Macros:
1480  *
1481  */
1482 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field. */
1483 #define ALT_CLKMGR_MAINPLL_MISC_FASTEN_LSB 13
1484 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field. */
1485 #define ALT_CLKMGR_MAINPLL_MISC_FASTEN_MSB 13
1486 /* The width in bits of the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field. */
1487 #define ALT_CLKMGR_MAINPLL_MISC_FASTEN_WIDTH 1
1488 /* The mask used to set the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field value. */
1489 #define ALT_CLKMGR_MAINPLL_MISC_FASTEN_SET_MSK 0x00002000
1490 /* The mask used to clear the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field value. */
1491 #define ALT_CLKMGR_MAINPLL_MISC_FASTEN_CLR_MSK 0xffffdfff
1492 /* The reset value of the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field. */
1493 #define ALT_CLKMGR_MAINPLL_MISC_FASTEN_RESET 0x0
1494 /* Extracts the ALT_CLKMGR_MAINPLL_MISC_FASTEN field value from a register. */
1495 #define ALT_CLKMGR_MAINPLL_MISC_FASTEN_GET(value) (((value) & 0x00002000) >> 13)
1496 /* Produces a ALT_CLKMGR_MAINPLL_MISC_FASTEN register field value suitable for setting the register. */
1497 #define ALT_CLKMGR_MAINPLL_MISC_FASTEN_SET(value) (((value) << 13) & 0x00002000)
1498 
1499 /*
1500  * Field : Saturation Enable - saten
1501  *
1502  * Enables saturation behavior.
1503  *
1504  * Field Access Macros:
1505  *
1506  */
1507 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MISC_SATEN register field. */
1508 #define ALT_CLKMGR_MAINPLL_MISC_SATEN_LSB 14
1509 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MISC_SATEN register field. */
1510 #define ALT_CLKMGR_MAINPLL_MISC_SATEN_MSB 14
1511 /* The width in bits of the ALT_CLKMGR_MAINPLL_MISC_SATEN register field. */
1512 #define ALT_CLKMGR_MAINPLL_MISC_SATEN_WIDTH 1
1513 /* The mask used to set the ALT_CLKMGR_MAINPLL_MISC_SATEN register field value. */
1514 #define ALT_CLKMGR_MAINPLL_MISC_SATEN_SET_MSK 0x00004000
1515 /* The mask used to clear the ALT_CLKMGR_MAINPLL_MISC_SATEN register field value. */
1516 #define ALT_CLKMGR_MAINPLL_MISC_SATEN_CLR_MSK 0xffffbfff
1517 /* The reset value of the ALT_CLKMGR_MAINPLL_MISC_SATEN register field. */
1518 #define ALT_CLKMGR_MAINPLL_MISC_SATEN_RESET 0x1
1519 /* Extracts the ALT_CLKMGR_MAINPLL_MISC_SATEN field value from a register. */
1520 #define ALT_CLKMGR_MAINPLL_MISC_SATEN_GET(value) (((value) & 0x00004000) >> 14)
1521 /* Produces a ALT_CLKMGR_MAINPLL_MISC_SATEN register field value suitable for setting the register. */
1522 #define ALT_CLKMGR_MAINPLL_MISC_SATEN_SET(value) (((value) << 14) & 0x00004000)
1523 
1524 #ifndef __ASSEMBLY__
1525 /*
1526  * WARNING: The C register and register group struct declarations are provided for
1527  * convenience and illustrative purposes. They should, however, be used with
1528  * caution as the C language standard provides no guarantees about the alignment or
1529  * atomicity of device memory accesses. The recommended practice for writing
1530  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1531  * alt_write_word() functions.
1532  *
1533  * The struct declaration for register ALT_CLKMGR_MAINPLL_MISC.
1534  */
1536 {
1537  uint32_t bwadjen : 1; /* Loop Bandwidth Adjust Enabled */
1538  uint32_t bwadj : 12; /* Loop Bandwidth Adjust */
1539  uint32_t fasten : 1; /* Fast Locking Enable */
1540  uint32_t saten : 1; /* Saturation Enable */
1541  uint32_t : 17; /* *UNDEFINED* */
1542 };
1543 
1544 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_MISC. */
1545 typedef volatile struct ALT_CLKMGR_MAINPLL_MISC_s ALT_CLKMGR_MAINPLL_MISC_t;
1546 #endif /* __ASSEMBLY__ */
1547 
1548 /* The byte offset of the ALT_CLKMGR_MAINPLL_MISC register from the beginning of the component. */
1549 #define ALT_CLKMGR_MAINPLL_MISC_OFST 0x4
1550 
1551 /*
1552  * Register : Main PLL C0 Control Register for Clock mpu_clk - mpuclk
1553  *
1554  * Contains settings that control clock mpu_clk generated from the C0 output of the
1555  * Main PLL.
1556  *
1557  * Only reset by a cold reset.
1558  *
1559  * Register Layout
1560  *
1561  * Bits | Access | Reset | Description
1562  * :-------|:-------|:------|:------------
1563  * [8:0] | RW | 0x0 | Counter
1564  * [31:9] | ??? | 0x0 | *UNDEFINED*
1565  *
1566  */
1567 /*
1568  * Field : Counter - cnt
1569  *
1570  * Divides the VCO/2 frequency by the value+1 in this field.
1571  *
1572  * Field Access Macros:
1573  *
1574  */
1575 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */
1576 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_LSB 0
1577 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */
1578 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_MSB 8
1579 /* The width in bits of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */
1580 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_WIDTH 9
1581 /* The mask used to set the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field value. */
1582 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_SET_MSK 0x000001ff
1583 /* The mask used to clear the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field value. */
1584 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_CLR_MSK 0xfffffe00
1585 /* The reset value of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */
1586 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_RESET 0x0
1587 /* Extracts the ALT_CLKMGR_MAINPLL_MPUCLK_CNT field value from a register. */
1588 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
1589 /* Produces a ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field value suitable for setting the register. */
1590 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
1591 
1592 #ifndef __ASSEMBLY__
1593 /*
1594  * WARNING: The C register and register group struct declarations are provided for
1595  * convenience and illustrative purposes. They should, however, be used with
1596  * caution as the C language standard provides no guarantees about the alignment or
1597  * atomicity of device memory accesses. The recommended practice for writing
1598  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1599  * alt_write_word() functions.
1600  *
1601  * The struct declaration for register ALT_CLKMGR_MAINPLL_MPUCLK.
1602  */
1604 {
1605  uint32_t cnt : 9; /* Counter */
1606  uint32_t : 23; /* *UNDEFINED* */
1607 };
1608 
1609 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_MPUCLK. */
1610 typedef volatile struct ALT_CLKMGR_MAINPLL_MPUCLK_s ALT_CLKMGR_MAINPLL_MPUCLK_t;
1611 #endif /* __ASSEMBLY__ */
1612 
1613 /* The byte offset of the ALT_CLKMGR_MAINPLL_MPUCLK register from the beginning of the component. */
1614 #define ALT_CLKMGR_MAINPLL_MPUCLK_OFST 0x8
1615 
1616 /*
1617  * Register : Main PLL C1 Control Register for Clock main_clk - mainclk
1618  *
1619  * Contains settings that control clock main_clk generated from the C1 output of
1620  * the Main PLL.
1621  *
1622  * Only reset by a cold reset.
1623  *
1624  * Register Layout
1625  *
1626  * Bits | Access | Reset | Description
1627  * :-------|:-------|:------|:------------
1628  * [8:0] | RW | 0x0 | Counter
1629  * [31:9] | ??? | 0x0 | *UNDEFINED*
1630  *
1631  */
1632 /*
1633  * Field : Counter - cnt
1634  *
1635  * Divides the VCO/4 frequency by the value+1 in this field.
1636  *
1637  * Field Access Macros:
1638  *
1639  */
1640 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field. */
1641 #define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_LSB 0
1642 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field. */
1643 #define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_MSB 8
1644 /* The width in bits of the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field. */
1645 #define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_WIDTH 9
1646 /* The mask used to set the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field value. */
1647 #define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_SET_MSK 0x000001ff
1648 /* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field value. */
1649 #define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_CLR_MSK 0xfffffe00
1650 /* The reset value of the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field. */
1651 #define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_RESET 0x0
1652 /* Extracts the ALT_CLKMGR_MAINPLL_MAINCLK_CNT field value from a register. */
1653 #define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
1654 /* Produces a ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field value suitable for setting the register. */
1655 #define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
1656 
1657 #ifndef __ASSEMBLY__
1658 /*
1659  * WARNING: The C register and register group struct declarations are provided for
1660  * convenience and illustrative purposes. They should, however, be used with
1661  * caution as the C language standard provides no guarantees about the alignment or
1662  * atomicity of device memory accesses. The recommended practice for writing
1663  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1664  * alt_write_word() functions.
1665  *
1666  * The struct declaration for register ALT_CLKMGR_MAINPLL_MAINCLK.
1667  */
1669 {
1670  uint32_t cnt : 9; /* Counter */
1671  uint32_t : 23; /* *UNDEFINED* */
1672 };
1673 
1674 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_MAINCLK. */
1675 typedef volatile struct ALT_CLKMGR_MAINPLL_MAINCLK_s ALT_CLKMGR_MAINPLL_MAINCLK_t;
1676 #endif /* __ASSEMBLY__ */
1677 
1678 /* The byte offset of the ALT_CLKMGR_MAINPLL_MAINCLK register from the beginning of the component. */
1679 #define ALT_CLKMGR_MAINPLL_MAINCLK_OFST 0xc
1680 
1681 /*
1682  * Register : Main PLL C2 Control Register for Clock dbg_base_clk - dbgatclk
1683  *
1684  * Contains settings that control clock dbg_base_clk generated from the C2 output
1685  * of the Main PLL.
1686  *
1687  * Only reset by a cold reset.
1688  *
1689  * Register Layout
1690  *
1691  * Bits | Access | Reset | Description
1692  * :-------|:-------|:------|:------------
1693  * [8:0] | RW | 0x0 | Counter
1694  * [31:9] | ??? | 0x0 | *UNDEFINED*
1695  *
1696  */
1697 /*
1698  * Field : Counter - cnt
1699  *
1700  * Divides the VCO/4 frequency by the value+1 in this field.
1701  *
1702  * Field Access Macros:
1703  *
1704  */
1705 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field. */
1706 #define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_LSB 0
1707 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field. */
1708 #define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_MSB 8
1709 /* The width in bits of the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field. */
1710 #define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_WIDTH 9
1711 /* The mask used to set the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field value. */
1712 #define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_SET_MSK 0x000001ff
1713 /* The mask used to clear the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field value. */
1714 #define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_CLR_MSK 0xfffffe00
1715 /* The reset value of the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field. */
1716 #define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_RESET 0x0
1717 /* Extracts the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT field value from a register. */
1718 #define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
1719 /* Produces a ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field value suitable for setting the register. */
1720 #define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
1721 
1722 #ifndef __ASSEMBLY__
1723 /*
1724  * WARNING: The C register and register group struct declarations are provided for
1725  * convenience and illustrative purposes. They should, however, be used with
1726  * caution as the C language standard provides no guarantees about the alignment or
1727  * atomicity of device memory accesses. The recommended practice for writing
1728  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1729  * alt_write_word() functions.
1730  *
1731  * The struct declaration for register ALT_CLKMGR_MAINPLL_DBGATCLK.
1732  */
1734 {
1735  uint32_t cnt : 9; /* Counter */
1736  uint32_t : 23; /* *UNDEFINED* */
1737 };
1738 
1739 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_DBGATCLK. */
1740 typedef volatile struct ALT_CLKMGR_MAINPLL_DBGATCLK_s ALT_CLKMGR_MAINPLL_DBGATCLK_t;
1741 #endif /* __ASSEMBLY__ */
1742 
1743 /* The byte offset of the ALT_CLKMGR_MAINPLL_DBGATCLK register from the beginning of the component. */
1744 #define ALT_CLKMGR_MAINPLL_DBGATCLK_OFST 0x10
1745 
1746 /*
1747  * Register : Main PLL C3 Control Register for Clock main_qspi_clk - mainqspiclk
1748  *
1749  * Contains settings that control clock main_qspi_clk generated from the C3 output
1750  * of the Main PLL.
1751  *
1752  * Only reset by a cold reset.
1753  *
1754  * Register Layout
1755  *
1756  * Bits | Access | Reset | Description
1757  * :-------|:-------|:------|:------------
1758  * [8:0] | RW | 0x3 | Counter
1759  * [31:9] | ??? | 0x0 | *UNDEFINED*
1760  *
1761  */
1762 /*
1763  * Field : Counter - cnt
1764  *
1765  * Divides the VCO frequency by the value+1 in this field.
1766  *
1767  * Field Access Macros:
1768  *
1769  */
1770 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field. */
1771 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_LSB 0
1772 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field. */
1773 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_MSB 8
1774 /* The width in bits of the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field. */
1775 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_WIDTH 9
1776 /* The mask used to set the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field value. */
1777 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_SET_MSK 0x000001ff
1778 /* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field value. */
1779 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_CLR_MSK 0xfffffe00
1780 /* The reset value of the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field. */
1781 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_RESET 0x3
1782 /* Extracts the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT field value from a register. */
1783 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
1784 /* Produces a ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field value suitable for setting the register. */
1785 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
1786 
1787 #ifndef __ASSEMBLY__
1788 /*
1789  * WARNING: The C register and register group struct declarations are provided for
1790  * convenience and illustrative purposes. They should, however, be used with
1791  * caution as the C language standard provides no guarantees about the alignment or
1792  * atomicity of device memory accesses. The recommended practice for writing
1793  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1794  * alt_write_word() functions.
1795  *
1796  * The struct declaration for register ALT_CLKMGR_MAINPLL_MAINQSPICLK.
1797  */
1799 {
1800  uint32_t cnt : 9; /* Counter */
1801  uint32_t : 23; /* *UNDEFINED* */
1802 };
1803 
1804 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_MAINQSPICLK. */
1805 typedef volatile struct ALT_CLKMGR_MAINPLL_MAINQSPICLK_s ALT_CLKMGR_MAINPLL_MAINQSPICLK_t;
1806 #endif /* __ASSEMBLY__ */
1807 
1808 /* The byte offset of the ALT_CLKMGR_MAINPLL_MAINQSPICLK register from the beginning of the component. */
1809 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_OFST 0x14
1810 
1811 /*
1812  * Register : Main PLL C4 Control Register for Clock main_nand_sdmmc_clk - mainnandsdmmcclk
1813  *
1814  * Contains settings that control clock main_nand_sdmmc_clk generated from the C4
1815  * output of the Main PLL.
1816  *
1817  * Only reset by a cold reset.
1818  *
1819  * Register Layout
1820  *
1821  * Bits | Access | Reset | Description
1822  * :-------|:-------|:------|:------------
1823  * [8:0] | RW | 0x3 | Counter
1824  * [31:9] | ??? | 0x0 | *UNDEFINED*
1825  *
1826  */
1827 /*
1828  * Field : Counter - cnt
1829  *
1830  * Divides the VCO frequency by the value+1 in this field.
1831  *
1832  * Field Access Macros:
1833  *
1834  */
1835 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field. */
1836 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_LSB 0
1837 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field. */
1838 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_MSB 8
1839 /* The width in bits of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field. */
1840 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_WIDTH 9
1841 /* The mask used to set the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field value. */
1842 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_SET_MSK 0x000001ff
1843 /* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field value. */
1844 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_CLR_MSK 0xfffffe00
1845 /* The reset value of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field. */
1846 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_RESET 0x3
1847 /* Extracts the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT field value from a register. */
1848 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
1849 /* Produces a ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field value suitable for setting the register. */
1850 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
1851 
1852 #ifndef __ASSEMBLY__
1853 /*
1854  * WARNING: The C register and register group struct declarations are provided for
1855  * convenience and illustrative purposes. They should, however, be used with
1856  * caution as the C language standard provides no guarantees about the alignment or
1857  * atomicity of device memory accesses. The recommended practice for writing
1858  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1859  * alt_write_word() functions.
1860  *
1861  * The struct declaration for register ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK.
1862  */
1864 {
1865  uint32_t cnt : 9; /* Counter */
1866  uint32_t : 23; /* *UNDEFINED* */
1867 };
1868 
1869 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK. */
1870 typedef volatile struct ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_s ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_t;
1871 #endif /* __ASSEMBLY__ */
1872 
1873 /* The byte offset of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK register from the beginning of the component. */
1874 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_OFST 0x18
1875 
1876 /*
1877  * Register : Main PLL C5 Control Register for Clock cfg_s2f_user0_clk - cfgs2fuser0clk
1878  *
1879  * Contains settings that control clock cfg_s2f_user0_clk generated from the C5
1880  * output of the Main PLL.
1881  *
1882  * Qsys and user documenation refer to cfg_s2f_user0_clk as cfg_h2f_user0_clk.
1883  *
1884  * Only reset by a cold reset.
1885  *
1886  * Register Layout
1887  *
1888  * Bits | Access | Reset | Description
1889  * :-------|:-------|:------|:------------
1890  * [8:0] | RW | 0xf | Counter
1891  * [31:9] | ??? | 0x0 | *UNDEFINED*
1892  *
1893  */
1894 /*
1895  * Field : Counter - cnt
1896  *
1897  * Divides the VCO frequency by the value+1 in this field.
1898  *
1899  * Field Access Macros:
1900  *
1901  */
1902 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field. */
1903 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_LSB 0
1904 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field. */
1905 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_MSB 8
1906 /* The width in bits of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field. */
1907 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_WIDTH 9
1908 /* The mask used to set the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field value. */
1909 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_SET_MSK 0x000001ff
1910 /* The mask used to clear the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field value. */
1911 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_CLR_MSK 0xfffffe00
1912 /* The reset value of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field. */
1913 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_RESET 0xf
1914 /* Extracts the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT field value from a register. */
1915 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
1916 /* Produces a ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field value suitable for setting the register. */
1917 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
1918 
1919 #ifndef __ASSEMBLY__
1920 /*
1921  * WARNING: The C register and register group struct declarations are provided for
1922  * convenience and illustrative purposes. They should, however, be used with
1923  * caution as the C language standard provides no guarantees about the alignment or
1924  * atomicity of device memory accesses. The recommended practice for writing
1925  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1926  * alt_write_word() functions.
1927  *
1928  * The struct declaration for register ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK.
1929  */
1931 {
1932  uint32_t cnt : 9; /* Counter */
1933  uint32_t : 23; /* *UNDEFINED* */
1934 };
1935 
1936 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK. */
1937 typedef volatile struct ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_s ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_t;
1938 #endif /* __ASSEMBLY__ */
1939 
1940 /* The byte offset of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK register from the beginning of the component. */
1941 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_OFST 0x1c
1942 
1943 /*
1944  * Register : Enable Register - en
1945  *
1946  * Contains fields that control clock enables for clocks derived from the Main PLL.
1947  *
1948  * 1: The clock is enabled.
1949  *
1950  * 0: The clock is disabled.
1951  *
1952  * Fields are only reset by a cold reset.
1953  *
1954  * Register Layout
1955  *
1956  * Bits | Access | Reset | Description
1957  * :--------|:-------|:------|:---------------------
1958  * [0] | RW | 0x1 | l4_main_clk Enable
1959  * [1] | RW | 0x1 | l3_mp_clk Enable
1960  * [2] | RW | 0x1 | l4_mp_clk Enable
1961  * [3] | RW | 0x1 | l4_sp_clk Enable
1962  * [4] | RW | 0x1 | dbg_at_clk Enable
1963  * [5] | RW | 0x1 | dbg_clk Enable
1964  * [6] | RW | 0x1 | dbg_trace_clk Enable
1965  * [7] | RW | 0x1 | dbg_timer_clk Enable
1966  * [8] | RW | 0x1 | cfg_clk Enable
1967  * [9] | RW | 0x1 | s2f_user0_clk Enable
1968  * [31:10] | ??? | 0x0 | *UNDEFINED*
1969  *
1970  */
1971 /*
1972  * Field : l4_main_clk Enable - l4mainclk
1973  *
1974  * Enables clock l4_main_clk output
1975  *
1976  * Field Access Macros:
1977  *
1978  */
1979 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field. */
1980 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_LSB 0
1981 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field. */
1982 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_MSB 0
1983 /* The width in bits of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field. */
1984 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_WIDTH 1
1985 /* The mask used to set the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field value. */
1986 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET_MSK 0x00000001
1987 /* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field value. */
1988 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_CLR_MSK 0xfffffffe
1989 /* The reset value of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field. */
1990 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_RESET 0x1
1991 /* Extracts the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK field value from a register. */
1992 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_GET(value) (((value) & 0x00000001) >> 0)
1993 /* Produces a ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field value suitable for setting the register. */
1994 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET(value) (((value) << 0) & 0x00000001)
1995 
1996 /*
1997  * Field : l3_mp_clk Enable - l3mpclk
1998  *
1999  * Enables clock l3_mp_clk output
2000  *
2001  * Field Access Macros:
2002  *
2003  */
2004 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field. */
2005 #define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_LSB 1
2006 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field. */
2007 #define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_MSB 1
2008 /* The width in bits of the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field. */
2009 #define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_WIDTH 1
2010 /* The mask used to set the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field value. */
2011 #define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK 0x00000002
2012 /* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field value. */
2013 #define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_CLR_MSK 0xfffffffd
2014 /* The reset value of the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field. */
2015 #define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_RESET 0x1
2016 /* Extracts the ALT_CLKMGR_MAINPLL_EN_L3MPCLK field value from a register. */
2017 #define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_GET(value) (((value) & 0x00000002) >> 1)
2018 /* Produces a ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field value suitable for setting the register. */
2019 #define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET(value) (((value) << 1) & 0x00000002)
2020 
2021 /*
2022  * Field : l4_mp_clk Enable - l4mpclk
2023  *
2024  * Enables clock l4_mp_clk output
2025  *
2026  * Field Access Macros:
2027  *
2028  */
2029 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field. */
2030 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_LSB 2
2031 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field. */
2032 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_MSB 2
2033 /* The width in bits of the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field. */
2034 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_WIDTH 1
2035 /* The mask used to set the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field value. */
2036 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK 0x00000004
2037 /* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field value. */
2038 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK 0xfffffffb
2039 /* The reset value of the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field. */
2040 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_RESET 0x1
2041 /* Extracts the ALT_CLKMGR_MAINPLL_EN_L4MPCLK field value from a register. */
2042 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_GET(value) (((value) & 0x00000004) >> 2)
2043 /* Produces a ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field value suitable for setting the register. */
2044 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET(value) (((value) << 2) & 0x00000004)
2045 
2046 /*
2047  * Field : l4_sp_clk Enable - l4spclk
2048  *
2049  * Enables clock l4_sp_clk output
2050  *
2051  * Field Access Macros:
2052  *
2053  */
2054 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field. */
2055 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_LSB 3
2056 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field. */
2057 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_MSB 3
2058 /* The width in bits of the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field. */
2059 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_WIDTH 1
2060 /* The mask used to set the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field value. */
2061 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK 0x00000008
2062 /* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field value. */
2063 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK 0xfffffff7
2064 /* The reset value of the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field. */
2065 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_RESET 0x1
2066 /* Extracts the ALT_CLKMGR_MAINPLL_EN_L4SPCLK field value from a register. */
2067 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_GET(value) (((value) & 0x00000008) >> 3)
2068 /* Produces a ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field value suitable for setting the register. */
2069 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET(value) (((value) << 3) & 0x00000008)
2070 
2071 /*
2072  * Field : dbg_at_clk Enable - dbgatclk
2073  *
2074  * Enables clock dbg_at_clk output
2075  *
2076  * Field Access Macros:
2077  *
2078  */
2079 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field. */
2080 #define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_LSB 4
2081 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field. */
2082 #define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_MSB 4
2083 /* The width in bits of the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field. */
2084 #define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_WIDTH 1
2085 /* The mask used to set the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field value. */
2086 #define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK 0x00000010
2087 /* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field value. */
2088 #define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_CLR_MSK 0xffffffef
2089 /* The reset value of the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field. */
2090 #define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_RESET 0x1
2091 /* Extracts the ALT_CLKMGR_MAINPLL_EN_DBGATCLK field value from a register. */
2092 #define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_GET(value) (((value) & 0x00000010) >> 4)
2093 /* Produces a ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field value suitable for setting the register. */
2094 #define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET(value) (((value) << 4) & 0x00000010)
2095 
2096 /*
2097  * Field : dbg_clk Enable - dbgclk
2098  *
2099  * Enables clock dbg_clk output
2100  *
2101  * Field Access Macros:
2102  *
2103  */
2104 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field. */
2105 #define ALT_CLKMGR_MAINPLL_EN_DBGCLK_LSB 5
2106 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field. */
2107 #define ALT_CLKMGR_MAINPLL_EN_DBGCLK_MSB 5
2108 /* The width in bits of the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field. */
2109 #define ALT_CLKMGR_MAINPLL_EN_DBGCLK_WIDTH 1
2110 /* The mask used to set the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field value. */
2111 #define ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET_MSK 0x00000020
2112 /* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field value. */
2113 #define ALT_CLKMGR_MAINPLL_EN_DBGCLK_CLR_MSK 0xffffffdf
2114 /* The reset value of the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field. */
2115 #define ALT_CLKMGR_MAINPLL_EN_DBGCLK_RESET 0x1
2116 /* Extracts the ALT_CLKMGR_MAINPLL_EN_DBGCLK field value from a register. */
2117 #define ALT_CLKMGR_MAINPLL_EN_DBGCLK_GET(value) (((value) & 0x00000020) >> 5)
2118 /* Produces a ALT_CLKMGR_MAINPLL_EN_DBGCLK register field value suitable for setting the register. */
2119 #define ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET(value) (((value) << 5) & 0x00000020)
2120 
2121 /*
2122  * Field : dbg_trace_clk Enable - dbgtraceclk
2123  *
2124  * Enables clock dbg_trace_clk output
2125  *
2126  * Field Access Macros:
2127  *
2128  */
2129 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field. */
2130 #define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_LSB 6
2131 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field. */
2132 #define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_MSB 6
2133 /* The width in bits of the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field. */
2134 #define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_WIDTH 1
2135 /* The mask used to set the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field value. */
2136 #define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK 0x00000040
2137 /* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field value. */
2138 #define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_CLR_MSK 0xffffffbf
2139 /* The reset value of the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field. */
2140 #define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_RESET 0x1
2141 /* Extracts the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK field value from a register. */
2142 #define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_GET(value) (((value) & 0x00000040) >> 6)
2143 /* Produces a ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field value suitable for setting the register. */
2144 #define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET(value) (((value) << 6) & 0x00000040)
2145 
2146 /*
2147  * Field : dbg_timer_clk Enable - dbgtimerclk
2148  *
2149  * Enables clock dbg_timer_clk output
2150  *
2151  * Field Access Macros:
2152  *
2153  */
2154 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field. */
2155 #define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_LSB 7
2156 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field. */
2157 #define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_MSB 7
2158 /* The width in bits of the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field. */
2159 #define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_WIDTH 1
2160 /* The mask used to set the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field value. */
2161 #define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET_MSK 0x00000080
2162 /* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field value. */
2163 #define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_CLR_MSK 0xffffff7f
2164 /* The reset value of the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field. */
2165 #define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_RESET 0x1
2166 /* Extracts the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK field value from a register. */
2167 #define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_GET(value) (((value) & 0x00000080) >> 7)
2168 /* Produces a ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field value suitable for setting the register. */
2169 #define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET(value) (((value) << 7) & 0x00000080)
2170 
2171 /*
2172  * Field : cfg_clk Enable - cfgclk
2173  *
2174  * Enables clock cfg_clk output
2175  *
2176  * Field Access Macros:
2177  *
2178  */
2179 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field. */
2180 #define ALT_CLKMGR_MAINPLL_EN_CFGCLK_LSB 8
2181 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field. */
2182 #define ALT_CLKMGR_MAINPLL_EN_CFGCLK_MSB 8
2183 /* The width in bits of the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field. */
2184 #define ALT_CLKMGR_MAINPLL_EN_CFGCLK_WIDTH 1
2185 /* The mask used to set the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field value. */
2186 #define ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK 0x00000100
2187 /* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field value. */
2188 #define ALT_CLKMGR_MAINPLL_EN_CFGCLK_CLR_MSK 0xfffffeff
2189 /* The reset value of the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field. */
2190 #define ALT_CLKMGR_MAINPLL_EN_CFGCLK_RESET 0x1
2191 /* Extracts the ALT_CLKMGR_MAINPLL_EN_CFGCLK field value from a register. */
2192 #define ALT_CLKMGR_MAINPLL_EN_CFGCLK_GET(value) (((value) & 0x00000100) >> 8)
2193 /* Produces a ALT_CLKMGR_MAINPLL_EN_CFGCLK register field value suitable for setting the register. */
2194 #define ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET(value) (((value) << 8) & 0x00000100)
2195 
2196 /*
2197  * Field : s2f_user0_clk Enable - s2fuser0clk
2198  *
2199  * Enables clock s2f_user0_clk output.
2200  *
2201  * Qsys and user documenation refer to s2f_user0_clk as h2f_user0_clk.
2202  *
2203  * Field Access Macros:
2204  *
2205  */
2206 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field. */
2207 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_LSB 9
2208 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field. */
2209 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_MSB 9
2210 /* The width in bits of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field. */
2211 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_WIDTH 1
2212 /* The mask used to set the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field value. */
2213 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK 0x00000200
2214 /* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field value. */
2215 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_CLR_MSK 0xfffffdff
2216 /* The reset value of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field. */
2217 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_RESET 0x1
2218 /* Extracts the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK field value from a register. */
2219 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_GET(value) (((value) & 0x00000200) >> 9)
2220 /* Produces a ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field value suitable for setting the register. */
2221 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET(value) (((value) << 9) & 0x00000200)
2222 
2223 #ifndef __ASSEMBLY__
2224 /*
2225  * WARNING: The C register and register group struct declarations are provided for
2226  * convenience and illustrative purposes. They should, however, be used with
2227  * caution as the C language standard provides no guarantees about the alignment or
2228  * atomicity of device memory accesses. The recommended practice for writing
2229  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2230  * alt_write_word() functions.
2231  *
2232  * The struct declaration for register ALT_CLKMGR_MAINPLL_EN.
2233  */
2235 {
2236  uint32_t l4mainclk : 1; /* l4_main_clk Enable */
2237  uint32_t l3mpclk : 1; /* l3_mp_clk Enable */
2238  uint32_t l4mpclk : 1; /* l4_mp_clk Enable */
2239  uint32_t l4spclk : 1; /* l4_sp_clk Enable */
2240  uint32_t dbgatclk : 1; /* dbg_at_clk Enable */
2241  uint32_t dbgclk : 1; /* dbg_clk Enable */
2242  uint32_t dbgtraceclk : 1; /* dbg_trace_clk Enable */
2243  uint32_t dbgtimerclk : 1; /* dbg_timer_clk Enable */
2244  uint32_t cfgclk : 1; /* cfg_clk Enable */
2245  uint32_t s2fuser0clk : 1; /* s2f_user0_clk Enable */
2246  uint32_t : 22; /* *UNDEFINED* */
2247 };
2248 
2249 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_EN. */
2250 typedef volatile struct ALT_CLKMGR_MAINPLL_EN_s ALT_CLKMGR_MAINPLL_EN_t;
2251 #endif /* __ASSEMBLY__ */
2252 
2253 /* The byte offset of the ALT_CLKMGR_MAINPLL_EN register from the beginning of the component. */
2254 #define ALT_CLKMGR_MAINPLL_EN_OFST 0x20
2255 
2256 /*
2257  * Register : Main Divide Register - maindiv
2258  *
2259  * Contains fields that control clock dividers for main clocks derived from the
2260  * Main PLL
2261  *
2262  * Fields are only reset by a cold reset.
2263  *
2264  * Register Layout
2265  *
2266  * Bits | Access | Reset | Description
2267  * :--------|:-------|:------|:--------------------
2268  * [1:0] | RW | 0x0 | L3 MP Clock Divider
2269  * [3:2] | RW | 0x0 | L3 SP Clock Divider
2270  * [6:4] | RW | 0x0 | L4 MP Clock Divider
2271  * [9:7] | RW | 0x0 | L4 SP Clock Divider
2272  * [31:10] | ??? | 0x0 | *UNDEFINED*
2273  *
2274  */
2275 /*
2276  * Field : L3 MP Clock Divider - l3mpclk
2277  *
2278  * The l3_mp_clk is divided down from the l3_main_clk by the value specified in
2279  * this field.
2280  *
2281  * Field Enumeration Values:
2282  *
2283  * Enum | Value | Description
2284  * :------------------------------------------|:------|:------------
2285  * ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV1 | 0x0 | Divide by 1
2286  * ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV2 | 0x1 | Divide by 2
2287  *
2288  * Field Access Macros:
2289  *
2290  */
2291 /*
2292  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK
2293  *
2294  * Divide by 1
2295  */
2296 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV1 0x0
2297 /*
2298  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK
2299  *
2300  * Divide by 2
2301  */
2302 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV2 0x1
2303 
2304 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field. */
2305 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_LSB 0
2306 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field. */
2307 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_MSB 1
2308 /* The width in bits of the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field. */
2309 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_WIDTH 2
2310 /* The mask used to set the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field value. */
2311 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_SET_MSK 0x00000003
2312 /* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field value. */
2313 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_CLR_MSK 0xfffffffc
2314 /* The reset value of the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field. */
2315 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_RESET 0x0
2316 /* Extracts the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK field value from a register. */
2317 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_GET(value) (((value) & 0x00000003) >> 0)
2318 /* Produces a ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field value suitable for setting the register. */
2319 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_SET(value) (((value) << 0) & 0x00000003)
2320 
2321 /*
2322  * Field : L3 SP Clock Divider - l3spclk
2323  *
2324  * The l3_sp_clk is divided down from the l3_mp_clk by the value specified in this
2325  * field.
2326  *
2327  * Field Enumeration Values:
2328  *
2329  * Enum | Value | Description
2330  * :------------------------------------------|:------|:------------
2331  * ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV1 | 0x0 | Divide by 1
2332  * ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2 | 0x1 | Divide by 2
2333  *
2334  * Field Access Macros:
2335  *
2336  */
2337 /*
2338  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK
2339  *
2340  * Divide by 1
2341  */
2342 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV1 0x0
2343 /*
2344  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK
2345  *
2346  * Divide by 2
2347  */
2348 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2 0x1
2349 
2350 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field. */
2351 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_LSB 2
2352 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field. */
2353 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_MSB 3
2354 /* The width in bits of the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field. */
2355 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_WIDTH 2
2356 /* The mask used to set the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field value. */
2357 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_SET_MSK 0x0000000c
2358 /* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field value. */
2359 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_CLR_MSK 0xfffffff3
2360 /* The reset value of the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field. */
2361 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_RESET 0x0
2362 /* Extracts the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK field value from a register. */
2363 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_GET(value) (((value) & 0x0000000c) >> 2)
2364 /* Produces a ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field value suitable for setting the register. */
2365 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_SET(value) (((value) << 2) & 0x0000000c)
2366 
2367 /*
2368  * Field : L4 MP Clock Divider - l4mpclk
2369  *
2370  * The l4_mp_clk is divided down from the periph_base_clk by the value specified in
2371  * this field.
2372  *
2373  * Field Enumeration Values:
2374  *
2375  * Enum | Value | Description
2376  * :--------------------------------------------|:------|:-------------
2377  * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV1 | 0x0 | Divide By 1
2378  * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV2 | 0x1 | Divide By 2
2379  * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV4 | 0x2 | Divide By 4
2380  * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV8 | 0x3 | Divide By 8
2381  * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV16 | 0x4 | Divide By 16
2382  * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_1 | 0x5 | Reserved
2383  * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_2 | 0x6 | Reserved
2384  * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_3 | 0x7 | Reserved
2385  *
2386  * Field Access Macros:
2387  *
2388  */
2389 /*
2390  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK
2391  *
2392  * Divide By 1
2393  */
2394 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV1 0x0
2395 /*
2396  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK
2397  *
2398  * Divide By 2
2399  */
2400 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV2 0x1
2401 /*
2402  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK
2403  *
2404  * Divide By 4
2405  */
2406 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV4 0x2
2407 /*
2408  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK
2409  *
2410  * Divide By 8
2411  */
2412 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV8 0x3
2413 /*
2414  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK
2415  *
2416  * Divide By 16
2417  */
2418 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV16 0x4
2419 /*
2420  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK
2421  *
2422  * Reserved
2423  */
2424 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_1 0x5
2425 /*
2426  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK
2427  *
2428  * Reserved
2429  */
2430 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_2 0x6
2431 /*
2432  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK
2433  *
2434  * Reserved
2435  */
2436 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_3 0x7
2437 
2438 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field. */
2439 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_LSB 4
2440 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field. */
2441 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_MSB 6
2442 /* The width in bits of the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field. */
2443 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_WIDTH 3
2444 /* The mask used to set the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field value. */
2445 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_SET_MSK 0x00000070
2446 /* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field value. */
2447 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_CLR_MSK 0xffffff8f
2448 /* The reset value of the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field. */
2449 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_RESET 0x0
2450 /* Extracts the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK field value from a register. */
2451 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_GET(value) (((value) & 0x00000070) >> 4)
2452 /* Produces a ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field value suitable for setting the register. */
2453 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_SET(value) (((value) << 4) & 0x00000070)
2454 
2455 /*
2456  * Field : L4 SP Clock Divider - l4spclk
2457  *
2458  * The l4_sp_clk is divided down from the periph_base_clk by the value specified in
2459  * this field.
2460  *
2461  * Field Enumeration Values:
2462  *
2463  * Enum | Value | Description
2464  * :--------------------------------------------|:------|:-------------
2465  * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV1 | 0x0 | Divide By 1
2466  * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV2 | 0x1 | Divide By 2
2467  * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV4 | 0x2 | Divide By 4
2468  * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV8 | 0x3 | Divide By 8
2469  * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV16 | 0x4 | Divide By 16
2470  * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_1 | 0x5 | Reserved
2471  * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_2 | 0x6 | Reserved
2472  * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_3 | 0x7 | Reserved
2473  *
2474  * Field Access Macros:
2475  *
2476  */
2477 /*
2478  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK
2479  *
2480  * Divide By 1
2481  */
2482 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV1 0x0
2483 /*
2484  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK
2485  *
2486  * Divide By 2
2487  */
2488 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV2 0x1
2489 /*
2490  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK
2491  *
2492  * Divide By 4
2493  */
2494 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV4 0x2
2495 /*
2496  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK
2497  *
2498  * Divide By 8
2499  */
2500 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV8 0x3
2501 /*
2502  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK
2503  *
2504  * Divide By 16
2505  */
2506 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV16 0x4
2507 /*
2508  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK
2509  *
2510  * Reserved
2511  */
2512 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_1 0x5
2513 /*
2514  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK
2515  *
2516  * Reserved
2517  */
2518 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_2 0x6
2519 /*
2520  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK
2521  *
2522  * Reserved
2523  */
2524 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_3 0x7
2525 
2526 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field. */
2527 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_LSB 7
2528 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field. */
2529 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_MSB 9
2530 /* The width in bits of the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field. */
2531 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_WIDTH 3
2532 /* The mask used to set the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field value. */
2533 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_SET_MSK 0x00000380
2534 /* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field value. */
2535 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_CLR_MSK 0xfffffc7f
2536 /* The reset value of the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field. */
2537 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_RESET 0x0
2538 /* Extracts the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK field value from a register. */
2539 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_GET(value) (((value) & 0x00000380) >> 7)
2540 /* Produces a ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field value suitable for setting the register. */
2541 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_SET(value) (((value) << 7) & 0x00000380)
2542 
2543 #ifndef __ASSEMBLY__
2544 /*
2545  * WARNING: The C register and register group struct declarations are provided for
2546  * convenience and illustrative purposes. They should, however, be used with
2547  * caution as the C language standard provides no guarantees about the alignment or
2548  * atomicity of device memory accesses. The recommended practice for writing
2549  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2550  * alt_write_word() functions.
2551  *
2552  * The struct declaration for register ALT_CLKMGR_MAINPLL_MAINDIV.
2553  */
2555 {
2556  uint32_t l3mpclk : 2; /* L3 MP Clock Divider */
2557  uint32_t l3spclk : 2; /* L3 SP Clock Divider */
2558  uint32_t l4mpclk : 3; /* L4 MP Clock Divider */
2559  uint32_t l4spclk : 3; /* L4 SP Clock Divider */
2560  uint32_t : 22; /* *UNDEFINED* */
2561 };
2562 
2563 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_MAINDIV. */
2564 typedef volatile struct ALT_CLKMGR_MAINPLL_MAINDIV_s ALT_CLKMGR_MAINPLL_MAINDIV_t;
2565 #endif /* __ASSEMBLY__ */
2566 
2567 /* The byte offset of the ALT_CLKMGR_MAINPLL_MAINDIV register from the beginning of the component. */
2568 #define ALT_CLKMGR_MAINPLL_MAINDIV_OFST 0x24
2569 
2570 /*
2571  * Register : Debug Divide Register - dbgdiv
2572  *
2573  * Contains fields that control clock dividers for debug clocks derived from the
2574  * Main PLL
2575  *
2576  * Fields are only reset by a cold reset.
2577  *
2578  * Register Layout
2579  *
2580  * Bits | Access | Reset | Description
2581  * :-------|:-------|:------|:-----------------------
2582  * [1:0] | RW | 0x0 | Debug AT Clock Divider
2583  * [3:2] | RW | 0x1 | Debug Clock Divider
2584  * [31:4] | ??? | 0x0 | *UNDEFINED*
2585  *
2586  */
2587 /*
2588  * Field : Debug AT Clock Divider - dbgatclk
2589  *
2590  * The dbg_at_clk is divided down from the C2 output of the Main PLL by the value
2591  * specified in this field.
2592  *
2593  * Field Enumeration Values:
2594  *
2595  * Enum | Value | Description
2596  * :------------------------------------------|:------|:------------
2597  * ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV1 | 0x0 | Divide by 1
2598  * ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV2 | 0x1 | Divide by 2
2599  * ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV4 | 0x2 | Divide by 4
2600  *
2601  * Field Access Macros:
2602  *
2603  */
2604 /*
2605  * Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK
2606  *
2607  * Divide by 1
2608  */
2609 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV1 0x0
2610 /*
2611  * Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK
2612  *
2613  * Divide by 2
2614  */
2615 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV2 0x1
2616 /*
2617  * Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK
2618  *
2619  * Divide by 4
2620  */
2621 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV4 0x2
2622 
2623 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field. */
2624 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_LSB 0
2625 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field. */
2626 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_MSB 1
2627 /* The width in bits of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field. */
2628 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_WIDTH 2
2629 /* The mask used to set the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field value. */
2630 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_SET_MSK 0x00000003
2631 /* The mask used to clear the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field value. */
2632 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_CLR_MSK 0xfffffffc
2633 /* The reset value of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field. */
2634 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_RESET 0x0
2635 /* Extracts the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK field value from a register. */
2636 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_GET(value) (((value) & 0x00000003) >> 0)
2637 /* Produces a ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field value suitable for setting the register. */
2638 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_SET(value) (((value) << 0) & 0x00000003)
2639 
2640 /*
2641  * Field : Debug Clock Divider - dbgclk
2642  *
2643  * The dbg_clk is divided down from the dbg_at_clk by the value specified in this
2644  * field.
2645  *
2646  * Field Enumeration Values:
2647  *
2648  * Enum | Value | Description
2649  * :----------------------------------------|:------|:------------
2650  * ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV2 | 0x1 | Divide by 2
2651  * ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV4 | 0x2 | Divide by 4
2652  *
2653  * Field Access Macros:
2654  *
2655  */
2656 /*
2657  * Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK
2658  *
2659  * Divide by 2
2660  */
2661 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV2 0x1
2662 /*
2663  * Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK
2664  *
2665  * Divide by 4
2666  */
2667 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV4 0x2
2668 
2669 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field. */
2670 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_LSB 2
2671 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field. */
2672 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_MSB 3
2673 /* The width in bits of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field. */
2674 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_WIDTH 2
2675 /* The mask used to set the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field value. */
2676 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_SET_MSK 0x0000000c
2677 /* The mask used to clear the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field value. */
2678 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_CLR_MSK 0xfffffff3
2679 /* The reset value of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field. */
2680 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_RESET 0x1
2681 /* Extracts the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK field value from a register. */
2682 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_GET(value) (((value) & 0x0000000c) >> 2)
2683 /* Produces a ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field value suitable for setting the register. */
2684 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_SET(value) (((value) << 2) & 0x0000000c)
2685 
2686 #ifndef __ASSEMBLY__
2687 /*
2688  * WARNING: The C register and register group struct declarations are provided for
2689  * convenience and illustrative purposes. They should, however, be used with
2690  * caution as the C language standard provides no guarantees about the alignment or
2691  * atomicity of device memory accesses. The recommended practice for writing
2692  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2693  * alt_write_word() functions.
2694  *
2695  * The struct declaration for register ALT_CLKMGR_MAINPLL_DBGDIV.
2696  */
2698 {
2699  uint32_t dbgatclk : 2; /* Debug AT Clock Divider */
2700  uint32_t dbgclk : 2; /* Debug Clock Divider */
2701  uint32_t : 28; /* *UNDEFINED* */
2702 };
2703 
2704 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_DBGDIV. */
2705 typedef volatile struct ALT_CLKMGR_MAINPLL_DBGDIV_s ALT_CLKMGR_MAINPLL_DBGDIV_t;
2706 #endif /* __ASSEMBLY__ */
2707 
2708 /* The byte offset of the ALT_CLKMGR_MAINPLL_DBGDIV register from the beginning of the component. */
2709 #define ALT_CLKMGR_MAINPLL_DBGDIV_OFST 0x28
2710 
2711 /*
2712  * Register : Debug Trace Divide Register - tracediv
2713  *
2714  * Contains a field that controls the clock divider for the debug trace clock
2715  * derived from the Main PLL
2716  *
2717  * Only reset by a cold reset.
2718  *
2719  * Register Layout
2720  *
2721  * Bits | Access | Reset | Description
2722  * :-------|:-------|:------|:--------------------------
2723  * [2:0] | RW | 0x0 | Debug Trace Clock Divider
2724  * [31:3] | ??? | 0x0 | *UNDEFINED*
2725  *
2726  */
2727 /*
2728  * Field : Debug Trace Clock Divider - traceclk
2729  *
2730  * The dbg_trace_clk is divided down from the C2 output of the Main PLL by the
2731  * value specified in this field.
2732  *
2733  * Field Enumeration Values:
2734  *
2735  * Enum | Value | Description
2736  * :----------------------------------------------|:------|:-------------
2737  * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV1 | 0x0 | Divide By 1
2738  * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV2 | 0x1 | Divide By 2
2739  * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV4 | 0x2 | Divide By 4
2740  * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV8 | 0x3 | Divide By 8
2741  * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV16 | 0x4 | Divide By 16
2742  * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_1 | 0x5 | Reserved
2743  * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_2 | 0x6 | Reserved
2744  * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_3 | 0x7 | Reserved
2745  *
2746  * Field Access Macros:
2747  *
2748  */
2749 /*
2750  * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK
2751  *
2752  * Divide By 1
2753  */
2754 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV1 0x0
2755 /*
2756  * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK
2757  *
2758  * Divide By 2
2759  */
2760 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV2 0x1
2761 /*
2762  * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK
2763  *
2764  * Divide By 4
2765  */
2766 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV4 0x2
2767 /*
2768  * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK
2769  *
2770  * Divide By 8
2771  */
2772 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV8 0x3
2773 /*
2774  * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK
2775  *
2776  * Divide By 16
2777  */
2778 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV16 0x4
2779 /*
2780  * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK
2781  *
2782  * Reserved
2783  */
2784 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_1 0x5
2785 /*
2786  * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK
2787  *
2788  * Reserved
2789  */
2790 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_2 0x6
2791 /*
2792  * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK
2793  *
2794  * Reserved
2795  */
2796 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_3 0x7
2797 
2798 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field. */
2799 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_LSB 0
2800 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field. */
2801 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_MSB 2
2802 /* The width in bits of the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field. */
2803 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_WIDTH 3
2804 /* The mask used to set the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field value. */
2805 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_SET_MSK 0x00000007
2806 /* The mask used to clear the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field value. */
2807 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_CLR_MSK 0xfffffff8
2808 /* The reset value of the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field. */
2809 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_RESET 0x0
2810 /* Extracts the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK field value from a register. */
2811 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_GET(value) (((value) & 0x00000007) >> 0)
2812 /* Produces a ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field value suitable for setting the register. */
2813 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_SET(value) (((value) << 0) & 0x00000007)
2814 
2815 #ifndef __ASSEMBLY__
2816 /*
2817  * WARNING: The C register and register group struct declarations are provided for
2818  * convenience and illustrative purposes. They should, however, be used with
2819  * caution as the C language standard provides no guarantees about the alignment or
2820  * atomicity of device memory accesses. The recommended practice for writing
2821  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2822  * alt_write_word() functions.
2823  *
2824  * The struct declaration for register ALT_CLKMGR_MAINPLL_TRACEDIV.
2825  */
2827 {
2828  uint32_t traceclk : 3; /* Debug Trace Clock Divider */
2829  uint32_t : 29; /* *UNDEFINED* */
2830 };
2831 
2832 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_TRACEDIV. */
2833 typedef volatile struct ALT_CLKMGR_MAINPLL_TRACEDIV_s ALT_CLKMGR_MAINPLL_TRACEDIV_t;
2834 #endif /* __ASSEMBLY__ */
2835 
2836 /* The byte offset of the ALT_CLKMGR_MAINPLL_TRACEDIV register from the beginning of the component. */
2837 #define ALT_CLKMGR_MAINPLL_TRACEDIV_OFST 0x2c
2838 
2839 /*
2840  * Register : L4 MP SP APB Clock Source - l4src
2841  *
2842  * Contains fields that select the clock source for L4 MP and SP APB interconnect
2843  *
2844  * Fields are only reset by a cold reset.
2845  *
2846  * Register Layout
2847  *
2848  * Bits | Access | Reset | Description
2849  * :-------|:-------|:------|:-----------------
2850  * [0] | RW | 0x0 | l4_mp_clk Source
2851  * [1] | RW | 0x0 | l4_sp_clk Source
2852  * [31:2] | ??? | 0x0 | *UNDEFINED*
2853  *
2854  */
2855 /*
2856  * Field : l4_mp_clk Source - l4mp
2857  *
2858  * Selects the source for l4_mp_clk
2859  *
2860  * Field Enumeration Values:
2861  *
2862  * Enum | Value | Description
2863  * :------------------------------------------|:------|:----------------
2864  * ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL | 0x0 | main_clk
2865  * ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_PERIPHPLL | 0x1 | periph_base_clk
2866  *
2867  * Field Access Macros:
2868  *
2869  */
2870 /*
2871  * Enumerated value for register field ALT_CLKMGR_MAINPLL_L4SRC_L4MP
2872  *
2873  * main_clk
2874  */
2875 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL 0x0
2876 /*
2877  * Enumerated value for register field ALT_CLKMGR_MAINPLL_L4SRC_L4MP
2878  *
2879  * periph_base_clk
2880  */
2881 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_PERIPHPLL 0x1
2882 
2883 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field. */
2884 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_LSB 0
2885 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field. */
2886 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_MSB 0
2887 /* The width in bits of the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field. */
2888 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_WIDTH 1
2889 /* The mask used to set the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field value. */
2890 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK 0x00000001
2891 /* The mask used to clear the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field value. */
2892 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_CLR_MSK 0xfffffffe
2893 /* The reset value of the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field. */
2894 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_RESET 0x0
2895 /* Extracts the ALT_CLKMGR_MAINPLL_L4SRC_L4MP field value from a register. */
2896 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_GET(value) (((value) & 0x00000001) >> 0)
2897 /* Produces a ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field value suitable for setting the register. */
2898 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET(value) (((value) << 0) & 0x00000001)
2899 
2900 /*
2901  * Field : l4_sp_clk Source - l4sp
2902  *
2903  * Selects the source for l4_sp_clk
2904  *
2905  * Field Enumeration Values:
2906  *
2907  * Enum | Value | Description
2908  * :------------------------------------------|:------|:----------------
2909  * ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL | 0x0 | main_clk
2910  * ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_PERIPHPLL | 0x1 | periph_base_clk
2911  *
2912  * Field Access Macros:
2913  *
2914  */
2915 /*
2916  * Enumerated value for register field ALT_CLKMGR_MAINPLL_L4SRC_L4SP
2917  *
2918  * main_clk
2919  */
2920 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL 0x0
2921 /*
2922  * Enumerated value for register field ALT_CLKMGR_MAINPLL_L4SRC_L4SP
2923  *
2924  * periph_base_clk
2925  */
2926 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_PERIPHPLL 0x1
2927 
2928 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field. */
2929 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_LSB 1
2930 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field. */
2931 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_MSB 1
2932 /* The width in bits of the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field. */
2933 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_WIDTH 1
2934 /* The mask used to set the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field value. */
2935 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK 0x00000002
2936 /* The mask used to clear the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field value. */
2937 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_CLR_MSK 0xfffffffd
2938 /* The reset value of the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field. */
2939 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_RESET 0x0
2940 /* Extracts the ALT_CLKMGR_MAINPLL_L4SRC_L4SP field value from a register. */
2941 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_GET(value) (((value) & 0x00000002) >> 1)
2942 /* Produces a ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field value suitable for setting the register. */
2943 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET(value) (((value) << 1) & 0x00000002)
2944 
2945 #ifndef __ASSEMBLY__
2946 /*
2947  * WARNING: The C register and register group struct declarations are provided for
2948  * convenience and illustrative purposes. They should, however, be used with
2949  * caution as the C language standard provides no guarantees about the alignment or
2950  * atomicity of device memory accesses. The recommended practice for writing
2951  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2952  * alt_write_word() functions.
2953  *
2954  * The struct declaration for register ALT_CLKMGR_MAINPLL_L4SRC.
2955  */
2957 {
2958  uint32_t l4mp : 1; /* l4_mp_clk Source */
2959  uint32_t l4sp : 1; /* l4_sp_clk Source */
2960  uint32_t : 30; /* *UNDEFINED* */
2961 };
2962 
2963 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_L4SRC. */
2964 typedef volatile struct ALT_CLKMGR_MAINPLL_L4SRC_s ALT_CLKMGR_MAINPLL_L4SRC_t;
2965 #endif /* __ASSEMBLY__ */
2966 
2967 /* The byte offset of the ALT_CLKMGR_MAINPLL_L4SRC register from the beginning of the component. */
2968 #define ALT_CLKMGR_MAINPLL_L4SRC_OFST 0x30
2969 
2970 /*
2971  * Register : Main PLL Output Counter Reset Ack Status Register - stat
2972  *
2973  * Contains Output Clock Counter Reset acknowledge status.
2974  *
2975  * Register Layout
2976  *
2977  * Bits | Access | Reset | Description
2978  * :-------|:-------|:------|:---------------------------------
2979  * [5:0] | R | 0x0 | Output Counter Reset Acknowledge
2980  * [31:6] | ??? | 0x0 | *UNDEFINED*
2981  *
2982  */
2983 /*
2984  * Field : Output Counter Reset Acknowledge - outresetack
2985  *
2986  * These read only bits per PLL output indicate that the PLL has received the
2987  * Output Reset Counter request and has gracefully stopped the respective PLL
2988  * output clock.
2989  *
2990  * For software to change the PLL output counter without producing glitches on the
2991  * respective clock, SW must set the VCO register respective Output Counter Reset
2992  * bit. Software then polls the respective Output Counter Reset Acknowledge bit in
2993  * the Output Counter Reset Ack Status Register. Software then writes the
2994  * appropriate counter register, and then clears the respective VCO register Output
2995  * Counter Reset bit.
2996  *
2997  * The reset value of this bit is applied on a cold reset; warm reset has no affect
2998  * on this bit.
2999  *
3000  * Field Enumeration Values:
3001  *
3002  * Enum | Value | Description
3003  * :--------------------------------------------|:------|:-------------------------------------
3004  * ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_E_IDLE | 0x0 | Idle
3005  * ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_E_ACK_RXD | 0x1 | Output Counter Acknowledge received.
3006  *
3007  * Field Access Macros:
3008  *
3009  */
3010 /*
3011  * Enumerated value for register field ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK
3012  *
3013  * Idle
3014  */
3015 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_E_IDLE 0x0
3016 /*
3017  * Enumerated value for register field ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK
3018  *
3019  * Output Counter Acknowledge received.
3020  */
3021 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_E_ACK_RXD 0x1
3022 
3023 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field. */
3024 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_LSB 0
3025 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field. */
3026 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_MSB 5
3027 /* The width in bits of the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field. */
3028 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_WIDTH 6
3029 /* The mask used to set the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field value. */
3030 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_SET_MSK 0x0000003f
3031 /* The mask used to clear the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field value. */
3032 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_CLR_MSK 0xffffffc0
3033 /* The reset value of the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field. */
3034 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_RESET 0x0
3035 /* Extracts the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK field value from a register. */
3036 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_GET(value) (((value) & 0x0000003f) >> 0)
3037 /* Produces a ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field value suitable for setting the register. */
3038 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_SET(value) (((value) << 0) & 0x0000003f)
3039 
3040 #ifndef __ASSEMBLY__
3041 /*
3042  * WARNING: The C register and register group struct declarations are provided for
3043  * convenience and illustrative purposes. They should, however, be used with
3044  * caution as the C language standard provides no guarantees about the alignment or
3045  * atomicity of device memory accesses. The recommended practice for writing
3046  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3047  * alt_write_word() functions.
3048  *
3049  * The struct declaration for register ALT_CLKMGR_MAINPLL_STAT.
3050  */
3052 {
3053  const uint32_t outresetack : 6; /* Output Counter Reset Acknowledge */
3054  uint32_t : 26; /* *UNDEFINED* */
3055 };
3056 
3057 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_STAT. */
3058 typedef volatile struct ALT_CLKMGR_MAINPLL_STAT_s ALT_CLKMGR_MAINPLL_STAT_t;
3059 #endif /* __ASSEMBLY__ */
3060 
3061 /* The byte offset of the ALT_CLKMGR_MAINPLL_STAT register from the beginning of the component. */
3062 #define ALT_CLKMGR_MAINPLL_STAT_OFST 0x34
3063 
3064 #ifndef __ASSEMBLY__
3065 /*
3066  * WARNING: The C register and register group struct declarations are provided for
3067  * convenience and illustrative purposes. They should, however, be used with
3068  * caution as the C language standard provides no guarantees about the alignment or
3069  * atomicity of device memory accesses. The recommended practice for writing
3070  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3071  * alt_write_word() functions.
3072  *
3073  * The struct declaration for register group ALT_CLKMGR_MAINPLL.
3074  */
3076 {
3077  volatile ALT_CLKMGR_MAINPLL_VCO_t vco; /* ALT_CLKMGR_MAINPLL_VCO */
3078  volatile ALT_CLKMGR_MAINPLL_MISC_t misc; /* ALT_CLKMGR_MAINPLL_MISC */
3079  volatile ALT_CLKMGR_MAINPLL_MPUCLK_t mpuclk; /* ALT_CLKMGR_MAINPLL_MPUCLK */
3080  volatile ALT_CLKMGR_MAINPLL_MAINCLK_t mainclk; /* ALT_CLKMGR_MAINPLL_MAINCLK */
3081  volatile ALT_CLKMGR_MAINPLL_DBGATCLK_t dbgatclk; /* ALT_CLKMGR_MAINPLL_DBGATCLK */
3082  volatile ALT_CLKMGR_MAINPLL_MAINQSPICLK_t mainqspiclk; /* ALT_CLKMGR_MAINPLL_MAINQSPICLK */
3083  volatile ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_t mainnandsdmmcclk; /* ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK */
3084  volatile ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_t cfgs2fuser0clk; /* ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK */
3085  volatile ALT_CLKMGR_MAINPLL_EN_t en; /* ALT_CLKMGR_MAINPLL_EN */
3086  volatile ALT_CLKMGR_MAINPLL_MAINDIV_t maindiv; /* ALT_CLKMGR_MAINPLL_MAINDIV */
3087  volatile ALT_CLKMGR_MAINPLL_DBGDIV_t dbgdiv; /* ALT_CLKMGR_MAINPLL_DBGDIV */
3088  volatile ALT_CLKMGR_MAINPLL_TRACEDIV_t tracediv; /* ALT_CLKMGR_MAINPLL_TRACEDIV */
3089  volatile ALT_CLKMGR_MAINPLL_L4SRC_t l4src; /* ALT_CLKMGR_MAINPLL_L4SRC */
3090  volatile ALT_CLKMGR_MAINPLL_STAT_t stat; /* ALT_CLKMGR_MAINPLL_STAT */
3091  volatile uint32_t _pad_0x38_0x40[2]; /* *UNDEFINED* */
3092 };
3093 
3094 /* The typedef declaration for register group ALT_CLKMGR_MAINPLL. */
3095 typedef volatile struct ALT_CLKMGR_MAINPLL_s ALT_CLKMGR_MAINPLL_t;
3096 /* The struct declaration for the raw register contents of register group ALT_CLKMGR_MAINPLL. */
3098 {
3099  volatile uint32_t vco; /* ALT_CLKMGR_MAINPLL_VCO */
3100  volatile uint32_t misc; /* ALT_CLKMGR_MAINPLL_MISC */
3101  volatile uint32_t mpuclk; /* ALT_CLKMGR_MAINPLL_MPUCLK */
3102  volatile uint32_t mainclk; /* ALT_CLKMGR_MAINPLL_MAINCLK */
3103  volatile uint32_t dbgatclk; /* ALT_CLKMGR_MAINPLL_DBGATCLK */
3104  volatile uint32_t mainqspiclk; /* ALT_CLKMGR_MAINPLL_MAINQSPICLK */
3105  volatile uint32_t mainnandsdmmcclk; /* ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK */
3106  volatile uint32_t cfgs2fuser0clk; /* ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK */
3107  volatile uint32_t en; /* ALT_CLKMGR_MAINPLL_EN */
3108  volatile uint32_t maindiv; /* ALT_CLKMGR_MAINPLL_MAINDIV */
3109  volatile uint32_t dbgdiv; /* ALT_CLKMGR_MAINPLL_DBGDIV */
3110  volatile uint32_t tracediv; /* ALT_CLKMGR_MAINPLL_TRACEDIV */
3111  volatile uint32_t l4src; /* ALT_CLKMGR_MAINPLL_L4SRC */
3112  volatile uint32_t stat; /* ALT_CLKMGR_MAINPLL_STAT */
3113  volatile uint32_t _pad_0x38_0x40[2]; /* *UNDEFINED* */
3114 };
3115 
3116 /* The typedef declaration for the raw register contents of register group ALT_CLKMGR_MAINPLL. */
3117 typedef volatile struct ALT_CLKMGR_MAINPLL_raw_s ALT_CLKMGR_MAINPLL_raw_t;
3118 #endif /* __ASSEMBLY__ */
3119 
3120 
3121 /*
3122  * Register Group : Peripheral PLL Group - ALT_CLKMGR_PERPLL
3123  * Peripheral PLL Group
3124  *
3125  * Contains registers with settings for the Peripheral PLL.
3126  *
3127  */
3128 /*
3129  * Register : Peripheral PLL VCO Control Register - vco
3130  *
3131  * Contains settings that control the Peripheral PLL VCO. The VCO output frequency
3132  * is the input frequency multiplied by the numerator (M+1) and divided by the
3133  * denominator (N+1).
3134  *
3135  * Fields are only reset by a cold reset.
3136  *
3137  * Register Layout
3138  *
3139  * Bits | Access | Reset | Description
3140  * :--------|:-------|:------|:--------------------------------
3141  * [0] | RW | 0x1 | BG PWRDN
3142  * [1] | RW | 0x0 | Enable
3143  * [2] | RW | 0x1 | Power down
3144  * [15:3] | RW | 0x1 | Numerator (M)
3145  * [21:16] | RW | 0x1 | Denominator (N)
3146  * [23:22] | RW | 0x0 | Clock Source
3147  * [24] | RW | 0x0 | All Output Counter Reset
3148  * [30:25] | RW | 0x0 | Output Counter Reset
3149  * [31] | RW | 0x1 | External Regulator Input Select
3150  *
3151  */
3152 /*
3153  * Field : BG PWRDN - bgpwrdn
3154  *
3155  * If '1', powers down bandgap. If '0', bandgap is not power down.
3156  *
3157  * Field Access Macros:
3158  *
3159  */
3160 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field. */
3161 #define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_LSB 0
3162 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field. */
3163 #define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_MSB 0
3164 /* The width in bits of the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field. */
3165 #define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_WIDTH 1
3166 /* The mask used to set the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field value. */
3167 #define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_SET_MSK 0x00000001
3168 /* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field value. */
3169 #define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_CLR_MSK 0xfffffffe
3170 /* The reset value of the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field. */
3171 #define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_RESET 0x1
3172 /* Extracts the ALT_CLKMGR_PERPLL_VCO_BGPWRDN field value from a register. */
3173 #define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0)
3174 /* Produces a ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field value suitable for setting the register. */
3175 #define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_SET(value) (((value) << 0) & 0x00000001)
3176 
3177 /*
3178  * Field : Enable - en
3179  *
3180  * If '1', VCO is enabled. If '0', VCO is in reset.
3181  *
3182  * Field Access Macros:
3183  *
3184  */
3185 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_EN register field. */
3186 #define ALT_CLKMGR_PERPLL_VCO_EN_LSB 1
3187 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_EN register field. */
3188 #define ALT_CLKMGR_PERPLL_VCO_EN_MSB 1
3189 /* The width in bits of the ALT_CLKMGR_PERPLL_VCO_EN register field. */
3190 #define ALT_CLKMGR_PERPLL_VCO_EN_WIDTH 1
3191 /* The mask used to set the ALT_CLKMGR_PERPLL_VCO_EN register field value. */
3192 #define ALT_CLKMGR_PERPLL_VCO_EN_SET_MSK 0x00000002
3193 /* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_EN register field value. */
3194 #define ALT_CLKMGR_PERPLL_VCO_EN_CLR_MSK 0xfffffffd
3195 /* The reset value of the ALT_CLKMGR_PERPLL_VCO_EN register field. */
3196 #define ALT_CLKMGR_PERPLL_VCO_EN_RESET 0x0
3197 /* Extracts the ALT_CLKMGR_PERPLL_VCO_EN field value from a register. */
3198 #define ALT_CLKMGR_PERPLL_VCO_EN_GET(value) (((value) & 0x00000002) >> 1)
3199 /* Produces a ALT_CLKMGR_PERPLL_VCO_EN register field value suitable for setting the register. */
3200 #define ALT_CLKMGR_PERPLL_VCO_EN_SET(value) (((value) << 1) & 0x00000002)
3201 
3202 /*
3203  * Field : Power down - pwrdn
3204  *
3205  * If '1', power down analog circuitry. If '0', analog circuitry not powered down.
3206  *
3207  * Field Access Macros:
3208  *
3209  */
3210 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_PWRDN register field. */
3211 #define ALT_CLKMGR_PERPLL_VCO_PWRDN_LSB 2
3212 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_PWRDN register field. */
3213 #define ALT_CLKMGR_PERPLL_VCO_PWRDN_MSB 2
3214 /* The width in bits of the ALT_CLKMGR_PERPLL_VCO_PWRDN register field. */
3215 #define ALT_CLKMGR_PERPLL_VCO_PWRDN_WIDTH 1
3216 /* The mask used to set the ALT_CLKMGR_PERPLL_VCO_PWRDN register field value. */
3217 #define ALT_CLKMGR_PERPLL_VCO_PWRDN_SET_MSK 0x00000004
3218 /* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_PWRDN register field value. */
3219 #define ALT_CLKMGR_PERPLL_VCO_PWRDN_CLR_MSK 0xfffffffb
3220 /* The reset value of the ALT_CLKMGR_PERPLL_VCO_PWRDN register field. */
3221 #define ALT_CLKMGR_PERPLL_VCO_PWRDN_RESET 0x1
3222 /* Extracts the ALT_CLKMGR_PERPLL_VCO_PWRDN field value from a register. */
3223 #define ALT_CLKMGR_PERPLL_VCO_PWRDN_GET(value) (((value) & 0x00000004) >> 2)
3224 /* Produces a ALT_CLKMGR_PERPLL_VCO_PWRDN register field value suitable for setting the register. */
3225 #define ALT_CLKMGR_PERPLL_VCO_PWRDN_SET(value) (((value) << 2) & 0x00000004)
3226 
3227 /*
3228  * Field : Numerator (M) - numer
3229  *
3230  * Numerator in VCO output frequency equation. For incremental frequency change, if
3231  * the new value lead to less than 20% of the frequency change, this value can be
3232  * changed without resetting the PLL. The Numerator and Denominator can not be
3233  * changed at the same time for incremental frequency changed.
3234  *
3235  * Field Access Macros:
3236  *
3237  */
3238 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_NUMER register field. */
3239 #define ALT_CLKMGR_PERPLL_VCO_NUMER_LSB 3
3240 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_NUMER register field. */
3241 #define ALT_CLKMGR_PERPLL_VCO_NUMER_MSB 15
3242 /* The width in bits of the ALT_CLKMGR_PERPLL_VCO_NUMER register field. */
3243 #define ALT_CLKMGR_PERPLL_VCO_NUMER_WIDTH 13
3244 /* The mask used to set the ALT_CLKMGR_PERPLL_VCO_NUMER register field value. */
3245 #define ALT_CLKMGR_PERPLL_VCO_NUMER_SET_MSK 0x0000fff8
3246 /* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_NUMER register field value. */
3247 #define ALT_CLKMGR_PERPLL_VCO_NUMER_CLR_MSK 0xffff0007
3248 /* The reset value of the ALT_CLKMGR_PERPLL_VCO_NUMER register field. */
3249 #define ALT_CLKMGR_PERPLL_VCO_NUMER_RESET 0x1
3250 /* Extracts the ALT_CLKMGR_PERPLL_VCO_NUMER field value from a register. */
3251 #define ALT_CLKMGR_PERPLL_VCO_NUMER_GET(value) (((value) & 0x0000fff8) >> 3)
3252 /* Produces a ALT_CLKMGR_PERPLL_VCO_NUMER register field value suitable for setting the register. */
3253 #define ALT_CLKMGR_PERPLL_VCO_NUMER_SET(value) (((value) << 3) & 0x0000fff8)
3254 
3255 /*
3256  * Field : Denominator (N) - denom
3257  *
3258  * Denominator in VCO output frequency equation. For incremental frequency change,
3259  * if the new value lead to less than 20% of the frequency change, this value can
3260  * be changed without resetting the PLL. The Numerator and Denominator can not be
3261  * changed at the same time for incremental frequency changed.
3262  *
3263  * Field Access Macros:
3264  *
3265  */
3266 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_DENOM register field. */
3267 #define ALT_CLKMGR_PERPLL_VCO_DENOM_LSB 16
3268 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_DENOM register field. */
3269 #define ALT_CLKMGR_PERPLL_VCO_DENOM_MSB 21
3270 /* The width in bits of the ALT_CLKMGR_PERPLL_VCO_DENOM register field. */
3271 #define ALT_CLKMGR_PERPLL_VCO_DENOM_WIDTH 6
3272 /* The mask used to set the ALT_CLKMGR_PERPLL_VCO_DENOM register field value. */
3273 #define ALT_CLKMGR_PERPLL_VCO_DENOM_SET_MSK 0x003f0000
3274 /* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_DENOM register field value. */
3275 #define ALT_CLKMGR_PERPLL_VCO_DENOM_CLR_MSK 0xffc0ffff
3276 /* The reset value of the ALT_CLKMGR_PERPLL_VCO_DENOM register field. */
3277 #define ALT_CLKMGR_PERPLL_VCO_DENOM_RESET 0x1
3278 /* Extracts the ALT_CLKMGR_PERPLL_VCO_DENOM field value from a register. */
3279 #define ALT_CLKMGR_PERPLL_VCO_DENOM_GET(value) (((value) & 0x003f0000) >> 16)
3280 /* Produces a ALT_CLKMGR_PERPLL_VCO_DENOM register field value suitable for setting the register. */
3281 #define ALT_CLKMGR_PERPLL_VCO_DENOM_SET(value) (((value) << 16) & 0x003f0000)
3282 
3283 /*
3284  * Field : Clock Source - psrc
3285  *
3286  * Controls the VCO input clock source.
3287  *
3288  * Qsys and user documenation refer to f2s_periph_ref_clk as f2h_periph_ref_clk.
3289  *
3290  * Field Enumeration Values:
3291  *
3292  * Enum | Value | Description
3293  * :--------------------------------------------|:------|:-------------------
3294  * ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1 | 0x0 | eosc1_clk
3295  * ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2 | 0x1 | eosc2_clk
3296  * ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF | 0x2 | f2s_periph_ref_clk
3297  *
3298  * Field Access Macros:
3299  *
3300  */
3301 /*
3302  * Enumerated value for register field ALT_CLKMGR_PERPLL_VCO_PSRC
3303  *
3304  * eosc1_clk
3305  */
3306 #define ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1 0x0
3307 /*
3308  * Enumerated value for register field ALT_CLKMGR_PERPLL_VCO_PSRC
3309  *
3310  * eosc2_clk
3311  */
3312 #define ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2 0x1
3313 /*
3314  * Enumerated value for register field ALT_CLKMGR_PERPLL_VCO_PSRC
3315  *
3316  * f2s_periph_ref_clk
3317  */
3318 #define ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF 0x2
3319 
3320 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_PSRC register field. */
3321 #define ALT_CLKMGR_PERPLL_VCO_PSRC_LSB 22
3322 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_PSRC register field. */
3323 #define ALT_CLKMGR_PERPLL_VCO_PSRC_MSB 23
3324 /* The width in bits of the ALT_CLKMGR_PERPLL_VCO_PSRC register field. */
3325 #define ALT_CLKMGR_PERPLL_VCO_PSRC_WIDTH 2
3326 /* The mask used to set the ALT_CLKMGR_PERPLL_VCO_PSRC register field value. */
3327 #define ALT_CLKMGR_PERPLL_VCO_PSRC_SET_MSK 0x00c00000
3328 /* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_PSRC register field value. */
3329 #define ALT_CLKMGR_PERPLL_VCO_PSRC_CLR_MSK 0xff3fffff
3330 /* The reset value of the ALT_CLKMGR_PERPLL_VCO_PSRC register field. */
3331 #define ALT_CLKMGR_PERPLL_VCO_PSRC_RESET 0x0
3332 /* Extracts the ALT_CLKMGR_PERPLL_VCO_PSRC field value from a register. */
3333 #define ALT_CLKMGR_PERPLL_VCO_PSRC_GET(value) (((value) & 0x00c00000) >> 22)
3334 /* Produces a ALT_CLKMGR_PERPLL_VCO_PSRC register field value suitable for setting the register. */
3335 #define ALT_CLKMGR_PERPLL_VCO_PSRC_SET(value) (((value) << 22) & 0x00c00000)
3336 
3337 /*
3338  * Field : All Output Counter Reset - outresetall
3339  *
3340  * Before releasing Bypass, All Output Counter Reset must be set and cleared by
3341  * software for correct clock operation.
3342  *
3343  * If '1', Reset phase multiplexer and all output counter state. So that after the
3344  * assertion all the clocks output are start from rising edge align.
3345  *
3346  * If '0', phase multiplexer and output counter state not reset and no change to
3347  * the phase of the clock outputs.
3348  *
3349  * Field Access Macros:
3350  *
3351  */
3352 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field. */
3353 #define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_LSB 24
3354 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field. */
3355 #define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_MSB 24
3356 /* The width in bits of the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field. */
3357 #define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_WIDTH 1
3358 /* The mask used to set the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field value. */
3359 #define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_SET_MSK 0x01000000
3360 /* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field value. */
3361 #define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_CLR_MSK 0xfeffffff
3362 /* The reset value of the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field. */
3363 #define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_RESET 0x0
3364 /* Extracts the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL field value from a register. */
3365 #define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_GET(value) (((value) & 0x01000000) >> 24)
3366 /* Produces a ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field value suitable for setting the register. */
3367 #define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_SET(value) (((value) << 24) & 0x01000000)
3368 
3369 /*
3370  * Field : Output Counter Reset - outreset
3371  *
3372  * Resets the individual PLL output counter.
3373  *
3374  * For software to change the PLL output counter without producing glitches on the
3375  * respective clock, SW must set the VCO register respective Output Counter Reset
3376  * bit. Software then polls the respective Output Counter Reset Acknowledge bit in
3377  * the Output Counter Reset Ack Status Register. Software then writes the
3378  * appropriate counter register, and then clears the respective VCO register Output
3379  * Counter Reset bit.
3380  *
3381  * LSB 'outreset[0]' corresponds to PLL output clock C0, etc.
3382  *
3383  * If set to '1', reset output divider, no clock output from counter.
3384  *
3385  * If set to '0', counter is not reset.
3386  *
3387  * The reset value of this bit is applied on a cold reset; warm reset has no affect
3388  * on this bit.
3389  *
3390  * Field Access Macros:
3391  *
3392  */
3393 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_OUTRST register field. */
3394 #define ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB 25
3395 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_OUTRST register field. */
3396 #define ALT_CLKMGR_PERPLL_VCO_OUTRST_MSB 30
3397 /* The width in bits of the ALT_CLKMGR_PERPLL_VCO_OUTRST register field. */
3398 #define ALT_CLKMGR_PERPLL_VCO_OUTRST_WIDTH 6
3399 /* The mask used to set the ALT_CLKMGR_PERPLL_VCO_OUTRST register field value. */
3400 #define ALT_CLKMGR_PERPLL_VCO_OUTRST_SET_MSK 0x7e000000
3401 /* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_OUTRST register field value. */
3402 #define ALT_CLKMGR_PERPLL_VCO_OUTRST_CLR_MSK 0x81ffffff
3403 /* The reset value of the ALT_CLKMGR_PERPLL_VCO_OUTRST register field. */
3404 #define ALT_CLKMGR_PERPLL_VCO_OUTRST_RESET 0x0
3405 /* Extracts the ALT_CLKMGR_PERPLL_VCO_OUTRST field value from a register. */
3406 #define ALT_CLKMGR_PERPLL_VCO_OUTRST_GET(value) (((value) & 0x7e000000) >> 25)
3407 /* Produces a ALT_CLKMGR_PERPLL_VCO_OUTRST register field value suitable for setting the register. */
3408 #define ALT_CLKMGR_PERPLL_VCO_OUTRST_SET(value) (((value) << 25) & 0x7e000000)
3409 
3410 /*
3411  * Field : External Regulator Input Select - regextsel
3412  *
3413  * If set to '1', the external regulator is selected for the PLL.
3414  *
3415  * If set to '0', the internal regulator is slected.
3416  *
3417  * It is strongly recommended to select the external regulator while the PLL is not
3418  * enabled (in reset), and then disable the external regulater once the PLL
3419  * becomes enabled. Software should simulateously update the 'Enable' bit and the
3420  * 'External Regulator Input Select' in the same write access to the VCO register.
3421  * When the 'Enable' bit is clear, the 'External Regulator Input Select' should be
3422  * set, and vice versa.
3423  *
3424  * The reset value of this bit is applied on a cold reset; warm reset has no affect
3425  * on this bit.
3426  *
3427  * Field Access Macros:
3428  *
3429  */
3430 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field. */
3431 #define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_LSB 31
3432 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field. */
3433 #define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_MSB 31
3434 /* The width in bits of the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field. */
3435 #define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_WIDTH 1
3436 /* The mask used to set the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field value. */
3437 #define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_SET_MSK 0x80000000
3438 /* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field value. */
3439 #define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_CLR_MSK 0x7fffffff
3440 /* The reset value of the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field. */
3441 #define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_RESET 0x1
3442 /* Extracts the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL field value from a register. */
3443 #define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_GET(value) (((value) & 0x80000000) >> 31)
3444 /* Produces a ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field value suitable for setting the register. */
3445 #define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_SET(value) (((value) << 31) & 0x80000000)
3446 
3447 #ifndef __ASSEMBLY__
3448 /*
3449  * WARNING: The C register and register group struct declarations are provided for
3450  * convenience and illustrative purposes. They should, however, be used with
3451  * caution as the C language standard provides no guarantees about the alignment or
3452  * atomicity of device memory accesses. The recommended practice for writing
3453  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3454  * alt_write_word() functions.
3455  *
3456  * The struct declaration for register ALT_CLKMGR_PERPLL_VCO.
3457  */
3459 {
3460  uint32_t bgpwrdn : 1; /* BG PWRDN */
3461  uint32_t en : 1; /* Enable */
3462  uint32_t pwrdn : 1; /* Power down */
3463  uint32_t numer : 13; /* Numerator (M) */
3464  uint32_t denom : 6; /* Denominator (N) */
3465  uint32_t psrc : 2; /* Clock Source */
3466  uint32_t outresetall : 1; /* All Output Counter Reset */
3467  uint32_t outreset : 6; /* Output Counter Reset */
3468  uint32_t regextsel : 1; /* External Regulator Input Select */
3469 };
3470 
3471 /* The typedef declaration for register ALT_CLKMGR_PERPLL_VCO. */
3472 typedef volatile struct ALT_CLKMGR_PERPLL_VCO_s ALT_CLKMGR_PERPLL_VCO_t;
3473 #endif /* __ASSEMBLY__ */
3474 
3475 /* The byte offset of the ALT_CLKMGR_PERPLL_VCO register from the beginning of the component. */
3476 #define ALT_CLKMGR_PERPLL_VCO_OFST 0x0
3477 
3478 /*
3479  * Register : Peripheral PLL VCO Advanced Control Register - misc
3480  *
3481  * Contains VCO control signals and other PLL control signals need to be
3482  * controllable through register.
3483  *
3484  * Fields are only reset by a cold reset.
3485  *
3486  * Register Layout
3487  *
3488  * Bits | Access | Reset | Description
3489  * :--------|:-------|:------|:------------------------------
3490  * [0] | RW | 0x0 | Loop Bandwidth Adjust Enabled
3491  * [12:1] | RW | 0x1 | Loop Bandwidth Adjust
3492  * [13] | RW | 0x0 | Fast Locking Enable
3493  * [14] | RW | 0x1 | Saturation Enable
3494  * [31:15] | ??? | 0x0 | *UNDEFINED*
3495  *
3496  */
3497 /*
3498  * Field : Loop Bandwidth Adjust Enabled - bwadjen
3499  *
3500  * If set to 1, the Loop Bandwidth Adjust value comes from the Loop Bandwidth
3501  * Adjust field.
3502  *
3503  * If set to 0, the Loop Bandwidth Adjust value equals the M field divided by 2
3504  * value of the VCO Control Register. The M divided by 2 is the upper 12 bits
3505  * (12:1) of the M field in the VCO register.
3506  *
3507  * Field Access Macros:
3508  *
3509  */
3510 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field. */
3511 #define ALT_CLKMGR_PERPLL_MISC_BWADJEN_LSB 0
3512 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field. */
3513 #define ALT_CLKMGR_PERPLL_MISC_BWADJEN_MSB 0
3514 /* The width in bits of the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field. */
3515 #define ALT_CLKMGR_PERPLL_MISC_BWADJEN_WIDTH 1
3516 /* The mask used to set the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field value. */
3517 #define ALT_CLKMGR_PERPLL_MISC_BWADJEN_SET_MSK 0x00000001
3518 /* The mask used to clear the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field value. */
3519 #define ALT_CLKMGR_PERPLL_MISC_BWADJEN_CLR_MSK 0xfffffffe
3520 /* The reset value of the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field. */
3521 #define ALT_CLKMGR_PERPLL_MISC_BWADJEN_RESET 0x0
3522 /* Extracts the ALT_CLKMGR_PERPLL_MISC_BWADJEN field value from a register. */
3523 #define ALT_CLKMGR_PERPLL_MISC_BWADJEN_GET(value) (((value) & 0x00000001) >> 0)
3524 /* Produces a ALT_CLKMGR_PERPLL_MISC_BWADJEN register field value suitable for setting the register. */
3525 #define ALT_CLKMGR_PERPLL_MISC_BWADJEN_SET(value) (((value) << 0) & 0x00000001)
3526 
3527 /*
3528  * Field : Loop Bandwidth Adjust - bwadj
3529  *
3530  * Provides Loop Bandwidth Adjust value.
3531  *
3532  * Field Access Macros:
3533  *
3534  */
3535 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_MISC_BWADJ register field. */
3536 #define ALT_CLKMGR_PERPLL_MISC_BWADJ_LSB 1
3537 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_MISC_BWADJ register field. */
3538 #define ALT_CLKMGR_PERPLL_MISC_BWADJ_MSB 12
3539 /* The width in bits of the ALT_CLKMGR_PERPLL_MISC_BWADJ register field. */
3540 #define ALT_CLKMGR_PERPLL_MISC_BWADJ_WIDTH 12
3541 /* The mask used to set the ALT_CLKMGR_PERPLL_MISC_BWADJ register field value. */
3542 #define ALT_CLKMGR_PERPLL_MISC_BWADJ_SET_MSK 0x00001ffe
3543 /* The mask used to clear the ALT_CLKMGR_PERPLL_MISC_BWADJ register field value. */
3544 #define ALT_CLKMGR_PERPLL_MISC_BWADJ_CLR_MSK 0xffffe001
3545 /* The reset value of the ALT_CLKMGR_PERPLL_MISC_BWADJ register field. */
3546 #define ALT_CLKMGR_PERPLL_MISC_BWADJ_RESET 0x1
3547 /* Extracts the ALT_CLKMGR_PERPLL_MISC_BWADJ field value from a register. */
3548 #define ALT_CLKMGR_PERPLL_MISC_BWADJ_GET(value) (((value) & 0x00001ffe) >> 1)
3549 /* Produces a ALT_CLKMGR_PERPLL_MISC_BWADJ register field value suitable for setting the register. */
3550 #define ALT_CLKMGR_PERPLL_MISC_BWADJ_SET(value) (((value) << 1) & 0x00001ffe)
3551 
3552 /*
3553  * Field : Fast Locking Enable - fasten
3554  *
3555  * Enables fast locking circuit.
3556  *
3557  * Field Access Macros:
3558  *
3559  */
3560 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_MISC_FASTEN register field. */
3561 #define ALT_CLKMGR_PERPLL_MISC_FASTEN_LSB 13
3562 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_MISC_FASTEN register field. */
3563 #define ALT_CLKMGR_PERPLL_MISC_FASTEN_MSB 13
3564 /* The width in bits of the ALT_CLKMGR_PERPLL_MISC_FASTEN register field. */
3565 #define ALT_CLKMGR_PERPLL_MISC_FASTEN_WIDTH 1
3566 /* The mask used to set the ALT_CLKMGR_PERPLL_MISC_FASTEN register field value. */
3567 #define ALT_CLKMGR_PERPLL_MISC_FASTEN_SET_MSK 0x00002000
3568 /* The mask used to clear the ALT_CLKMGR_PERPLL_MISC_FASTEN register field value. */
3569 #define ALT_CLKMGR_PERPLL_MISC_FASTEN_CLR_MSK 0xffffdfff
3570 /* The reset value of the ALT_CLKMGR_PERPLL_MISC_FASTEN register field. */
3571 #define ALT_CLKMGR_PERPLL_MISC_FASTEN_RESET 0x0
3572 /* Extracts the ALT_CLKMGR_PERPLL_MISC_FASTEN field value from a register. */
3573 #define ALT_CLKMGR_PERPLL_MISC_FASTEN_GET(value) (((value) & 0x00002000) >> 13)
3574 /* Produces a ALT_CLKMGR_PERPLL_MISC_FASTEN register field value suitable for setting the register. */
3575 #define ALT_CLKMGR_PERPLL_MISC_FASTEN_SET(value) (((value) << 13) & 0x00002000)
3576 
3577 /*
3578  * Field : Saturation Enable - saten
3579  *
3580  * Enables saturation behavior.
3581  *
3582  * Field Access Macros:
3583  *
3584  */
3585 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_MISC_SATEN register field. */
3586 #define ALT_CLKMGR_PERPLL_MISC_SATEN_LSB 14
3587 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_MISC_SATEN register field. */
3588 #define ALT_CLKMGR_PERPLL_MISC_SATEN_MSB 14
3589 /* The width in bits of the ALT_CLKMGR_PERPLL_MISC_SATEN register field. */
3590 #define ALT_CLKMGR_PERPLL_MISC_SATEN_WIDTH 1
3591 /* The mask used to set the ALT_CLKMGR_PERPLL_MISC_SATEN register field value. */
3592 #define ALT_CLKMGR_PERPLL_MISC_SATEN_SET_MSK 0x00004000
3593 /* The mask used to clear the ALT_CLKMGR_PERPLL_MISC_SATEN register field value. */
3594 #define ALT_CLKMGR_PERPLL_MISC_SATEN_CLR_MSK 0xffffbfff
3595 /* The reset value of the ALT_CLKMGR_PERPLL_MISC_SATEN register field. */
3596 #define ALT_CLKMGR_PERPLL_MISC_SATEN_RESET 0x1
3597 /* Extracts the ALT_CLKMGR_PERPLL_MISC_SATEN field value from a register. */
3598 #define ALT_CLKMGR_PERPLL_MISC_SATEN_GET(value) (((value) & 0x00004000) >> 14)
3599 /* Produces a ALT_CLKMGR_PERPLL_MISC_SATEN register field value suitable for setting the register. */
3600 #define ALT_CLKMGR_PERPLL_MISC_SATEN_SET(value) (((value) << 14) & 0x00004000)
3601 
3602 #ifndef __ASSEMBLY__
3603 /*
3604  * WARNING: The C register and register group struct declarations are provided for
3605  * convenience and illustrative purposes. They should, however, be used with
3606  * caution as the C language standard provides no guarantees about the alignment or
3607  * atomicity of device memory accesses. The recommended practice for writing
3608  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3609  * alt_write_word() functions.
3610  *
3611  * The struct declaration for register ALT_CLKMGR_PERPLL_MISC.
3612  */
3614 {
3615  uint32_t bwadjen : 1; /* Loop Bandwidth Adjust Enabled */
3616  uint32_t bwadj : 12; /* Loop Bandwidth Adjust */
3617  uint32_t fasten : 1; /* Fast Locking Enable */
3618  uint32_t saten : 1; /* Saturation Enable */
3619  uint32_t : 17; /* *UNDEFINED* */
3620 };
3621 
3622 /* The typedef declaration for register ALT_CLKMGR_PERPLL_MISC. */
3623 typedef volatile struct ALT_CLKMGR_PERPLL_MISC_s ALT_CLKMGR_PERPLL_MISC_t;
3624 #endif /* __ASSEMBLY__ */
3625 
3626 /* The byte offset of the ALT_CLKMGR_PERPLL_MISC register from the beginning of the component. */
3627 #define ALT_CLKMGR_PERPLL_MISC_OFST 0x4
3628 
3629 /*
3630  * Register : Peripheral PLL C0 Control Register for Clock emac0_clk - emac0clk
3631  *
3632  * Contains settings that control clock emac0_clk generated from the C0 output of
3633  * the Peripheral PLL.
3634  *
3635  * Only reset by a cold reset.
3636  *
3637  * Register Layout
3638  *
3639  * Bits | Access | Reset | Description
3640  * :-------|:-------|:------|:------------
3641  * [8:0] | RW | 0x1 | Counter
3642  * [31:9] | ??? | 0x0 | *UNDEFINED*
3643  *
3644  */
3645 /*
3646  * Field : Counter - cnt
3647  *
3648  * Divides the VCO frequency by the value+1 in this field.
3649  *
3650  * Field Access Macros:
3651  *
3652  */
3653 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field. */
3654 #define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_LSB 0
3655 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field. */
3656 #define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_MSB 8
3657 /* The width in bits of the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field. */
3658 #define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_WIDTH 9
3659 /* The mask used to set the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field value. */
3660 #define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_SET_MSK 0x000001ff
3661 /* The mask used to clear the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field value. */
3662 #define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_CLR_MSK 0xfffffe00
3663 /* The reset value of the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field. */
3664 #define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_RESET 0x1
3665 /* Extracts the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT field value from a register. */
3666 #define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
3667 /* Produces a ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field value suitable for setting the register. */
3668 #define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
3669 
3670 #ifndef __ASSEMBLY__
3671 /*
3672  * WARNING: The C register and register group struct declarations are provided for
3673  * convenience and illustrative purposes. They should, however, be used with
3674  * caution as the C language standard provides no guarantees about the alignment or
3675  * atomicity of device memory accesses. The recommended practice for writing
3676  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3677  * alt_write_word() functions.
3678  *
3679  * The struct declaration for register ALT_CLKMGR_PERPLL_EMAC0CLK.
3680  */
3682 {
3683  uint32_t cnt : 9; /* Counter */
3684  uint32_t : 23; /* *UNDEFINED* */
3685 };
3686 
3687 /* The typedef declaration for register ALT_CLKMGR_PERPLL_EMAC0CLK. */
3688 typedef volatile struct ALT_CLKMGR_PERPLL_EMAC0CLK_s ALT_CLKMGR_PERPLL_EMAC0CLK_t;
3689 #endif /* __ASSEMBLY__ */
3690 
3691 /* The byte offset of the ALT_CLKMGR_PERPLL_EMAC0CLK register from the beginning of the component. */
3692 #define ALT_CLKMGR_PERPLL_EMAC0CLK_OFST 0x8
3693 
3694 /*
3695  * Register : Peripheral PLL C1 Control Register for Clock emac1_clk - emac1clk
3696  *
3697  * Contains settings that control clock emac1_clk generated from the C1 output of
3698  * the Peripheral PLL.
3699  *
3700  * Only reset by a cold reset.
3701  *
3702  * Register Layout
3703  *
3704  * Bits | Access | Reset | Description
3705  * :-------|:-------|:------|:------------
3706  * [8:0] | RW | 0x1 | Counter
3707  * [31:9] | ??? | 0x0 | *UNDEFINED*
3708  *
3709  */
3710 /*
3711  * Field : Counter - cnt
3712  *
3713  * Divides the VCO frequency by the value+1 in this field.
3714  *
3715  * Field Access Macros:
3716  *
3717  */
3718 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field. */
3719 #define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_LSB 0
3720 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field. */
3721 #define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_MSB 8
3722 /* The width in bits of the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field. */
3723 #define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_WIDTH 9
3724 /* The mask used to set the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field value. */
3725 #define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_SET_MSK 0x000001ff
3726 /* The mask used to clear the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field value. */
3727 #define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_CLR_MSK 0xfffffe00
3728 /* The reset value of the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field. */
3729 #define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_RESET 0x1
3730 /* Extracts the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT field value from a register. */
3731 #define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
3732 /* Produces a ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field value suitable for setting the register. */
3733 #define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
3734 
3735 #ifndef __ASSEMBLY__
3736 /*
3737  * WARNING: The C register and register group struct declarations are provided for
3738  * convenience and illustrative purposes. They should, however, be used with
3739  * caution as the C language standard provides no guarantees about the alignment or
3740  * atomicity of device memory accesses. The recommended practice for writing
3741  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3742  * alt_write_word() functions.
3743  *
3744  * The struct declaration for register ALT_CLKMGR_PERPLL_EMAC1CLK.
3745  */
3747 {
3748  uint32_t cnt : 9; /* Counter */
3749  uint32_t : 23; /* *UNDEFINED* */
3750 };
3751 
3752 /* The typedef declaration for register ALT_CLKMGR_PERPLL_EMAC1CLK. */
3753 typedef volatile struct ALT_CLKMGR_PERPLL_EMAC1CLK_s ALT_CLKMGR_PERPLL_EMAC1CLK_t;
3754 #endif /* __ASSEMBLY__ */
3755 
3756 /* The byte offset of the ALT_CLKMGR_PERPLL_EMAC1CLK register from the beginning of the component. */
3757 #define ALT_CLKMGR_PERPLL_EMAC1CLK_OFST 0xc
3758 
3759 /*
3760  * Register : Peripheral PLL C2 Control Register for Clock periph_qspi_clk - perqspiclk
3761  *
3762  * Contains settings that control clock periph_qspi_clk generated from the C2
3763  * output of the Peripheral PLL.
3764  *
3765  * Only reset by a cold reset.
3766  *
3767  * Register Layout
3768  *
3769  * Bits | Access | Reset | Description
3770  * :-------|:-------|:------|:------------
3771  * [8:0] | RW | 0x1 | Counter
3772  * [31:9] | ??? | 0x0 | *UNDEFINED*
3773  *
3774  */
3775 /*
3776  * Field : Counter - cnt
3777  *
3778  * Divides the VCO frequency by the value+1 in this field.
3779  *
3780  * Field Access Macros:
3781  *
3782  */
3783 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field. */
3784 #define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_LSB 0
3785 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field. */
3786 #define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_MSB 8
3787 /* The width in bits of the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field. */
3788 #define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_WIDTH 9
3789 /* The mask used to set the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field value. */
3790 #define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_SET_MSK 0x000001ff
3791 /* The mask used to clear the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field value. */
3792 #define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_CLR_MSK 0xfffffe00
3793 /* The reset value of the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field. */
3794 #define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_RESET 0x1
3795 /* Extracts the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT field value from a register. */
3796 #define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
3797 /* Produces a ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field value suitable for setting the register. */
3798 #define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
3799 
3800 #ifndef __ASSEMBLY__
3801 /*
3802  * WARNING: The C register and register group struct declarations are provided for
3803  * convenience and illustrative purposes. They should, however, be used with
3804  * caution as the C language standard provides no guarantees about the alignment or
3805  * atomicity of device memory accesses. The recommended practice for writing
3806  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3807  * alt_write_word() functions.
3808  *
3809  * The struct declaration for register ALT_CLKMGR_PERPLL_PERQSPICLK.
3810  */
3812 {
3813  uint32_t cnt : 9; /* Counter */
3814  uint32_t : 23; /* *UNDEFINED* */
3815 };
3816 
3817 /* The typedef declaration for register ALT_CLKMGR_PERPLL_PERQSPICLK. */
3818 typedef volatile struct ALT_CLKMGR_PERPLL_PERQSPICLK_s ALT_CLKMGR_PERPLL_PERQSPICLK_t;
3819 #endif /* __ASSEMBLY__ */
3820 
3821 /* The byte offset of the ALT_CLKMGR_PERPLL_PERQSPICLK register from the beginning of the component. */
3822 #define ALT_CLKMGR_PERPLL_PERQSPICLK_OFST 0x10
3823 
3824 /*
3825  * Register : Peripheral PLL C3 Control Register for Clock periph_nand_sdmmc_clk - pernandsdmmcclk
3826  *
3827  * Contains settings that control clock periph_nand_sdmmc_clk generated from the C3
3828  * output of the Peripheral PLL.
3829  *
3830  * Only reset by a cold reset.
3831  *
3832  * Register Layout
3833  *
3834  * Bits | Access | Reset | Description
3835  * :-------|:-------|:------|:------------
3836  * [8:0] | RW | 0x1 | Counter
3837  * [31:9] | ??? | 0x0 | *UNDEFINED*
3838  *
3839  */
3840 /*
3841  * Field : Counter - cnt
3842  *
3843  * Divides the VCO frequency by the value+1 in this field.
3844  *
3845  * Field Access Macros:
3846  *
3847  */
3848 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field. */
3849 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_LSB 0
3850 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field. */
3851 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_MSB 8
3852 /* The width in bits of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field. */
3853 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_WIDTH 9
3854 /* The mask used to set the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field value. */
3855 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_SET_MSK 0x000001ff
3856 /* The mask used to clear the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field value. */
3857 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_CLR_MSK 0xfffffe00
3858 /* The reset value of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field. */
3859 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_RESET 0x1
3860 /* Extracts the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT field value from a register. */
3861 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
3862 /* Produces a ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field value suitable for setting the register. */
3863 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
3864 
3865 #ifndef __ASSEMBLY__
3866 /*
3867  * WARNING: The C register and register group struct declarations are provided for
3868  * convenience and illustrative purposes. They should, however, be used with
3869  * caution as the C language standard provides no guarantees about the alignment or
3870  * atomicity of device memory accesses. The recommended practice for writing
3871  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3872  * alt_write_word() functions.
3873  *
3874  * The struct declaration for register ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK.
3875  */
3877 {
3878  uint32_t cnt : 9; /* Counter */
3879  uint32_t : 23; /* *UNDEFINED* */
3880 };
3881 
3882 /* The typedef declaration for register ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK. */
3883 typedef volatile struct ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_s ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_t;
3884 #endif /* __ASSEMBLY__ */
3885 
3886 /* The byte offset of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK register from the beginning of the component. */
3887 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_OFST 0x14
3888 
3889 /*
3890  * Register : Peripheral PLL C4 Control Register for Clock periph_base_clk - perbaseclk
3891  *
3892  * Contains settings that control clock periph_base_clk generated from the C4
3893  * output of the Peripheral PLL.
3894  *
3895  * Only reset by a cold reset.
3896  *
3897  * Register Layout
3898  *
3899  * Bits | Access | Reset | Description
3900  * :-------|:-------|:------|:------------
3901  * [8:0] | RW | 0x1 | Counter
3902  * [31:9] | ??? | 0x0 | *UNDEFINED*
3903  *
3904  */
3905 /*
3906  * Field : Counter - cnt
3907  *
3908  * Divides the VCO frequency by the value+1 in this field.
3909  *
3910  * Field Access Macros:
3911  *
3912  */
3913 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field. */
3914 #define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_LSB 0
3915 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field. */
3916 #define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_MSB 8
3917 /* The width in bits of the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field. */
3918 #define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_WIDTH 9
3919 /* The mask used to set the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field value. */
3920 #define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_SET_MSK 0x000001ff
3921 /* The mask used to clear the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field value. */
3922 #define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_CLR_MSK 0xfffffe00
3923 /* The reset value of the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field. */
3924 #define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_RESET 0x1
3925 /* Extracts the ALT_CLKMGR_PERPLL_PERBASECLK_CNT field value from a register. */
3926 #define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
3927 /* Produces a ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field value suitable for setting the register. */
3928 #define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
3929 
3930 #ifndef __ASSEMBLY__
3931 /*
3932  * WARNING: The C register and register group struct declarations are provided for
3933  * convenience and illustrative purposes. They should, however, be used with
3934  * caution as the C language standard provides no guarantees about the alignment or
3935  * atomicity of device memory accesses. The recommended practice for writing
3936  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3937  * alt_write_word() functions.
3938  *
3939  * The struct declaration for register ALT_CLKMGR_PERPLL_PERBASECLK.
3940  */
3942 {
3943  uint32_t cnt : 9; /* Counter */
3944  uint32_t : 23; /* *UNDEFINED* */
3945 };
3946 
3947 /* The typedef declaration for register ALT_CLKMGR_PERPLL_PERBASECLK. */
3948 typedef volatile struct ALT_CLKMGR_PERPLL_PERBASECLK_s ALT_CLKMGR_PERPLL_PERBASECLK_t;
3949 #endif /* __ASSEMBLY__ */
3950 
3951 /* The byte offset of the ALT_CLKMGR_PERPLL_PERBASECLK register from the beginning of the component. */
3952 #define ALT_CLKMGR_PERPLL_PERBASECLK_OFST 0x18
3953 
3954 /*
3955  * Register : Peripheral PLL C5 Control Register for Clock s2f_user1_clk - s2fuser1clk
3956  *
3957  * Contains settings that control clock s2f_user1_clk generated from the C5 output
3958  * of the Peripheral PLL.
3959  *
3960  * Qsys and user documenation refer to s2f_user1_clk as h2f_user1_clk.
3961  *
3962  * Only reset by a cold reset.
3963  *
3964  * Register Layout
3965  *
3966  * Bits | Access | Reset | Description
3967  * :-------|:-------|:------|:------------
3968  * [8:0] | RW | 0x1 | Counter
3969  * [31:9] | ??? | 0x0 | *UNDEFINED*
3970  *
3971  */
3972 /*
3973  * Field : Counter - cnt
3974  *
3975  * Divides the VCO frequency by the value+1 in this field.
3976  *
3977  * Field Access Macros:
3978  *
3979  */
3980 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field. */
3981 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_LSB 0
3982 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field. */
3983 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_MSB 8
3984 /* The width in bits of the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field. */
3985 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_WIDTH 9
3986 /* The mask used to set the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field value. */
3987 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_SET_MSK 0x000001ff
3988 /* The mask used to clear the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field value. */
3989 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_CLR_MSK 0xfffffe00
3990 /* The reset value of the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field. */
3991 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_RESET 0x1
3992 /* Extracts the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT field value from a register. */
3993 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
3994 /* Produces a ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field value suitable for setting the register. */
3995 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
3996 
3997 #ifndef __ASSEMBLY__
3998 /*
3999  * WARNING: The C register and register group struct declarations are provided for
4000  * convenience and illustrative purposes. They should, however, be used with
4001  * caution as the C language standard provides no guarantees about the alignment or
4002  * atomicity of device memory accesses. The recommended practice for writing
4003  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4004  * alt_write_word() functions.
4005  *
4006  * The struct declaration for register ALT_CLKMGR_PERPLL_S2FUSER1CLK.
4007  */
4009 {
4010  uint32_t cnt : 9; /* Counter */
4011  uint32_t : 23; /* *UNDEFINED* */
4012 };
4013 
4014 /* The typedef declaration for register ALT_CLKMGR_PERPLL_S2FUSER1CLK. */
4015 typedef volatile struct ALT_CLKMGR_PERPLL_S2FUSER1CLK_s ALT_CLKMGR_PERPLL_S2FUSER1CLK_t;
4016 #endif /* __ASSEMBLY__ */
4017 
4018 /* The byte offset of the ALT_CLKMGR_PERPLL_S2FUSER1CLK register from the beginning of the component. */
4019 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_OFST 0x1c
4020 
4021 /*
4022  * Register : Enable Register - en
4023  *
4024  * Contains fields that control clock enables for clocks derived from the
4025  * Peripheral PLL
4026  *
4027  * 1: The clock is enabled.
4028  *
4029  * 0: The clock is disabled.
4030  *
4031  * Fields are only reset by a cold reset.
4032  *
4033  * Register Layout
4034  *
4035  * Bits | Access | Reset | Description
4036  * :--------|:-------|:------|:---------------------
4037  * [0] | RW | 0x1 | emac0_clk Enable
4038  * [1] | RW | 0x1 | emac1_clk Enable
4039  * [2] | RW | 0x1 | usb_mp_clk Enable
4040  * [3] | RW | 0x1 | spi_m_clk Enable
4041  * [4] | RW | 0x1 | can0_clk Enable
4042  * [5] | RW | 0x1 | can1_clk Enable
4043  * [6] | RW | 0x1 | gpio_clk Enable
4044  * [7] | RW | 0x1 | s2f_user1_clk Enable
4045  * [8] | RW | 0x1 | sdmmc_clk Enable
4046  * [9] | RW | 0x1 | nand_x_clk Enable
4047  * [10] | RW | 0x1 | nand_clk Enable
4048  * [11] | RW | 0x1 | qspi_clk Enable
4049  * [31:12] | ??? | 0x0 | *UNDEFINED*
4050  *
4051  */
4052 /*
4053  * Field : emac0_clk Enable - emac0clk
4054  *
4055  * Enables clock emac0_clk output
4056  *
4057  * Field Access Macros:
4058  *
4059  */
4060 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field. */
4061 #define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_LSB 0
4062 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field. */
4063 #define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_MSB 0
4064 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field. */
4065 #define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_WIDTH 1
4066 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field value. */
4067 #define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK 0x00000001
4068 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field value. */
4069 #define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_CLR_MSK 0xfffffffe
4070 /* The reset value of the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field. */
4071 #define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_RESET 0x1
4072 /* Extracts the ALT_CLKMGR_PERPLL_EN_EMAC0CLK field value from a register. */
4073 #define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_GET(value) (((value) & 0x00000001) >> 0)
4074 /* Produces a ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field value suitable for setting the register. */
4075 #define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET(value) (((value) << 0) & 0x00000001)
4076 
4077 /*
4078  * Field : emac1_clk Enable - emac1clk
4079  *
4080  * Enables clock emac1_clk output
4081  *
4082  * Field Access Macros:
4083  *
4084  */
4085 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field. */
4086 #define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_LSB 1
4087 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field. */
4088 #define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_MSB 1
4089 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field. */
4090 #define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_WIDTH 1
4091 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field value. */
4092 #define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK 0x00000002
4093 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field value. */
4094 #define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_CLR_MSK 0xfffffffd
4095 /* The reset value of the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field. */
4096 #define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_RESET 0x1
4097 /* Extracts the ALT_CLKMGR_PERPLL_EN_EMAC1CLK field value from a register. */
4098 #define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_GET(value) (((value) & 0x00000002) >> 1)
4099 /* Produces a ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field value suitable for setting the register. */
4100 #define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET(value) (((value) << 1) & 0x00000002)
4101 
4102 /*
4103  * Field : usb_mp_clk Enable - usbclk
4104  *
4105  * Enables clock usb_mp_clk output
4106  *
4107  * Field Access Macros:
4108  *
4109  */
4110 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_USBCLK register field. */
4111 #define ALT_CLKMGR_PERPLL_EN_USBCLK_LSB 2
4112 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_USBCLK register field. */
4113 #define ALT_CLKMGR_PERPLL_EN_USBCLK_MSB 2
4114 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_USBCLK register field. */
4115 #define ALT_CLKMGR_PERPLL_EN_USBCLK_WIDTH 1
4116 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_USBCLK register field value. */
4117 #define ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK 0x00000004
4118 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_USBCLK register field value. */
4119 #define ALT_CLKMGR_PERPLL_EN_USBCLK_CLR_MSK 0xfffffffb
4120 /* The reset value of the ALT_CLKMGR_PERPLL_EN_USBCLK register field. */
4121 #define ALT_CLKMGR_PERPLL_EN_USBCLK_RESET 0x1
4122 /* Extracts the ALT_CLKMGR_PERPLL_EN_USBCLK field value from a register. */
4123 #define ALT_CLKMGR_PERPLL_EN_USBCLK_GET(value) (((value) & 0x00000004) >> 2)
4124 /* Produces a ALT_CLKMGR_PERPLL_EN_USBCLK register field value suitable for setting the register. */
4125 #define ALT_CLKMGR_PERPLL_EN_USBCLK_SET(value) (((value) << 2) & 0x00000004)
4126 
4127 /*
4128  * Field : spi_m_clk Enable - spimclk
4129  *
4130  * Enables clock spi_m_clk output
4131  *
4132  * Field Access Macros:
4133  *
4134  */
4135 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field. */
4136 #define ALT_CLKMGR_PERPLL_EN_SPIMCLK_LSB 3
4137 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field. */
4138 #define ALT_CLKMGR_PERPLL_EN_SPIMCLK_MSB 3
4139 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field. */
4140 #define ALT_CLKMGR_PERPLL_EN_SPIMCLK_WIDTH 1
4141 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field value. */
4142 #define ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK 0x00000008
4143 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field value. */
4144 #define ALT_CLKMGR_PERPLL_EN_SPIMCLK_CLR_MSK 0xfffffff7
4145 /* The reset value of the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field. */
4146 #define ALT_CLKMGR_PERPLL_EN_SPIMCLK_RESET 0x1
4147 /* Extracts the ALT_CLKMGR_PERPLL_EN_SPIMCLK field value from a register. */
4148 #define ALT_CLKMGR_PERPLL_EN_SPIMCLK_GET(value) (((value) & 0x00000008) >> 3)
4149 /* Produces a ALT_CLKMGR_PERPLL_EN_SPIMCLK register field value suitable for setting the register. */
4150 #define ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET(value) (((value) << 3) & 0x00000008)
4151 
4152 /*
4153  * Field : can0_clk Enable - can0clk
4154  *
4155  * Enables clock can0_clk output
4156  *
4157  * Field Access Macros:
4158  *
4159  */
4160 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field. */
4161 #define ALT_CLKMGR_PERPLL_EN_CAN0CLK_LSB 4
4162 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field. */
4163 #define ALT_CLKMGR_PERPLL_EN_CAN0CLK_MSB 4
4164 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field. */
4165 #define ALT_CLKMGR_PERPLL_EN_CAN0CLK_WIDTH 1
4166 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field value. */
4167 #define ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK 0x00000010
4168 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field value. */
4169 #define ALT_CLKMGR_PERPLL_EN_CAN0CLK_CLR_MSK 0xffffffef
4170 /* The reset value of the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field. */
4171 #define ALT_CLKMGR_PERPLL_EN_CAN0CLK_RESET 0x1
4172 /* Extracts the ALT_CLKMGR_PERPLL_EN_CAN0CLK field value from a register. */
4173 #define ALT_CLKMGR_PERPLL_EN_CAN0CLK_GET(value) (((value) & 0x00000010) >> 4)
4174 /* Produces a ALT_CLKMGR_PERPLL_EN_CAN0CLK register field value suitable for setting the register. */
4175 #define ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET(value) (((value) << 4) & 0x00000010)
4176 
4177 /*
4178  * Field : can1_clk Enable - can1clk
4179  *
4180  * Enables clock can1_clk output
4181  *
4182  * Field Access Macros:
4183  *
4184  */
4185 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field. */
4186 #define ALT_CLKMGR_PERPLL_EN_CAN1CLK_LSB 5
4187 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field. */
4188 #define ALT_CLKMGR_PERPLL_EN_CAN1CLK_MSB 5
4189 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field. */
4190 #define ALT_CLKMGR_PERPLL_EN_CAN1CLK_WIDTH 1
4191 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field value. */
4192 #define ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK 0x00000020
4193 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field value. */
4194 #define ALT_CLKMGR_PERPLL_EN_CAN1CLK_CLR_MSK 0xffffffdf
4195 /* The reset value of the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field. */
4196 #define ALT_CLKMGR_PERPLL_EN_CAN1CLK_RESET 0x1
4197 /* Extracts the ALT_CLKMGR_PERPLL_EN_CAN1CLK field value from a register. */
4198 #define ALT_CLKMGR_PERPLL_EN_CAN1CLK_GET(value) (((value) & 0x00000020) >> 5)
4199 /* Produces a ALT_CLKMGR_PERPLL_EN_CAN1CLK register field value suitable for setting the register. */
4200 #define ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET(value) (((value) << 5) & 0x00000020)
4201 
4202 /*
4203  * Field : gpio_clk Enable - gpioclk
4204  *
4205  * Enables clock gpio_clk output
4206  *
4207  * Field Access Macros:
4208  *
4209  */
4210 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field. */
4211 #define ALT_CLKMGR_PERPLL_EN_GPIOCLK_LSB 6
4212 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field. */
4213 #define ALT_CLKMGR_PERPLL_EN_GPIOCLK_MSB 6
4214 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field. */
4215 #define ALT_CLKMGR_PERPLL_EN_GPIOCLK_WIDTH 1
4216 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field value. */
4217 #define ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK 0x00000040
4218 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field value. */
4219 #define ALT_CLKMGR_PERPLL_EN_GPIOCLK_CLR_MSK 0xffffffbf
4220 /* The reset value of the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field. */
4221 #define ALT_CLKMGR_PERPLL_EN_GPIOCLK_RESET 0x1
4222 /* Extracts the ALT_CLKMGR_PERPLL_EN_GPIOCLK field value from a register. */
4223 #define ALT_CLKMGR_PERPLL_EN_GPIOCLK_GET(value) (((value) & 0x00000040) >> 6)
4224 /* Produces a ALT_CLKMGR_PERPLL_EN_GPIOCLK register field value suitable for setting the register. */
4225 #define ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET(value) (((value) << 6) & 0x00000040)
4226 
4227 /*
4228  * Field : s2f_user1_clk Enable - s2fuser1clk
4229  *
4230  * Enables clock s2f_user1_clk output.
4231  *
4232  * Qsys and user documenation refer to s2f_user1_clk as h2f_user1_clk.
4233  *
4234  * Field Access Macros:
4235  *
4236  */
4237 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field. */
4238 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_LSB 7
4239 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field. */
4240 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_MSB 7
4241 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field. */
4242 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_WIDTH 1
4243 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field value. */
4244 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK 0x00000080
4245 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field value. */
4246 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_CLR_MSK 0xffffff7f
4247 /* The reset value of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field. */
4248 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_RESET 0x1
4249 /* Extracts the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK field value from a register. */
4250 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_GET(value) (((value) & 0x00000080) >> 7)
4251 /* Produces a ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field value suitable for setting the register. */
4252 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET(value) (((value) << 7) & 0x00000080)
4253 
4254 /*
4255  * Field : sdmmc_clk Enable - sdmmcclk
4256  *
4257  * Enables clock sdmmc_clk output
4258  *
4259  * Field Access Macros:
4260  *
4261  */
4262 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field. */
4263 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_LSB 8
4264 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field. */
4265 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_MSB 8
4266 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field. */
4267 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_WIDTH 1
4268 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field value. */
4269 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK 0x00000100
4270 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field value. */
4271 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_CLR_MSK 0xfffffeff
4272 /* The reset value of the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field. */
4273 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_RESET 0x1
4274 /* Extracts the ALT_CLKMGR_PERPLL_EN_SDMMCCLK field value from a register. */
4275 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_GET(value) (((value) & 0x00000100) >> 8)
4276 /* Produces a ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field value suitable for setting the register. */
4277 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET(value) (((value) << 8) & 0x00000100)
4278 
4279 /*
4280  * Field : nand_x_clk Enable - nandxclk
4281  *
4282  * Enables clock nand_x_clk output
4283  *
4284  * nand_clk Enable should always be de-asserted before the nand_x_clk Enable, and
4285  * the nand_x_clk Enable should always be asserted before the nand_clk Enable is
4286  * asserted. A brief delay is also required between switching the enables (8 *
4287  * nand_clk period).
4288  *
4289  * Field Access Macros:
4290  *
4291  */
4292 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field. */
4293 #define ALT_CLKMGR_PERPLL_EN_NANDXCLK_LSB 9
4294 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field. */
4295 #define ALT_CLKMGR_PERPLL_EN_NANDXCLK_MSB 9
4296 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field. */
4297 #define ALT_CLKMGR_PERPLL_EN_NANDXCLK_WIDTH 1
4298 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field value. */
4299 #define ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK 0x00000200
4300 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field value. */
4301 #define ALT_CLKMGR_PERPLL_EN_NANDXCLK_CLR_MSK 0xfffffdff
4302 /* The reset value of the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field. */
4303 #define ALT_CLKMGR_PERPLL_EN_NANDXCLK_RESET 0x1
4304 /* Extracts the ALT_CLKMGR_PERPLL_EN_NANDXCLK field value from a register. */
4305 #define ALT_CLKMGR_PERPLL_EN_NANDXCLK_GET(value) (((value) & 0x00000200) >> 9)
4306 /* Produces a ALT_CLKMGR_PERPLL_EN_NANDXCLK register field value suitable for setting the register. */
4307 #define ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET(value) (((value) << 9) & 0x00000200)
4308 
4309 /*
4310  * Field : nand_clk Enable - nandclk
4311  *
4312  * Enables clock nand_clk output
4313  *
4314  * nand_clk Enable should always be de-asserted before the nand_x_clk Enable, and
4315  * the nand_x_clk Enable should always be asserted before the nand_clk Enable is
4316  * asserted. A brief delay is also required between switching the enables (8 *
4317  * nand_clk period).
4318  *
4319  * Field Access Macros:
4320  *
4321  */
4322 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_NANDCLK register field. */
4323 #define ALT_CLKMGR_PERPLL_EN_NANDCLK_LSB 10
4324 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_NANDCLK register field. */
4325 #define ALT_CLKMGR_PERPLL_EN_NANDCLK_MSB 10
4326 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_NANDCLK register field. */
4327 #define ALT_CLKMGR_PERPLL_EN_NANDCLK_WIDTH 1
4328 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_NANDCLK register field value. */
4329 #define ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK 0x00000400
4330 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_NANDCLK register field value. */
4331 #define ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK 0xfffffbff
4332 /* The reset value of the ALT_CLKMGR_PERPLL_EN_NANDCLK register field. */
4333 #define ALT_CLKMGR_PERPLL_EN_NANDCLK_RESET 0x1
4334 /* Extracts the ALT_CLKMGR_PERPLL_EN_NANDCLK field value from a register. */
4335 #define ALT_CLKMGR_PERPLL_EN_NANDCLK_GET(value) (((value) & 0x00000400) >> 10)
4336 /* Produces a ALT_CLKMGR_PERPLL_EN_NANDCLK register field value suitable for setting the register. */
4337 #define ALT_CLKMGR_PERPLL_EN_NANDCLK_SET(value) (((value) << 10) & 0x00000400)
4338 
4339 /*
4340  * Field : qspi_clk Enable - qspiclk
4341  *
4342  * Enables clock qspi_clk output
4343  *
4344  * Field Access Macros:
4345  *
4346  */
4347 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_QSPICLK register field. */
4348 #define ALT_CLKMGR_PERPLL_EN_QSPICLK_LSB 11
4349 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_QSPICLK register field. */
4350 #define ALT_CLKMGR_PERPLL_EN_QSPICLK_MSB 11
4351 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_QSPICLK register field. */
4352 #define ALT_CLKMGR_PERPLL_EN_QSPICLK_WIDTH 1
4353 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_QSPICLK register field value. */
4354 #define ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK 0x00000800
4355 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_QSPICLK register field value. */
4356 #define ALT_CLKMGR_PERPLL_EN_QSPICLK_CLR_MSK 0xfffff7ff
4357 /* The reset value of the ALT_CLKMGR_PERPLL_EN_QSPICLK register field. */
4358 #define ALT_CLKMGR_PERPLL_EN_QSPICLK_RESET 0x1
4359 /* Extracts the ALT_CLKMGR_PERPLL_EN_QSPICLK field value from a register. */
4360 #define ALT_CLKMGR_PERPLL_EN_QSPICLK_GET(value) (((value) & 0x00000800) >> 11)
4361 /* Produces a ALT_CLKMGR_PERPLL_EN_QSPICLK register field value suitable for setting the register. */
4362 #define ALT_CLKMGR_PERPLL_EN_QSPICLK_SET(value) (((value) << 11) & 0x00000800)
4363 
4364 #ifndef __ASSEMBLY__
4365 /*
4366  * WARNING: The C register and register group struct declarations are provided for
4367  * convenience and illustrative purposes. They should, however, be used with
4368  * caution as the C language standard provides no guarantees about the alignment or
4369  * atomicity of device memory accesses. The recommended practice for writing
4370  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4371  * alt_write_word() functions.
4372  *
4373  * The struct declaration for register ALT_CLKMGR_PERPLL_EN.
4374  */
4376 {
4377  uint32_t emac0clk : 1; /* emac0_clk Enable */
4378  uint32_t emac1clk : 1; /* emac1_clk Enable */
4379  uint32_t usbclk : 1; /* usb_mp_clk Enable */
4380  uint32_t spimclk : 1; /* spi_m_clk Enable */
4381  uint32_t can0clk : 1; /* can0_clk Enable */
4382  uint32_t can1clk : 1; /* can1_clk Enable */
4383  uint32_t gpioclk : 1; /* gpio_clk Enable */
4384  uint32_t s2fuser1clk : 1; /* s2f_user1_clk Enable */
4385  uint32_t sdmmcclk : 1; /* sdmmc_clk Enable */
4386  uint32_t nandxclk : 1; /* nand_x_clk Enable */
4387  uint32_t nandclk : 1; /* nand_clk Enable */
4388  uint32_t qspiclk : 1; /* qspi_clk Enable */
4389  uint32_t : 20; /* *UNDEFINED* */
4390 };
4391 
4392 /* The typedef declaration for register ALT_CLKMGR_PERPLL_EN. */
4393 typedef volatile struct ALT_CLKMGR_PERPLL_EN_s ALT_CLKMGR_PERPLL_EN_t;
4394 #endif /* __ASSEMBLY__ */
4395 
4396 /* The byte offset of the ALT_CLKMGR_PERPLL_EN register from the beginning of the component. */
4397 #define ALT_CLKMGR_PERPLL_EN_OFST 0x20
4398 
4399 /*
4400  * Register : Divide Register - div
4401  *
4402  * Contains fields that control clock dividers for clocks derived from the
4403  * Peripheral PLL
4404  *
4405  * Fields are only reset by a cold reset.
4406  *
4407  * Register Layout
4408  *
4409  * Bits | Access | Reset | Description
4410  * :--------|:-------|:------|:-------------------------
4411  * [2:0] | RW | 0x0 | USB Clock Divider
4412  * [5:3] | RW | 0x0 | SPI Master Clock Divider
4413  * [8:6] | RW | 0x0 | CAN0 Clock Divider
4414  * [11:9] | RW | 0x0 | CAN1 Clock Divider
4415  * [31:12] | ??? | 0x0 | *UNDEFINED*
4416  *
4417  */
4418 /*
4419  * Field : USB Clock Divider - usbclk
4420  *
4421  * The usb_mp_clk is divided down from the periph_base_clk by the value specified
4422  * in this field.
4423  *
4424  * Field Enumeration Values:
4425  *
4426  * Enum | Value | Description
4427  * :--------------------------------------|:------|:-------------
4428  * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV1 | 0x0 | Divide By 1
4429  * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV2 | 0x1 | Divide By 2
4430  * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV4 | 0x2 | Divide By 4
4431  * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV8 | 0x3 | Divide By 8
4432  * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV16 | 0x4 | Divide By 16
4433  * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_1 | 0x5 | Reserved
4434  * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_2 | 0x6 | Reserved
4435  * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_3 | 0x7 | Reserved
4436  *
4437  * Field Access Macros:
4438  *
4439  */
4440 /*
4441  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK
4442  *
4443  * Divide By 1
4444  */
4445 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV1 0x0
4446 /*
4447  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK
4448  *
4449  * Divide By 2
4450  */
4451 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV2 0x1
4452 /*
4453  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK
4454  *
4455  * Divide By 4
4456  */
4457 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV4 0x2
4458 /*
4459  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK
4460  *
4461  * Divide By 8
4462  */
4463 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV8 0x3
4464 /*
4465  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK
4466  *
4467  * Divide By 16
4468  */
4469 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV16 0x4
4470 /*
4471  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK
4472  *
4473  * Reserved
4474  */
4475 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_1 0x5
4476 /*
4477  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK
4478  *
4479  * Reserved
4480  */
4481 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_2 0x6
4482 /*
4483  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK
4484  *
4485  * Reserved
4486  */
4487 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_3 0x7
4488 
4489 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_DIV_USBCLK register field. */
4490 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_LSB 0
4491 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_DIV_USBCLK register field. */
4492 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_MSB 2
4493 /* The width in bits of the ALT_CLKMGR_PERPLL_DIV_USBCLK register field. */
4494 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_WIDTH 3
4495 /* The mask used to set the ALT_CLKMGR_PERPLL_DIV_USBCLK register field value. */
4496 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_SET_MSK 0x00000007
4497 /* The mask used to clear the ALT_CLKMGR_PERPLL_DIV_USBCLK register field value. */
4498 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_CLR_MSK 0xfffffff8
4499 /* The reset value of the ALT_CLKMGR_PERPLL_DIV_USBCLK register field. */
4500 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_RESET 0x0
4501 /* Extracts the ALT_CLKMGR_PERPLL_DIV_USBCLK field value from a register. */
4502 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_GET(value) (((value) & 0x00000007) >> 0)
4503 /* Produces a ALT_CLKMGR_PERPLL_DIV_USBCLK register field value suitable for setting the register. */
4504 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_SET(value) (((value) << 0) & 0x00000007)
4505 
4506 /*
4507  * Field : SPI Master Clock Divider - spimclk
4508  *
4509  * The spi_m_clk is divided down from the periph_base_clk by the value specified in
4510  * this field.
4511  *
4512  * Field Enumeration Values:
4513  *
4514  * Enum | Value | Description
4515  * :---------------------------------------|:------|:-------------
4516  * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV1 | 0x0 | Divide By 1
4517  * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV2 | 0x1 | Divide By 2
4518  * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV4 | 0x2 | Divide By 4
4519  * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV8 | 0x3 | Divide By 8
4520  * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV16 | 0x4 | Divide By 16
4521  * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_1 | 0x5 | Reserved
4522  * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_2 | 0x6 | Reserved
4523  * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_3 | 0x7 | Reserved
4524  *
4525  * Field Access Macros:
4526  *
4527  */
4528 /*
4529  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK
4530  *
4531  * Divide By 1
4532  */
4533 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV1 0x0
4534 /*
4535  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK
4536  *
4537  * Divide By 2
4538  */
4539 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV2 0x1
4540 /*
4541  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK
4542  *
4543  * Divide By 4
4544  */
4545 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV4 0x2
4546 /*
4547  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK
4548  *
4549  * Divide By 8
4550  */
4551 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV8 0x3
4552 /*
4553  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK
4554  *
4555  * Divide By 16
4556  */
4557 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV16 0x4
4558 /*
4559  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK
4560  *
4561  * Reserved
4562  */
4563 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_1 0x5
4564 /*
4565  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK
4566  *
4567  * Reserved
4568  */
4569 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_2 0x6
4570 /*
4571  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK
4572  *
4573  * Reserved
4574  */
4575 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_3 0x7
4576 
4577 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field. */
4578 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_LSB 3
4579 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field. */
4580 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_MSB 5
4581 /* The width in bits of the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field. */
4582 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_WIDTH 3
4583 /* The mask used to set the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field value. */
4584 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_SET_MSK 0x00000038
4585 /* The mask used to clear the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field value. */
4586 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_CLR_MSK 0xffffffc7
4587 /* The reset value of the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field. */
4588 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_RESET 0x0
4589 /* Extracts the ALT_CLKMGR_PERPLL_DIV_SPIMCLK field value from a register. */
4590 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_GET(value) (((value) & 0x00000038) >> 3)
4591 /* Produces a ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field value suitable for setting the register. */
4592 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_SET(value) (((value) << 3) & 0x00000038)
4593 
4594 /*
4595  * Field : CAN0 Clock Divider - can0clk
4596  *
4597  * The can0_clk is divided down from the periph_base_clk by the value specified in
4598  * this field.
4599  *
4600  * Field Enumeration Values:
4601  *
4602  * Enum | Value | Description
4603  * :---------------------------------------|:------|:-------------
4604  * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV1 | 0x0 | Divide By 1
4605  * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV2 | 0x1 | Divide By 2
4606  * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV4 | 0x2 | Divide By 4
4607  * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV8 | 0x3 | Divide By 8
4608  * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV16 | 0x4 | Divide By 16
4609  * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_1 | 0x5 | Reserved
4610  * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_2 | 0x6 | Reserved
4611  * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_3 | 0x7 | Reserved
4612  *
4613  * Field Access Macros:
4614  *
4615  */
4616 /*
4617  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK
4618  *
4619  * Divide By 1
4620  */
4621 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV1 0x0
4622 /*
4623  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK
4624  *
4625  * Divide By 2
4626  */
4627 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV2 0x1
4628 /*
4629  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK
4630  *
4631  * Divide By 4
4632  */
4633 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV4 0x2
4634 /*
4635  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK
4636  *
4637  * Divide By 8
4638  */
4639 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV8 0x3
4640 /*
4641  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK
4642  *
4643  * Divide By 16
4644  */
4645 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV16 0x4
4646 /*
4647  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK
4648  *
4649  * Reserved
4650  */
4651 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_1 0x5
4652 /*
4653  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK
4654  *
4655  * Reserved
4656  */
4657 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_2 0x6
4658 /*
4659  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK
4660  *
4661  * Reserved
4662  */
4663 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_3 0x7
4664 
4665 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field. */
4666 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_LSB 6
4667 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field. */
4668 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_MSB 8
4669 /* The width in bits of the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field. */
4670 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_WIDTH 3
4671 /* The mask used to set the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field value. */
4672 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_SET_MSK 0x000001c0
4673 /* The mask used to clear the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field value. */
4674 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_CLR_MSK 0xfffffe3f
4675 /* The reset value of the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field. */
4676 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_RESET 0x0
4677 /* Extracts the ALT_CLKMGR_PERPLL_DIV_CAN0CLK field value from a register. */
4678 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_GET(value) (((value) & 0x000001c0) >> 6)
4679 /* Produces a ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field value suitable for setting the register. */
4680 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_SET(value) (((value) << 6) & 0x000001c0)
4681 
4682 /*
4683  * Field : CAN1 Clock Divider - can1clk
4684  *
4685  * The can1_clk is divided down from the periph_base_clk by the value specified in
4686  * this field.
4687  *
4688  * Field Enumeration Values:
4689  *
4690  * Enum | Value | Description
4691  * :---------------------------------------|:------|:-------------
4692  * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV1 | 0x0 | Divide By 1
4693  * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV2 | 0x1 | Divide By 2
4694  * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV4 | 0x2 | Divide By 4
4695  * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV8 | 0x3 | Divide By 8
4696  * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV16 | 0x4 | Divide By 16
4697  * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_1 | 0x5 | Reserved
4698  * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_2 | 0x6 | Reserved
4699  * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_3 | 0x7 | Reserved
4700  *
4701  * Field Access Macros:
4702  *
4703  */
4704 /*
4705  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK
4706  *
4707  * Divide By 1
4708  */
4709 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV1 0x0
4710 /*
4711  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK
4712  *
4713  * Divide By 2
4714  */
4715 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV2 0x1
4716 /*
4717  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK
4718  *
4719  * Divide By 4
4720  */
4721 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV4 0x2
4722 /*
4723  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK
4724  *
4725  * Divide By 8
4726  */
4727 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV8 0x3
4728 /*
4729  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK
4730  *
4731  * Divide By 16
4732  */
4733 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV16 0x4
4734 /*
4735  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK
4736  *
4737  * Reserved
4738  */
4739 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_1 0x5
4740 /*
4741  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK
4742  *
4743  * Reserved
4744  */
4745 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_2 0x6
4746 /*
4747  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK
4748  *
4749  * Reserved
4750  */
4751 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_3 0x7
4752 
4753 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field. */
4754 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_LSB 9
4755 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field. */
4756 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_MSB 11
4757 /* The width in bits of the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field. */
4758 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_WIDTH 3
4759 /* The mask used to set the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field value. */
4760 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_SET_MSK 0x00000e00
4761 /* The mask used to clear the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field value. */
4762 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_CLR_MSK 0xfffff1ff
4763 /* The reset value of the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field. */
4764 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_RESET 0x0
4765 /* Extracts the ALT_CLKMGR_PERPLL_DIV_CAN1CLK field value from a register. */
4766 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_GET(value) (((value) & 0x00000e00) >> 9)
4767 /* Produces a ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field value suitable for setting the register. */
4768 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_SET(value) (((value) << 9) & 0x00000e00)
4769 
4770 #ifndef __ASSEMBLY__
4771 /*
4772  * WARNING: The C register and register group struct declarations are provided for
4773  * convenience and illustrative purposes. They should, however, be used with
4774  * caution as the C language standard provides no guarantees about the alignment or
4775  * atomicity of device memory accesses. The recommended practice for writing
4776  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4777  * alt_write_word() functions.
4778  *
4779  * The struct declaration for register ALT_CLKMGR_PERPLL_DIV.
4780  */
4782 {
4783  uint32_t usbclk : 3; /* USB Clock Divider */
4784  uint32_t spimclk : 3; /* SPI Master Clock Divider */
4785  uint32_t can0clk : 3; /* CAN0 Clock Divider */
4786  uint32_t can1clk : 3; /* CAN1 Clock Divider */
4787  uint32_t : 20; /* *UNDEFINED* */
4788 };
4789 
4790 /* The typedef declaration for register ALT_CLKMGR_PERPLL_DIV. */
4791 typedef volatile struct ALT_CLKMGR_PERPLL_DIV_s ALT_CLKMGR_PERPLL_DIV_t;
4792 #endif /* __ASSEMBLY__ */
4793 
4794 /* The byte offset of the ALT_CLKMGR_PERPLL_DIV register from the beginning of the component. */
4795 #define ALT_CLKMGR_PERPLL_DIV_OFST 0x24
4796 
4797 /*
4798  * Register : GPIO Divide Register - gpiodiv
4799  *
4800  * Contains a field that controls the clock divider for the GPIO De-bounce clock.
4801  *
4802  * Only reset by a cold reset.
4803  *
4804  * Register Layout
4805  *
4806  * Bits | Access | Reset | Description
4807  * :--------|:-------|:------|:-----------------------------
4808  * [23:0] | RW | 0x1 | GPIO De-bounce Clock Divider
4809  * [31:24] | ??? | 0x0 | *UNDEFINED*
4810  *
4811  */
4812 /*
4813  * Field : GPIO De-bounce Clock Divider - gpiodbclk
4814  *
4815  * The gpio_db_clk is divided down from the periph_base_clk by the value plus one
4816  * specified in this field. The value 0 (divide by 1) is illegal. A value of 1
4817  * indicates divide by 2, 2 divide by 3, etc.
4818  *
4819  * Field Access Macros:
4820  *
4821  */
4822 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */
4823 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_LSB 0
4824 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */
4825 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_MSB 23
4826 /* The width in bits of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */
4827 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_WIDTH 24
4828 /* The mask used to set the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field value. */
4829 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET_MSK 0x00ffffff
4830 /* The mask used to clear the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field value. */
4831 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_CLR_MSK 0xff000000
4832 /* The reset value of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */
4833 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_RESET 0x1
4834 /* Extracts the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK field value from a register. */
4835 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_GET(value) (((value) & 0x00ffffff) >> 0)
4836 /* Produces a ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field value suitable for setting the register. */
4837 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(value) (((value) << 0) & 0x00ffffff)
4838 
4839 #ifndef __ASSEMBLY__
4840 /*
4841  * WARNING: The C register and register group struct declarations are provided for
4842  * convenience and illustrative purposes. They should, however, be used with
4843  * caution as the C language standard provides no guarantees about the alignment or
4844  * atomicity of device memory accesses. The recommended practice for writing
4845  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4846  * alt_write_word() functions.
4847  *
4848  * The struct declaration for register ALT_CLKMGR_PERPLL_GPIODIV.
4849  */
4851 {
4852  uint32_t gpiodbclk : 24; /* GPIO De-bounce Clock Divider */
4853  uint32_t : 8; /* *UNDEFINED* */
4854 };
4855 
4856 /* The typedef declaration for register ALT_CLKMGR_PERPLL_GPIODIV. */
4857 typedef volatile struct ALT_CLKMGR_PERPLL_GPIODIV_s ALT_CLKMGR_PERPLL_GPIODIV_t;
4858 #endif /* __ASSEMBLY__ */
4859 
4860 /* The byte offset of the ALT_CLKMGR_PERPLL_GPIODIV register from the beginning of the component. */
4861 #define ALT_CLKMGR_PERPLL_GPIODIV_OFST 0x28
4862 
4863 /*
4864  * Register : Flash Clock Source Register - src
4865  *
4866  * Contains fields that select the source clocks for the flash controllers.
4867  *
4868  * Fields are only reset by a cold reset.
4869  *
4870  * Register Layout
4871  *
4872  * Bits | Access | Reset | Description
4873  * :-------|:-------|:------|:-------------------
4874  * [1:0] | RW | 0x1 | SDMMC Clock Source
4875  * [3:2] | RW | 0x1 | NAND Clock Source
4876  * [5:4] | RW | 0x1 | QSPI Clock Source
4877  * [31:6] | ??? | 0x0 | *UNDEFINED*
4878  *
4879  */
4880 /*
4881  * Field : SDMMC Clock Source - sdmmc
4882  *
4883  * Selects the source clock for the SDMMC.
4884  *
4885  * Qsys and user documenation refer to f2s_periph_ref_clk as f2h_periph_ref_clk.
4886  *
4887  * Field Enumeration Values:
4888  *
4889  * Enum | Value | Description
4890  * :-------------------------------------------------|:------|:----------------------
4891  * ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK | 0x0 | f2s_periph_ref_clk
4892  * ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK | 0x1 | main_nand_sdmmc_clk
4893  * ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK | 0x2 | periph_nand_sdmmc_clk
4894  *
4895  * Field Access Macros:
4896  *
4897  */
4898 /*
4899  * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_SDMMC
4900  *
4901  * f2s_periph_ref_clk
4902  */
4903 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK 0x0
4904 /*
4905  * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_SDMMC
4906  *
4907  * main_nand_sdmmc_clk
4908  */
4909 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK 0x1
4910 /*
4911  * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_SDMMC
4912  *
4913  * periph_nand_sdmmc_clk
4914  */
4915 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK 0x2
4916 
4917 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_SRC_SDMMC register field. */
4918 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_LSB 0
4919 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_SRC_SDMMC register field. */
4920 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_MSB 1
4921 /* The width in bits of the ALT_CLKMGR_PERPLL_SRC_SDMMC register field. */
4922 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_WIDTH 2
4923 /* The mask used to set the ALT_CLKMGR_PERPLL_SRC_SDMMC register field value. */
4924 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_SET_MSK 0x00000003
4925 /* The mask used to clear the ALT_CLKMGR_PERPLL_SRC_SDMMC register field value. */
4926 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_CLR_MSK 0xfffffffc
4927 /* The reset value of the ALT_CLKMGR_PERPLL_SRC_SDMMC register field. */
4928 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_RESET 0x1
4929 /* Extracts the ALT_CLKMGR_PERPLL_SRC_SDMMC field value from a register. */
4930 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(value) (((value) & 0x00000003) >> 0)
4931 /* Produces a ALT_CLKMGR_PERPLL_SRC_SDMMC register field value suitable for setting the register. */
4932 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_SET(value) (((value) << 0) & 0x00000003)
4933 
4934 /*
4935  * Field : NAND Clock Source - nand
4936  *
4937  * Selects the source clock for the NAND.
4938  *
4939  * Qsys and user documenation refer to f2s_periph_ref_clk as f2h_periph_ref_clk.
4940  *
4941  * Field Enumeration Values:
4942  *
4943  * Enum | Value | Description
4944  * :------------------------------------------------|:------|:----------------------
4945  * ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK | 0x0 | f2s_periph_ref_clk
4946  * ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK | 0x1 | main_nand_sdmmc_clk
4947  * ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK | 0x2 | periph_nand_sdmmc_clk
4948  *
4949  * Field Access Macros:
4950  *
4951  */
4952 /*
4953  * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_NAND
4954  *
4955  * f2s_periph_ref_clk
4956  */
4957 #define ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK 0x0
4958 /*
4959  * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_NAND
4960  *
4961  * main_nand_sdmmc_clk
4962  */
4963 #define ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK 0x1
4964 /*
4965  * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_NAND
4966  *
4967  * periph_nand_sdmmc_clk
4968  */
4969 #define ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK 0x2
4970 
4971 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_SRC_NAND register field. */
4972 #define ALT_CLKMGR_PERPLL_SRC_NAND_LSB 2
4973 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_SRC_NAND register field. */
4974 #define ALT_CLKMGR_PERPLL_SRC_NAND_MSB 3
4975 /* The width in bits of the ALT_CLKMGR_PERPLL_SRC_NAND register field. */
4976 #define ALT_CLKMGR_PERPLL_SRC_NAND_WIDTH 2
4977 /* The mask used to set the ALT_CLKMGR_PERPLL_SRC_NAND register field value. */
4978 #define ALT_CLKMGR_PERPLL_SRC_NAND_SET_MSK 0x0000000c
4979 /* The mask used to clear the ALT_CLKMGR_PERPLL_SRC_NAND register field value. */
4980 #define ALT_CLKMGR_PERPLL_SRC_NAND_CLR_MSK 0xfffffff3
4981 /* The reset value of the ALT_CLKMGR_PERPLL_SRC_NAND register field. */
4982 #define ALT_CLKMGR_PERPLL_SRC_NAND_RESET 0x1
4983 /* Extracts the ALT_CLKMGR_PERPLL_SRC_NAND field value from a register. */
4984 #define ALT_CLKMGR_PERPLL_SRC_NAND_GET(value) (((value) & 0x0000000c) >> 2)
4985 /* Produces a ALT_CLKMGR_PERPLL_SRC_NAND register field value suitable for setting the register. */
4986 #define ALT_CLKMGR_PERPLL_SRC_NAND_SET(value) (((value) << 2) & 0x0000000c)
4987 
4988 /*
4989  * Field : QSPI Clock Source - qspi
4990  *
4991  * Selects the source clock for the QSPI.
4992  *
4993  * Qsys and user documenation refer to f2s_periph_ref_clk as f2h_periph_ref_clk.
4994  *
4995  * Field Enumeration Values:
4996  *
4997  * Enum | Value | Description
4998  * :------------------------------------------------|:------|:-------------------
4999  * ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK | 0x0 | f2s_periph_ref_clk
5000  * ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK | 0x1 | main_qspi_clk
5001  * ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK | 0x2 | periph_qspi_clk
5002  *
5003  * Field Access Macros:
5004  *
5005  */
5006 /*
5007  * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_QSPI
5008  *
5009  * f2s_periph_ref_clk
5010  */
5011 #define ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK 0x0
5012 /*
5013  * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_QSPI
5014  *
5015  * main_qspi_clk
5016  */
5017 #define ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK 0x1
5018 /*
5019  * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_QSPI
5020  *
5021  * periph_qspi_clk
5022  */
5023 #define ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK 0x2
5024 
5025 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_SRC_QSPI register field. */
5026 #define ALT_CLKMGR_PERPLL_SRC_QSPI_LSB 4
5027 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_SRC_QSPI register field. */
5028 #define ALT_CLKMGR_PERPLL_SRC_QSPI_MSB 5
5029 /* The width in bits of the ALT_CLKMGR_PERPLL_SRC_QSPI register field. */
5030 #define ALT_CLKMGR_PERPLL_SRC_QSPI_WIDTH 2
5031 /* The mask used to set the ALT_CLKMGR_PERPLL_SRC_QSPI register field value. */
5032 #define ALT_CLKMGR_PERPLL_SRC_QSPI_SET_MSK 0x00000030
5033 /* The mask used to clear the ALT_CLKMGR_PERPLL_SRC_QSPI register field value. */
5034 #define ALT_CLKMGR_PERPLL_SRC_QSPI_CLR_MSK 0xffffffcf
5035 /* The reset value of the ALT_CLKMGR_PERPLL_SRC_QSPI register field. */
5036 #define ALT_CLKMGR_PERPLL_SRC_QSPI_RESET 0x1
5037 /* Extracts the ALT_CLKMGR_PERPLL_SRC_QSPI field value from a register. */
5038 #define ALT_CLKMGR_PERPLL_SRC_QSPI_GET(value) (((value) & 0x00000030) >> 4)
5039 /* Produces a ALT_CLKMGR_PERPLL_SRC_QSPI register field value suitable for setting the register. */
5040 #define ALT_CLKMGR_PERPLL_SRC_QSPI_SET(value) (((value) << 4) & 0x00000030)
5041 
5042 #ifndef __ASSEMBLY__
5043 /*
5044  * WARNING: The C register and register group struct declarations are provided for
5045  * convenience and illustrative purposes. They should, however, be used with
5046  * caution as the C language standard provides no guarantees about the alignment or
5047  * atomicity of device memory accesses. The recommended practice for writing
5048  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5049  * alt_write_word() functions.
5050  *
5051  * The struct declaration for register ALT_CLKMGR_PERPLL_SRC.
5052  */
5054 {
5055  uint32_t sdmmc : 2; /* SDMMC Clock Source */
5056  uint32_t nand : 2; /* NAND Clock Source */
5057  uint32_t qspi : 2; /* QSPI Clock Source */
5058  uint32_t : 26; /* *UNDEFINED* */
5059 };
5060 
5061 /* The typedef declaration for register ALT_CLKMGR_PERPLL_SRC. */
5062 typedef volatile struct ALT_CLKMGR_PERPLL_SRC_s ALT_CLKMGR_PERPLL_SRC_t;
5063 #endif /* __ASSEMBLY__ */
5064 
5065 /* The byte offset of the ALT_CLKMGR_PERPLL_SRC register from the beginning of the component. */
5066 #define ALT_CLKMGR_PERPLL_SRC_OFST 0x2c
5067 
5068 /*
5069  * Register : Peripheral PLL Output Counter Reset Ack Status Register - stat
5070  *
5071  * Contains Output Clock Counter Reset acknowledge status.
5072  *
5073  * Register Layout
5074  *
5075  * Bits | Access | Reset | Description
5076  * :-------|:-------|:------|:---------------------------------
5077  * [5:0] | R | 0x0 | Output Counter Reset Acknowledge
5078  * [31:6] | ??? | 0x0 | *UNDEFINED*
5079  *
5080  */
5081 /*
5082  * Field : Output Counter Reset Acknowledge - outresetack
5083  *
5084  * These read only bits per PLL output indicate that the PLL has received the
5085  * Output Reset Counter request and has gracefully stopped the respective PLL
5086  * output clock.
5087  *
5088  * For software to change the PLL output counter without producing glitches on the
5089  * respective clock, SW must set the VCO register respective Output Counter Reset
5090  * bit. Software then polls the respective Output Counter Reset Acknowledge bit in
5091  * the Output Counter Reset Ack Status Register. Software then writes the
5092  * appropriate counter register, and then clears the respective VCO register Output
5093  * Counter Reset bit.
5094  *
5095  * The reset value of this bit is applied on a cold reset; warm reset has no affect
5096  * on this bit.
5097  *
5098  * Field Enumeration Values:
5099  *
5100  * Enum | Value | Description
5101  * :-------------------------------------------|:------|:-------------------------------------
5102  * ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_E_IDLE | 0x0 | Idle
5103  * ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_E_ACK_RXD | 0x1 | Output Counter Acknowledge received.
5104  *
5105  * Field Access Macros:
5106  *
5107  */
5108 /*
5109  * Enumerated value for register field ALT_CLKMGR_PERPLL_STAT_OUTRSTACK
5110  *
5111  * Idle
5112  */
5113 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_E_IDLE 0x0
5114 /*
5115  * Enumerated value for register field ALT_CLKMGR_PERPLL_STAT_OUTRSTACK
5116  *
5117  * Output Counter Acknowledge received.
5118  */
5119 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_E_ACK_RXD 0x1
5120 
5121 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field. */
5122 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_LSB 0
5123 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field. */
5124 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_MSB 5
5125 /* The width in bits of the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field. */
5126 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_WIDTH 6
5127 /* The mask used to set the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field value. */
5128 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_SET_MSK 0x0000003f
5129 /* The mask used to clear the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field value. */
5130 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_CLR_MSK 0xffffffc0
5131 /* The reset value of the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field. */
5132 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_RESET 0x0
5133 /* Extracts the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK field value from a register. */
5134 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_GET(value) (((value) & 0x0000003f) >> 0)
5135 /* Produces a ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field value suitable for setting the register. */
5136 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_SET(value) (((value) << 0) & 0x0000003f)
5137 
5138 #ifndef __ASSEMBLY__
5139 /*
5140  * WARNING: The C register and register group struct declarations are provided for
5141  * convenience and illustrative purposes. They should, however, be used with
5142  * caution as the C language standard provides no guarantees about the alignment or
5143  * atomicity of device memory accesses. The recommended practice for writing
5144  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5145  * alt_write_word() functions.
5146  *
5147  * The struct declaration for register ALT_CLKMGR_PERPLL_STAT.
5148  */
5150 {
5151  const uint32_t outresetack : 6; /* Output Counter Reset Acknowledge */
5152  uint32_t : 26; /* *UNDEFINED* */
5153 };
5154 
5155 /* The typedef declaration for register ALT_CLKMGR_PERPLL_STAT. */
5156 typedef volatile struct ALT_CLKMGR_PERPLL_STAT_s ALT_CLKMGR_PERPLL_STAT_t;
5157 #endif /* __ASSEMBLY__ */
5158 
5159 /* The byte offset of the ALT_CLKMGR_PERPLL_STAT register from the beginning of the component. */
5160 #define ALT_CLKMGR_PERPLL_STAT_OFST 0x30
5161 
5162 #ifndef __ASSEMBLY__
5163 /*
5164  * WARNING: The C register and register group struct declarations are provided for
5165  * convenience and illustrative purposes. They should, however, be used with
5166  * caution as the C language standard provides no guarantees about the alignment or
5167  * atomicity of device memory accesses. The recommended practice for writing
5168  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5169  * alt_write_word() functions.
5170  *
5171  * The struct declaration for register group ALT_CLKMGR_PERPLL.
5172  */
5174 {
5175  volatile ALT_CLKMGR_PERPLL_VCO_t vco; /* ALT_CLKMGR_PERPLL_VCO */
5176  volatile ALT_CLKMGR_PERPLL_MISC_t misc; /* ALT_CLKMGR_PERPLL_MISC */
5177  volatile ALT_CLKMGR_PERPLL_EMAC0CLK_t emac0clk; /* ALT_CLKMGR_PERPLL_EMAC0CLK */
5178  volatile ALT_CLKMGR_PERPLL_EMAC1CLK_t emac1clk; /* ALT_CLKMGR_PERPLL_EMAC1CLK */
5179  volatile ALT_CLKMGR_PERPLL_PERQSPICLK_t perqspiclk; /* ALT_CLKMGR_PERPLL_PERQSPICLK */
5180  volatile ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_t pernandsdmmcclk; /* ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK */
5181  volatile ALT_CLKMGR_PERPLL_PERBASECLK_t perbaseclk; /* ALT_CLKMGR_PERPLL_PERBASECLK */
5182  volatile ALT_CLKMGR_PERPLL_S2FUSER1CLK_t s2fuser1clk; /* ALT_CLKMGR_PERPLL_S2FUSER1CLK */
5183  volatile ALT_CLKMGR_PERPLL_EN_t en; /* ALT_CLKMGR_PERPLL_EN */
5184  volatile ALT_CLKMGR_PERPLL_DIV_t div; /* ALT_CLKMGR_PERPLL_DIV */
5185  volatile ALT_CLKMGR_PERPLL_GPIODIV_t gpiodiv; /* ALT_CLKMGR_PERPLL_GPIODIV */
5186  volatile ALT_CLKMGR_PERPLL_SRC_t src; /* ALT_CLKMGR_PERPLL_SRC */
5187  volatile ALT_CLKMGR_PERPLL_STAT_t stat; /* ALT_CLKMGR_PERPLL_STAT */
5188  volatile uint32_t _pad_0x34_0x40[3]; /* *UNDEFINED* */
5189 };
5190 
5191 /* The typedef declaration for register group ALT_CLKMGR_PERPLL. */
5192 typedef volatile struct ALT_CLKMGR_PERPLL_s ALT_CLKMGR_PERPLL_t;
5193 /* The struct declaration for the raw register contents of register group ALT_CLKMGR_PERPLL. */
5195 {
5196  volatile uint32_t vco; /* ALT_CLKMGR_PERPLL_VCO */
5197  volatile uint32_t misc; /* ALT_CLKMGR_PERPLL_MISC */
5198  volatile uint32_t emac0clk; /* ALT_CLKMGR_PERPLL_EMAC0CLK */
5199  volatile uint32_t emac1clk; /* ALT_CLKMGR_PERPLL_EMAC1CLK */
5200  volatile uint32_t perqspiclk; /* ALT_CLKMGR_PERPLL_PERQSPICLK */
5201  volatile uint32_t pernandsdmmcclk; /* ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK */
5202  volatile uint32_t perbaseclk; /* ALT_CLKMGR_PERPLL_PERBASECLK */
5203  volatile uint32_t s2fuser1clk; /* ALT_CLKMGR_PERPLL_S2FUSER1CLK */
5204  volatile uint32_t en; /* ALT_CLKMGR_PERPLL_EN */
5205  volatile uint32_t div; /* ALT_CLKMGR_PERPLL_DIV */
5206  volatile uint32_t gpiodiv; /* ALT_CLKMGR_PERPLL_GPIODIV */
5207  volatile uint32_t src; /* ALT_CLKMGR_PERPLL_SRC */
5208  volatile uint32_t stat; /* ALT_CLKMGR_PERPLL_STAT */
5209  volatile uint32_t _pad_0x34_0x40[3]; /* *UNDEFINED* */
5210 };
5211 
5212 /* The typedef declaration for the raw register contents of register group ALT_CLKMGR_PERPLL. */
5213 typedef volatile struct ALT_CLKMGR_PERPLL_raw_s ALT_CLKMGR_PERPLL_raw_t;
5214 #endif /* __ASSEMBLY__ */
5215 
5216 
5217 /*
5218  * Register Group : SDRAM PLL Group - ALT_CLKMGR_SDRPLL
5219  * SDRAM PLL Group
5220  *
5221  * Contains registers with settings for the SDRAM PLL.
5222  *
5223  */
5224 /*
5225  * Register : SDRAM PLL VCO Control Register - vco
5226  *
5227  * Contains settings that control the SDRAM PLL VCO. The VCO output frequency is
5228  * the input frequency multiplied by the numerator (M+1) and divided by the
5229  * denominator (N+1).
5230  *
5231  * Fields are only reset by a cold reset.
5232  *
5233  * Register Layout
5234  *
5235  * Bits | Access | Reset | Description
5236  * :--------|:-------|:------|:--------------------------------
5237  * [0] | RW | 0x1 | BG PWRDN
5238  * [1] | RW | 0x0 | Enable
5239  * [2] | RW | 0x1 | Power down
5240  * [15:3] | RW | 0x1 | Numerator (M)
5241  * [21:16] | RW | 0x1 | Denominator (N)
5242  * [23:22] | RW | 0x0 | Clock Source
5243  * [24] | RW | 0x0 | SDRAM All Output Counter Reset
5244  * [30:25] | RW | 0x0 | Output Counter Reset
5245  * [31] | RW | 0x1 | External Regulator Input Select
5246  *
5247  */
5248 /*
5249  * Field : BG PWRDN - bgpwrdn
5250  *
5251  * If '1', powers down bandgap. If '0', bandgap is not power down.
5252  *
5253  * Field Access Macros:
5254  *
5255  */
5256 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field. */
5257 #define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_LSB 0
5258 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field. */
5259 #define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_MSB 0
5260 /* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field. */
5261 #define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_WIDTH 1
5262 /* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field value. */
5263 #define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_SET_MSK 0x00000001
5264 /* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field value. */
5265 #define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_CLR_MSK 0xfffffffe
5266 /* The reset value of the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field. */
5267 #define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_RESET 0x1
5268 /* Extracts the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN field value from a register. */
5269 #define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0)
5270 /* Produces a ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field value suitable for setting the register. */
5271 #define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_SET(value) (((value) << 0) & 0x00000001)
5272 
5273 /*
5274  * Field : Enable - en
5275  *
5276  * If '1', VCO is enabled. If '0', VCO is in reset.
5277  *
5278  * Field Access Macros:
5279  *
5280  */
5281 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_EN register field. */
5282 #define ALT_CLKMGR_SDRPLL_VCO_EN_LSB 1
5283 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_EN register field. */
5284 #define ALT_CLKMGR_SDRPLL_VCO_EN_MSB 1
5285 /* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_EN register field. */
5286 #define ALT_CLKMGR_SDRPLL_VCO_EN_WIDTH 1
5287 /* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_EN register field value. */
5288 #define ALT_CLKMGR_SDRPLL_VCO_EN_SET_MSK 0x00000002
5289 /* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_EN register field value. */
5290 #define ALT_CLKMGR_SDRPLL_VCO_EN_CLR_MSK 0xfffffffd
5291 /* The reset value of the ALT_CLKMGR_SDRPLL_VCO_EN register field. */
5292 #define ALT_CLKMGR_SDRPLL_VCO_EN_RESET 0x0
5293 /* Extracts the ALT_CLKMGR_SDRPLL_VCO_EN field value from a register. */
5294 #define ALT_CLKMGR_SDRPLL_VCO_EN_GET(value) (((value) & 0x00000002) >> 1)
5295 /* Produces a ALT_CLKMGR_SDRPLL_VCO_EN register field value suitable for setting the register. */
5296 #define ALT_CLKMGR_SDRPLL_VCO_EN_SET(value) (((value) << 1) & 0x00000002)
5297 
5298 /*
5299  * Field : Power down - pwrdn
5300  *
5301  * If '1', power down analog circuitry. If '0', analog circuitry not powered down.
5302  *
5303  * Field Access Macros:
5304  *
5305  */
5306 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field. */
5307 #define ALT_CLKMGR_SDRPLL_VCO_PWRDN_LSB 2
5308 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field. */
5309 #define ALT_CLKMGR_SDRPLL_VCO_PWRDN_MSB 2
5310 /* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field. */
5311 #define ALT_CLKMGR_SDRPLL_VCO_PWRDN_WIDTH 1
5312 /* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field value. */
5313 #define ALT_CLKMGR_SDRPLL_VCO_PWRDN_SET_MSK 0x00000004
5314 /* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field value. */
5315 #define ALT_CLKMGR_SDRPLL_VCO_PWRDN_CLR_MSK 0xfffffffb
5316 /* The reset value of the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field. */
5317 #define ALT_CLKMGR_SDRPLL_VCO_PWRDN_RESET 0x1
5318 /* Extracts the ALT_CLKMGR_SDRPLL_VCO_PWRDN field value from a register. */
5319 #define ALT_CLKMGR_SDRPLL_VCO_PWRDN_GET(value) (((value) & 0x00000004) >> 2)
5320 /* Produces a ALT_CLKMGR_SDRPLL_VCO_PWRDN register field value suitable for setting the register. */
5321 #define ALT_CLKMGR_SDRPLL_VCO_PWRDN_SET(value) (((value) << 2) & 0x00000004)
5322 
5323 /*
5324  * Field : Numerator (M) - numer
5325  *
5326  * Numerator in VCO output frequency equation. For incremental frequency change, if
5327  * the new value lead to less than 20% of the frequency change, this value can be
5328  * changed without resetting the PLL. The Numerator and Denominator can not be
5329  * changed at the same time for incremental frequency changed.
5330  *
5331  * Field Access Macros:
5332  *
5333  */
5334 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_NUMER register field. */
5335 #define ALT_CLKMGR_SDRPLL_VCO_NUMER_LSB 3
5336 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_NUMER register field. */
5337 #define ALT_CLKMGR_SDRPLL_VCO_NUMER_MSB 15
5338 /* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_NUMER register field. */
5339 #define ALT_CLKMGR_SDRPLL_VCO_NUMER_WIDTH 13
5340 /* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_NUMER register field value. */
5341 #define ALT_CLKMGR_SDRPLL_VCO_NUMER_SET_MSK 0x0000fff8
5342 /* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_NUMER register field value. */
5343 #define ALT_CLKMGR_SDRPLL_VCO_NUMER_CLR_MSK 0xffff0007
5344 /* The reset value of the ALT_CLKMGR_SDRPLL_VCO_NUMER register field. */
5345 #define ALT_CLKMGR_SDRPLL_VCO_NUMER_RESET 0x1
5346 /* Extracts the ALT_CLKMGR_SDRPLL_VCO_NUMER field value from a register. */
5347 #define ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(value) (((value) & 0x0000fff8) >> 3)
5348 /* Produces a ALT_CLKMGR_SDRPLL_VCO_NUMER register field value suitable for setting the register. */
5349 #define ALT_CLKMGR_SDRPLL_VCO_NUMER_SET(value) (((value) << 3) & 0x0000fff8)
5350 
5351 /*
5352  * Field : Denominator (N) - denom
5353  *
5354  * Denominator in VCO output frequency equation. For incremental frequency change,
5355  * if the new value lead to less than 20% of the frequency change, this value can
5356  * be changed without resetting the PLL. The Numerator and Denominator can not be
5357  * changed at the same time for incremental frequency changed.
5358  *
5359  * Field Access Macros:
5360  *
5361  */
5362 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_DENOM register field. */
5363 #define ALT_CLKMGR_SDRPLL_VCO_DENOM_LSB 16
5364 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_DENOM register field. */
5365 #define ALT_CLKMGR_SDRPLL_VCO_DENOM_MSB 21
5366 /* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_DENOM register field. */
5367 #define ALT_CLKMGR_SDRPLL_VCO_DENOM_WIDTH 6
5368 /* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_DENOM register field value. */
5369 #define ALT_CLKMGR_SDRPLL_VCO_DENOM_SET_MSK 0x003f0000
5370 /* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_DENOM register field value. */
5371 #define ALT_CLKMGR_SDRPLL_VCO_DENOM_CLR_MSK 0xffc0ffff
5372 /* The reset value of the ALT_CLKMGR_SDRPLL_VCO_DENOM register field. */
5373 #define ALT_CLKMGR_SDRPLL_VCO_DENOM_RESET 0x1
5374 /* Extracts the ALT_CLKMGR_SDRPLL_VCO_DENOM field value from a register. */
5375 #define ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(value) (((value) & 0x003f0000) >> 16)
5376 /* Produces a ALT_CLKMGR_SDRPLL_VCO_DENOM register field value suitable for setting the register. */
5377 #define ALT_CLKMGR_SDRPLL_VCO_DENOM_SET(value) (((value) << 16) & 0x003f0000)
5378 
5379 /*
5380  * Field : Clock Source - ssrc
5381  *
5382  * Controls the VCO input clock source. The PLL must by bypassed to eosc1_clk
5383  * before changing this field.
5384  *
5385  * Qsys and user documenation refer to f2s_sdram_ref_clk as f2h_sdram_ref_clk.
5386  *
5387  * Field Enumeration Values:
5388  *
5389  * Enum | Value | Description
5390  * :-------------------------------------------|:------|:------------------
5391  * ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1 | 0x0 | eosc1_clk
5392  * ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2 | 0x1 | eosc2_clk
5393  * ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF | 0x2 | f2s_sdram_ref_clk
5394  *
5395  * Field Access Macros:
5396  *
5397  */
5398 /*
5399  * Enumerated value for register field ALT_CLKMGR_SDRPLL_VCO_SSRC
5400  *
5401  * eosc1_clk
5402  */
5403 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1 0x0
5404 /*
5405  * Enumerated value for register field ALT_CLKMGR_SDRPLL_VCO_SSRC
5406  *
5407  * eosc2_clk
5408  */
5409 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2 0x1
5410 /*
5411  * Enumerated value for register field ALT_CLKMGR_SDRPLL_VCO_SSRC
5412  *
5413  * f2s_sdram_ref_clk
5414  */
5415 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF 0x2
5416 
5417 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_SSRC register field. */
5418 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_LSB 22
5419 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_SSRC register field. */
5420 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_MSB 23
5421 /* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_SSRC register field. */
5422 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_WIDTH 2
5423 /* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_SSRC register field value. */
5424 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_SET_MSK 0x00c00000
5425 /* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_SSRC register field value. */
5426 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_CLR_MSK 0xff3fffff
5427 /* The reset value of the ALT_CLKMGR_SDRPLL_VCO_SSRC register field. */
5428 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_RESET 0x0
5429 /* Extracts the ALT_CLKMGR_SDRPLL_VCO_SSRC field value from a register. */
5430 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(value) (((value) & 0x00c00000) >> 22)
5431 /* Produces a ALT_CLKMGR_SDRPLL_VCO_SSRC register field value suitable for setting the register. */
5432 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(value) (((value) << 22) & 0x00c00000)
5433 
5434 /*
5435  * Field : SDRAM All Output Counter Reset - outresetall
5436  *
5437  * Before releasing Bypass, All Output Counter Reset must be set and cleared by
5438  * software for correct clock operation.
5439  *
5440  * If '1', Reset phase multiplexer and output counter state. So that after the
5441  * assertion all the clocks output are start from rising edge align.
5442  *
5443  * If '0', phase multiplexer and output counter state not reset and no change to
5444  * the phase of the clock outputs.
5445  *
5446  * Field Access Macros:
5447  *
5448  */
5449 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field. */
5450 #define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_LSB 24
5451 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field. */
5452 #define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_MSB 24
5453 /* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field. */
5454 #define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_WIDTH 1
5455 /* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field value. */
5456 #define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET_MSK 0x01000000
5457 /* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field value. */
5458 #define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_CLR_MSK 0xfeffffff
5459 /* The reset value of the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field. */
5460 #define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_RESET 0x0
5461 /* Extracts the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL field value from a register. */
5462 #define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_GET(value) (((value) & 0x01000000) >> 24)
5463 /* Produces a ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field value suitable for setting the register. */
5464 #define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET(value) (((value) << 24) & 0x01000000)
5465 
5466 /*
5467  * Field : Output Counter Reset - outreset
5468  *
5469  * Resets the individual PLL output counter.
5470  *
5471  * For software to change the PLL output counter without producing glitches on the
5472  * respective clock, SW must set the VCO register respective Output Counter Reset
5473  * bit. Software then polls the respective Output Counter Reset Acknowledge bit in
5474  * the Output Counter Reset Ack Status Register. Software then writes the
5475  * appropriate counter register, and then clears the respective VCO register Output
5476  * Counter Reset bit.
5477  *
5478  * LSB 'outreset[0]' corresponds to PLL output clock C0, etc.
5479  *
5480  * If set to '1', reset output divider, no clock output from counter.
5481  *
5482  * If set to '0', counter is not reset.
5483  *
5484  * The reset value of this bit is applied on a cold reset; warm reset has no affect
5485  * on this bit.
5486  *
5487  * Field Access Macros:
5488  *
5489  */
5490 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field. */
5491 #define ALT_CLKMGR_SDRPLL_VCO_OUTRST_LSB 25
5492 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field. */
5493 #define ALT_CLKMGR_SDRPLL_VCO_OUTRST_MSB 30
5494 /* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field. */
5495 #define ALT_CLKMGR_SDRPLL_VCO_OUTRST_WIDTH 6
5496 /* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field value. */
5497 #define ALT_CLKMGR_SDRPLL_VCO_OUTRST_SET_MSK 0x7e000000
5498 /* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field value. */
5499 #define ALT_CLKMGR_SDRPLL_VCO_OUTRST_CLR_MSK 0x81ffffff
5500 /* The reset value of the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field. */
5501 #define ALT_CLKMGR_SDRPLL_VCO_OUTRST_RESET 0x0
5502 /* Extracts the ALT_CLKMGR_SDRPLL_VCO_OUTRST field value from a register. */
5503 #define ALT_CLKMGR_SDRPLL_VCO_OUTRST_GET(value) (((value) & 0x7e000000) >> 25)
5504 /* Produces a ALT_CLKMGR_SDRPLL_VCO_OUTRST register field value suitable for setting the register. */
5505 #define ALT_CLKMGR_SDRPLL_VCO_OUTRST_SET(value) (((value) << 25) & 0x7e000000)
5506 
5507 /*
5508  * Field : External Regulator Input Select - regextsel
5509  *
5510  * If set to '1', the external regulator is selected for the PLL.
5511  *
5512  * If set to '0', the internal regulator is slected.
5513  *
5514  * It is strongly recommended to select the external regulator while the PLL is not
5515  * enabled (in reset), and then disable the external regulater once the PLL
5516  * becomes enabled. Software should simulateously update the 'Enable' bit and the
5517  * 'External Regulator Input Select' in the same write access to the VCO register.
5518  * When the 'Enable' bit is clear, the 'External Regulator Input Select' should be
5519  * set, and vice versa.
5520  *
5521  * The reset value of this bit is applied on a cold reset; warm reset has no affect
5522  * on this bit.
5523  *
5524  * Field Access Macros:
5525  *
5526  */
5527 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field. */
5528 #define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_LSB 31
5529 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field. */
5530 #define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_MSB 31
5531 /* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field. */
5532 #define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_WIDTH 1
5533 /* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field value. */
5534 #define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_SET_MSK 0x80000000
5535 /* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field value. */
5536 #define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_CLR_MSK 0x7fffffff
5537 /* The reset value of the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field. */
5538 #define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_RESET 0x1
5539 /* Extracts the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL field value from a register. */
5540 #define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_GET(value) (((value) & 0x80000000) >> 31)
5541 /* Produces a ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field value suitable for setting the register. */
5542 #define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_SET(value) (((value) << 31) & 0x80000000)
5543 
5544 #ifndef __ASSEMBLY__
5545 /*
5546  * WARNING: The C register and register group struct declarations are provided for
5547  * convenience and illustrative purposes. They should, however, be used with
5548  * caution as the C language standard provides no guarantees about the alignment or
5549  * atomicity of device memory accesses. The recommended practice for writing
5550  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5551  * alt_write_word() functions.
5552  *
5553  * The struct declaration for register ALT_CLKMGR_SDRPLL_VCO.
5554  */
5556 {
5557  uint32_t bgpwrdn : 1; /* BG PWRDN */
5558  uint32_t en : 1; /* Enable */
5559  uint32_t pwrdn : 1; /* Power down */
5560  uint32_t numer : 13; /* Numerator (M) */
5561  uint32_t denom : 6; /* Denominator (N) */
5562  uint32_t ssrc : 2; /* Clock Source */
5563  uint32_t outresetall : 1; /* SDRAM All Output Counter Reset */
5564  uint32_t outreset : 6; /* Output Counter Reset */
5565  uint32_t regextsel : 1; /* External Regulator Input Select */
5566 };
5567 
5568 /* The typedef declaration for register ALT_CLKMGR_SDRPLL_VCO. */
5569 typedef volatile struct ALT_CLKMGR_SDRPLL_VCO_s ALT_CLKMGR_SDRPLL_VCO_t;
5570 #endif /* __ASSEMBLY__ */
5571 
5572 /* The byte offset of the ALT_CLKMGR_SDRPLL_VCO register from the beginning of the component. */
5573 #define ALT_CLKMGR_SDRPLL_VCO_OFST 0x0
5574 
5575 /*
5576  * Register : SDRAM PLL VCO Advanced Control Register - ctrl
5577  *
5578  * Contains VCO control signals and other PLL control signals need to be
5579  * controllable through register.
5580  *
5581  * Fields are only reset by a cold reset.
5582  *
5583  * Register Layout
5584  *
5585  * Bits | Access | Reset | Description
5586  * :--------|:-------|:------|:------------------------------
5587  * [0] | RW | 0x0 | Loop Bandwidth Adjust Enabled
5588  * [12:1] | RW | 0x1 | Loop Bandwidth Adjust
5589  * [13] | RW | 0x0 | Fast Locking Enable
5590  * [14] | RW | 0x1 | Saturation Enable
5591  * [31:15] | ??? | 0x0 | *UNDEFINED*
5592  *
5593  */
5594 /*
5595  * Field : Loop Bandwidth Adjust Enabled - bwadjen
5596  *
5597  * If set to 1, the Loop Bandwidth Adjust value comes from the Loop Bandwidth
5598  * Adjust field.
5599  *
5600  * If set to 0, the Loop Bandwidth Adjust value equals the M field divided by 2
5601  * value of the VCO Control Register. The M divided by 2 is the upper 12 bits
5602  * (12:1) of the M field in the VCO register.
5603  *
5604  * Field Access Macros:
5605  *
5606  */
5607 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field. */
5608 #define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_LSB 0
5609 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field. */
5610 #define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_MSB 0
5611 /* The width in bits of the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field. */
5612 #define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_WIDTH 1
5613 /* The mask used to set the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field value. */
5614 #define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_SET_MSK 0x00000001
5615 /* The mask used to clear the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field value. */
5616 #define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_CLR_MSK 0xfffffffe
5617 /* The reset value of the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field. */
5618 #define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_RESET 0x0
5619 /* Extracts the ALT_CLKMGR_SDRPLL_CTL_BWADJEN field value from a register. */
5620 #define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_GET(value) (((value) & 0x00000001) >> 0)
5621 /* Produces a ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field value suitable for setting the register. */
5622 #define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_SET(value) (((value) << 0) & 0x00000001)
5623 
5624 /*
5625  * Field : Loop Bandwidth Adjust - bwadj
5626  *
5627  * Provides Loop Bandwidth Adjust value.
5628  *
5629  * Field Access Macros:
5630  *
5631  */
5632 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field. */
5633 #define ALT_CLKMGR_SDRPLL_CTL_BWADJ_LSB 1
5634 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field. */
5635 #define ALT_CLKMGR_SDRPLL_CTL_BWADJ_MSB 12
5636 /* The width in bits of the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field. */
5637 #define ALT_CLKMGR_SDRPLL_CTL_BWADJ_WIDTH 12
5638 /* The mask used to set the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field value. */
5639 #define ALT_CLKMGR_SDRPLL_CTL_BWADJ_SET_MSK 0x00001ffe
5640 /* The mask used to clear the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field value. */
5641 #define ALT_CLKMGR_SDRPLL_CTL_BWADJ_CLR_MSK 0xffffe001
5642 /* The reset value of the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field. */
5643 #define ALT_CLKMGR_SDRPLL_CTL_BWADJ_RESET 0x1
5644 /* Extracts the ALT_CLKMGR_SDRPLL_CTL_BWADJ field value from a register. */
5645 #define ALT_CLKMGR_SDRPLL_CTL_BWADJ_GET(value) (((value) & 0x00001ffe) >> 1)
5646 /* Produces a ALT_CLKMGR_SDRPLL_CTL_BWADJ register field value suitable for setting the register. */
5647 #define ALT_CLKMGR_SDRPLL_CTL_BWADJ_SET(value) (((value) << 1) & 0x00001ffe)
5648 
5649 /*
5650  * Field : Fast Locking Enable - fasten
5651  *
5652  * Enables fast locking circuit.
5653  *
5654  * Field Access Macros:
5655  *
5656  */
5657 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field. */
5658 #define ALT_CLKMGR_SDRPLL_CTL_FASTEN_LSB 13
5659 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field. */
5660 #define ALT_CLKMGR_SDRPLL_CTL_FASTEN_MSB 13
5661 /* The width in bits of the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field. */
5662 #define ALT_CLKMGR_SDRPLL_CTL_FASTEN_WIDTH 1
5663 /* The mask used to set the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field value. */
5664 #define ALT_CLKMGR_SDRPLL_CTL_FASTEN_SET_MSK 0x00002000
5665 /* The mask used to clear the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field value. */
5666 #define ALT_CLKMGR_SDRPLL_CTL_FASTEN_CLR_MSK 0xffffdfff
5667 /* The reset value of the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field. */
5668 #define ALT_CLKMGR_SDRPLL_CTL_FASTEN_RESET 0x0
5669 /* Extracts the ALT_CLKMGR_SDRPLL_CTL_FASTEN field value from a register. */
5670 #define ALT_CLKMGR_SDRPLL_CTL_FASTEN_GET(value) (((value) & 0x00002000) >> 13)
5671 /* Produces a ALT_CLKMGR_SDRPLL_CTL_FASTEN register field value suitable for setting the register. */
5672 #define ALT_CLKMGR_SDRPLL_CTL_FASTEN_SET(value) (((value) << 13) & 0x00002000)
5673 
5674 /*
5675  * Field : Saturation Enable - saten
5676  *
5677  * Enables saturation behavior.
5678  *
5679  * Field Access Macros:
5680  *
5681  */
5682 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_CTL_SATEN register field. */
5683 #define ALT_CLKMGR_SDRPLL_CTL_SATEN_LSB 14
5684 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_CTL_SATEN register field. */
5685 #define ALT_CLKMGR_SDRPLL_CTL_SATEN_MSB 14
5686 /* The width in bits of the ALT_CLKMGR_SDRPLL_CTL_SATEN register field. */
5687 #define ALT_CLKMGR_SDRPLL_CTL_SATEN_WIDTH 1
5688 /* The mask used to set the ALT_CLKMGR_SDRPLL_CTL_SATEN register field value. */
5689 #define ALT_CLKMGR_SDRPLL_CTL_SATEN_SET_MSK 0x00004000
5690 /* The mask used to clear the ALT_CLKMGR_SDRPLL_CTL_SATEN register field value. */
5691 #define ALT_CLKMGR_SDRPLL_CTL_SATEN_CLR_MSK 0xffffbfff
5692 /* The reset value of the ALT_CLKMGR_SDRPLL_CTL_SATEN register field. */
5693 #define ALT_CLKMGR_SDRPLL_CTL_SATEN_RESET 0x1
5694 /* Extracts the ALT_CLKMGR_SDRPLL_CTL_SATEN field value from a register. */
5695 #define ALT_CLKMGR_SDRPLL_CTL_SATEN_GET(value) (((value) & 0x00004000) >> 14)
5696 /* Produces a ALT_CLKMGR_SDRPLL_CTL_SATEN register field value suitable for setting the register. */
5697 #define ALT_CLKMGR_SDRPLL_CTL_SATEN_SET(value) (((value) << 14) & 0x00004000)
5698 
5699 #ifndef __ASSEMBLY__
5700 /*
5701  * WARNING: The C register and register group struct declarations are provided for
5702  * convenience and illustrative purposes. They should, however, be used with
5703  * caution as the C language standard provides no guarantees about the alignment or
5704  * atomicity of device memory accesses. The recommended practice for writing
5705  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5706  * alt_write_word() functions.
5707  *
5708  * The struct declaration for register ALT_CLKMGR_SDRPLL_CTL.
5709  */
5711 {
5712  uint32_t bwadjen : 1; /* Loop Bandwidth Adjust Enabled */
5713  uint32_t bwadj : 12; /* Loop Bandwidth Adjust */
5714  uint32_t fasten : 1; /* Fast Locking Enable */
5715  uint32_t saten : 1; /* Saturation Enable */
5716  uint32_t : 17; /* *UNDEFINED* */
5717 };
5718 
5719 /* The typedef declaration for register ALT_CLKMGR_SDRPLL_CTL. */
5720 typedef volatile struct ALT_CLKMGR_SDRPLL_CTL_s ALT_CLKMGR_SDRPLL_CTL_t;
5721 #endif /* __ASSEMBLY__ */
5722 
5723 /* The byte offset of the ALT_CLKMGR_SDRPLL_CTL register from the beginning of the component. */
5724 #define ALT_CLKMGR_SDRPLL_CTL_OFST 0x4
5725 
5726 /*
5727  * Register : SDRAM PLL C0 Control Register for Clock ddr_dqs_clk - ddrdqsclk
5728  *
5729  * Contains settings that control clock ddr_dqs_clk generated from the C0 output of
5730  * the SDRAM PLL.
5731  *
5732  * Fields are only reset by a cold reset.
5733  *
5734  * Register Layout
5735  *
5736  * Bits | Access | Reset | Description
5737  * :--------|:-------|:------|:------------
5738  * [8:0] | RW | 0x1 | Counter
5739  * [20:9] | RW | 0x0 | Phase Shift
5740  * [31:21] | ??? | 0x0 | *UNDEFINED*
5741  *
5742  */
5743 /*
5744  * Field : Counter - cnt
5745  *
5746  * Divides the VCO frequency by the value+1 in this field.
5747  *
5748  * Field Access Macros:
5749  *
5750  */
5751 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field. */
5752 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_LSB 0
5753 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field. */
5754 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_MSB 8
5755 /* The width in bits of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field. */
5756 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_WIDTH 9
5757 /* The mask used to set the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field value. */
5758 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET_MSK 0x000001ff
5759 /* The mask used to clear the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field value. */
5760 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_CLR_MSK 0xfffffe00
5761 /* The reset value of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field. */
5762 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_RESET 0x1
5763 /* Extracts the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT field value from a register. */
5764 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
5765 /* Produces a ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field value suitable for setting the register. */
5766 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
5767 
5768 /*
5769  * Field : Phase Shift - phase
5770  *
5771  * Increment the phase of the VCO output by the value in this field multiplied by
5772  * 45 degrees. The accumulated phase shift is the total shifted amount since the
5773  * last assertion of the 'SDRAM All Output Divider Reset' bit in the SDRAM vco
5774  * control register. In order to guarantee the phase shift to a known value, 'SDRAM
5775  * clocks output phase align' bit should be asserted before programming this field.
5776  *
5777  * This field is only writeable by SW when it is zero. HW updates this field in
5778  * real time as the phase adjustment is being made. SW may poll this field
5779  * waiting for zero indicating the phase adjustment has completed by HW.
5780  *
5781  * Field Access Macros:
5782  *
5783  */
5784 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field. */
5785 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_LSB 9
5786 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field. */
5787 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_MSB 20
5788 /* The width in bits of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field. */
5789 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_WIDTH 12
5790 /* The mask used to set the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field value. */
5791 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET_MSK 0x001ffe00
5792 /* The mask used to clear the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field value. */
5793 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_CLR_MSK 0xffe001ff
5794 /* The reset value of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field. */
5795 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_RESET 0x0
5796 /* Extracts the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE field value from a register. */
5797 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9)
5798 /* Produces a ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field value suitable for setting the register. */
5799 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00)
5800 
5801 #ifndef __ASSEMBLY__
5802 /*
5803  * WARNING: The C register and register group struct declarations are provided for
5804  * convenience and illustrative purposes. They should, however, be used with
5805  * caution as the C language standard provides no guarantees about the alignment or
5806  * atomicity of device memory accesses. The recommended practice for writing
5807  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5808  * alt_write_word() functions.
5809  *
5810  * The struct declaration for register ALT_CLKMGR_SDRPLL_DDRDQSCLK.
5811  */
5813 {
5814  uint32_t cnt : 9; /* Counter */
5815  uint32_t phase : 12; /* Phase Shift */
5816  uint32_t : 11; /* *UNDEFINED* */
5817 };
5818 
5819 /* The typedef declaration for register ALT_CLKMGR_SDRPLL_DDRDQSCLK. */
5820 typedef volatile struct ALT_CLKMGR_SDRPLL_DDRDQSCLK_s ALT_CLKMGR_SDRPLL_DDRDQSCLK_t;
5821 #endif /* __ASSEMBLY__ */
5822 
5823 /* The byte offset of the ALT_CLKMGR_SDRPLL_DDRDQSCLK register from the beginning of the component. */
5824 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_OFST 0x8
5825 
5826 /*
5827  * Register : SDRAM PLL C1 Control Register for Clock ddr_2x_dqs_clk - ddr2xdqsclk
5828  *
5829  * Contains settings that control clock ddr_2x_dqs_clk generated from the C1 output
5830  * of the SDRAM PLL.
5831  *
5832  * Fields are only reset by a cold reset.
5833  *
5834  * Register Layout
5835  *
5836  * Bits | Access | Reset | Description
5837  * :--------|:-------|:------|:------------
5838  * [8:0] | RW | 0x1 | Counter
5839  * [20:9] | RW | 0x0 | Phase Shift
5840  * [31:21] | ??? | 0x0 | *UNDEFINED*
5841  *
5842  */
5843 /*
5844  * Field : Counter - cnt
5845  *
5846  * Divides the VCO frequency by the value+1 in this field.
5847  *
5848  * Field Access Macros:
5849  *
5850  */
5851 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field. */
5852 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_LSB 0
5853 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field. */
5854 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_MSB 8
5855 /* The width in bits of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field. */
5856 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_WIDTH 9
5857 /* The mask used to set the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field value. */
5858 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET_MSK 0x000001ff
5859 /* The mask used to clear the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field value. */
5860 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_CLR_MSK 0xfffffe00
5861 /* The reset value of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field. */
5862 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_RESET 0x1
5863 /* Extracts the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT field value from a register. */
5864 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
5865 /* Produces a ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field value suitable for setting the register. */
5866 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
5867 
5868 /*
5869  * Field : Phase Shift - phase
5870  *
5871  * Increment the phase of the VCO output by the value in this field multiplied by
5872  * 45 degrees. The accumulated phase shift is the total shifted amount since the
5873  * last assertion of the 'SDRAM All Output Divider Reset' bit in the SDRAM vco
5874  * control register. In order to guarantee the phase shift to a known value, 'SDRAM
5875  * clocks output phase align' bit should be asserted before programming this field.
5876  *
5877  * This field is only writeable by SW when it is zero. HW updates this field in
5878  * real time as the phase adjustment is being made. SW may poll this field
5879  * waiting for zero indicating the phase adjustment has completed by HW.
5880  *
5881  * Field Access Macros:
5882  *
5883  */
5884 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field. */
5885 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_LSB 9
5886 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field. */
5887 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_MSB 20
5888 /* The width in bits of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field. */
5889 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_WIDTH 12
5890 /* The mask used to set the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field value. */
5891 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET_MSK 0x001ffe00
5892 /* The mask used to clear the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field value. */
5893 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_CLR_MSK 0xffe001ff
5894 /* The reset value of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field. */
5895 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_RESET 0x0
5896 /* Extracts the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE field value from a register. */
5897 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9)
5898 /* Produces a ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field value suitable for setting the register. */
5899 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00)
5900 
5901 #ifndef __ASSEMBLY__
5902 /*
5903  * WARNING: The C register and register group struct declarations are provided for
5904  * convenience and illustrative purposes. They should, however, be used with
5905  * caution as the C language standard provides no guarantees about the alignment or
5906  * atomicity of device memory accesses. The recommended practice for writing
5907  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5908  * alt_write_word() functions.
5909  *
5910  * The struct declaration for register ALT_CLKMGR_SDRPLL_DDR2XDQSCLK.
5911  */
5913 {
5914  uint32_t cnt : 9; /* Counter */
5915  uint32_t phase : 12; /* Phase Shift */
5916  uint32_t : 11; /* *UNDEFINED* */
5917 };
5918 
5919 /* The typedef declaration for register ALT_CLKMGR_SDRPLL_DDR2XDQSCLK. */
5920 typedef volatile struct ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_s ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_t;
5921 #endif /* __ASSEMBLY__ */
5922 
5923 /* The byte offset of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK register from the beginning of the component. */
5924 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_OFST 0xc
5925 
5926 /*
5927  * Register : SDRAM PLL C2 Control Register for Clock ddr_dq_clk - ddrdqclk
5928  *
5929  * Contains settings that control clock ddr_dq_clk generated from the C2 output of
5930  * the SDRAM PLL.
5931  *
5932  * Fields are only reset by a cold reset.
5933  *
5934  * Register Layout
5935  *
5936  * Bits | Access | Reset | Description
5937  * :--------|:-------|:------|:------------
5938  * [8:0] | RW | 0x1 | Counter
5939  * [20:9] | RW | 0x0 | Phase Shift
5940  * [31:21] | ??? | 0x0 | *UNDEFINED*
5941  *
5942  */
5943 /*
5944  * Field : Counter - cnt
5945  *
5946  * Divides the VCO frequency by the value+1 in this field.
5947  *
5948  * Field Access Macros:
5949  *
5950  */
5951 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field. */
5952 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_LSB 0
5953 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field. */
5954 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_MSB 8
5955 /* The width in bits of the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field. */
5956 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_WIDTH 9
5957 /* The mask used to set the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field value. */
5958 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET_MSK 0x000001ff
5959 /* The mask used to clear the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field value. */
5960 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_CLR_MSK 0xfffffe00
5961 /* The reset value of the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field. */
5962 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_RESET 0x1
5963 /* Extracts the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT field value from a register. */
5964 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
5965 /* Produces a ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field value suitable for setting the register. */
5966 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
5967 
5968 /*
5969  * Field : Phase Shift - phase
5970  *
5971  * Increment the phase of the VCO output by the value in this field multiplied by
5972  * 45 degrees. The accumulated phase shift is the total shifted amount since the
5973  * last assertion of the 'SDRAM All Output Divider Reset' bit in the SDRAM vco
5974  * control register. In order to guarantee the phase shift to a known value, 'SDRAM
5975  * clocks output phase align' bit should be asserted before programming this field.
5976  *
5977  * This field is only writeable by SW when it is zero. HW updates this field in
5978  * real time as the phase adjustment is being made. SW may poll this field
5979  * waiting for zero indicating the phase adjustment has completed by HW.
5980  *
5981  * Field Access Macros:
5982  *
5983  */
5984 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field. */
5985 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_LSB 9
5986 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field. */
5987 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_MSB 20
5988 /* The width in bits of the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field. */
5989 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_WIDTH 12
5990 /* The mask used to set the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field value. */
5991 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET_MSK 0x001ffe00
5992 /* The mask used to clear the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field value. */
5993 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_CLR_MSK 0xffe001ff
5994 /* The reset value of the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field. */
5995 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_RESET 0x0
5996 /* Extracts the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE field value from a register. */
5997 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9)
5998 /* Produces a ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field value suitable for setting the register. */
5999 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00)
6000 
6001 #ifndef __ASSEMBLY__
6002 /*
6003  * WARNING: The C register and register group struct declarations are provided for
6004  * convenience and illustrative purposes. They should, however, be used with
6005  * caution as the C language standard provides no guarantees about the alignment or
6006  * atomicity of device memory accesses. The recommended practice for writing
6007  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6008  * alt_write_word() functions.
6009  *
6010  * The struct declaration for register ALT_CLKMGR_SDRPLL_DDRDQCLK.
6011  */
6013 {
6014  uint32_t cnt : 9; /* Counter */
6015  uint32_t phase : 12; /* Phase Shift */
6016  uint32_t : 11; /* *UNDEFINED* */
6017 };
6018 
6019 /* The typedef declaration for register ALT_CLKMGR_SDRPLL_DDRDQCLK. */
6020 typedef volatile struct ALT_CLKMGR_SDRPLL_DDRDQCLK_s ALT_CLKMGR_SDRPLL_DDRDQCLK_t;
6021 #endif /* __ASSEMBLY__ */
6022 
6023 /* The byte offset of the ALT_CLKMGR_SDRPLL_DDRDQCLK register from the beginning of the component. */
6024 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_OFST 0x10
6025 
6026 /*
6027  * Register : SDRAM PLL C5 Control Register for Clock s2f_user2_clk - s2fuser2clk
6028  *
6029  * Contains settings that control clock s2f_user2_clk generated from the C5 output
6030  * of the SDRAM PLL.
6031  *
6032  * Qsys and user documenation refer to s2f_user2_clk as h2f_user2_clk
6033  *
6034  * Fields are only reset by a cold reset.
6035  *
6036  * Register Layout
6037  *
6038  * Bits | Access | Reset | Description
6039  * :--------|:-------|:------|:------------
6040  * [8:0] | RW | 0x1 | Counter
6041  * [20:9] | RW | 0x0 | Phase Shift
6042  * [31:21] | ??? | 0x0 | *UNDEFINED*
6043  *
6044  */
6045 /*
6046  * Field : Counter - cnt
6047  *
6048  * Divides the VCO frequency by the value+1 in this field.
6049  *
6050  * Field Access Macros:
6051  *
6052  */
6053 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field. */
6054 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_LSB 0
6055 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field. */
6056 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_MSB 8
6057 /* The width in bits of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field. */
6058 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_WIDTH 9
6059 /* The mask used to set the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field value. */
6060 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET_MSK 0x000001ff
6061 /* The mask used to clear the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field value. */
6062 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_CLR_MSK 0xfffffe00
6063 /* The reset value of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field. */
6064 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_RESET 0x1
6065 /* Extracts the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT field value from a register. */
6066 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
6067 /* Produces a ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field value suitable for setting the register. */
6068 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
6069 
6070 /*
6071  * Field : Phase Shift - phase
6072  *
6073  * Increment the phase of the VCO output by the value in this field multiplied by
6074  * 45 degrees. The accumulated phase shift is the total shifted amount since the
6075  * last assertion of the 'SDRAM All Output Divider Reset' bit in the SDRAM vco
6076  * control register. In order to guarantee the phase shift to a known value, 'SDRAM
6077  * clocks output phase align' bit should be asserted before programming this field.
6078  *
6079  * This field is only writeable by SW when it is zero. HW updates this field in
6080  * real time as the phase adjustment is being made. SW may poll this field
6081  * waiting for zero indicating the phase adjustment has completed by HW.
6082  *
6083  * Field Access Macros:
6084  *
6085  */
6086 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field. */
6087 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_LSB 9
6088 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field. */
6089 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_MSB 20
6090 /* The width in bits of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field. */
6091 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_WIDTH 12
6092 /* The mask used to set the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field value. */
6093 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET_MSK 0x001ffe00
6094 /* The mask used to clear the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field value. */
6095 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_CLR_MSK 0xffe001ff
6096 /* The reset value of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field. */
6097 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_RESET 0x0
6098 /* Extracts the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE field value from a register. */
6099 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9)
6100 /* Produces a ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field value suitable for setting the register. */
6101 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00)
6102 
6103 #ifndef __ASSEMBLY__
6104 /*
6105  * WARNING: The C register and register group struct declarations are provided for
6106  * convenience and illustrative purposes. They should, however, be used with
6107  * caution as the C language standard provides no guarantees about the alignment or
6108  * atomicity of device memory accesses. The recommended practice for writing
6109  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6110  * alt_write_word() functions.
6111  *
6112  * The struct declaration for register ALT_CLKMGR_SDRPLL_S2FUSER2CLK.
6113  */
6115 {
6116  uint32_t cnt : 9; /* Counter */
6117  uint32_t phase : 12; /* Phase Shift */
6118  uint32_t : 11; /* *UNDEFINED* */
6119 };
6120 
6121 /* The typedef declaration for register ALT_CLKMGR_SDRPLL_S2FUSER2CLK. */
6122 typedef volatile struct ALT_CLKMGR_SDRPLL_S2FUSER2CLK_s ALT_CLKMGR_SDRPLL_S2FUSER2CLK_t;
6123 #endif /* __ASSEMBLY__ */
6124 
6125 /* The byte offset of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK register from the beginning of the component. */
6126 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_OFST 0x14
6127 
6128 /*
6129  * Register : Enable Register - en
6130  *
6131  * Contains fields that control the SDRAM Clock Group enables generated from the
6132  * SDRAM PLL clock outputs.
6133  *
6134  * 1: The clock is enabled.
6135  *
6136  * 0: The clock is disabled.
6137  *
6138  * Fields are only reset by a cold reset.
6139  *
6140  * Register Layout
6141  *
6142  * Bits | Access | Reset | Description
6143  * :-------|:-------|:------|:----------------------
6144  * [0] | RW | 0x1 | ddr_dqs_clk Enable
6145  * [1] | RW | 0x1 | ddr_2x_dqs_clk Enable
6146  * [2] | RW | 0x1 | ddr_dq_clk Enable
6147  * [3] | RW | 0x1 | s2f_user2_clk Enable
6148  * [31:4] | ??? | 0x0 | *UNDEFINED*
6149  *
6150  */
6151 /*
6152  * Field : ddr_dqs_clk Enable - ddrdqsclk
6153  *
6154  * Enables clock ddr_dqs_clk output
6155  *
6156  * Field Access Macros:
6157  *
6158  */
6159 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field. */
6160 #define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_LSB 0
6161 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field. */
6162 #define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_MSB 0
6163 /* The width in bits of the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field. */
6164 #define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_WIDTH 1
6165 /* The mask used to set the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field value. */
6166 #define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK 0x00000001
6167 /* The mask used to clear the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field value. */
6168 #define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_CLR_MSK 0xfffffffe
6169 /* The reset value of the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field. */
6170 #define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_RESET 0x1
6171 /* Extracts the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK field value from a register. */
6172 #define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_GET(value) (((value) & 0x00000001) >> 0)
6173 /* Produces a ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field value suitable for setting the register. */
6174 #define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET(value) (((value) << 0) & 0x00000001)
6175 
6176 /*
6177  * Field : ddr_2x_dqs_clk Enable - ddr2xdqsclk
6178  *
6179  * Enables clock ddr_2x_dqs_clk output
6180  *
6181  * Field Access Macros:
6182  *
6183  */
6184 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field. */
6185 #define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_LSB 1
6186 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field. */
6187 #define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_MSB 1
6188 /* The width in bits of the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field. */
6189 #define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_WIDTH 1
6190 /* The mask used to set the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field value. */
6191 #define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK 0x00000002
6192 /* The mask used to clear the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field value. */
6193 #define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_CLR_MSK 0xfffffffd
6194 /* The reset value of the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field. */
6195 #define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_RESET 0x1
6196 /* Extracts the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK field value from a register. */
6197 #define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_GET(value) (((value) & 0x00000002) >> 1)
6198 /* Produces a ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field value suitable for setting the register. */
6199 #define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET(value) (((value) << 1) & 0x00000002)
6200 
6201 /*
6202  * Field : ddr_dq_clk Enable - ddrdqclk
6203  *
6204  * Enables clock ddr_dq_clk output
6205  *
6206  * Field Access Macros:
6207  *
6208  */
6209 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field. */
6210 #define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_LSB 2
6211 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field. */
6212 #define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_MSB 2
6213 /* The width in bits of the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field. */
6214 #define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_WIDTH 1
6215 /* The mask used to set the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field value. */
6216 #define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK 0x00000004
6217 /* The mask used to clear the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field value. */
6218 #define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_CLR_MSK 0xfffffffb
6219 /* The reset value of the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field. */
6220 #define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_RESET 0x1
6221 /* Extracts the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK field value from a register. */
6222 #define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_GET(value) (((value) & 0x00000004) >> 2)
6223 /* Produces a ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field value suitable for setting the register. */
6224 #define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET(value) (((value) << 2) & 0x00000004)
6225 
6226 /*
6227  * Field : s2f_user2_clk Enable - s2fuser2clk
6228  *
6229  * Enables clock s2f_user2_clk output.
6230  *
6231  * Qsys and user documenation refer to s2f_user2_clk as h2f_user2_clk.
6232  *
6233  * Field Access Macros:
6234  *
6235  */
6236 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field. */
6237 #define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_LSB 3
6238 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field. */
6239 #define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_MSB 3
6240 /* The width in bits of the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field. */
6241 #define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_WIDTH 1
6242 /* The mask used to set the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field value. */
6243 #define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK 0x00000008
6244 /* The mask used to clear the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field value. */
6245 #define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_CLR_MSK 0xfffffff7
6246 /* The reset value of the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field. */
6247 #define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_RESET 0x1
6248 /* Extracts the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK field value from a register. */
6249 #define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_GET(value) (((value) & 0x00000008) >> 3)
6250 /* Produces a ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field value suitable for setting the register. */
6251 #define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET(value) (((value) << 3) & 0x00000008)
6252 
6253 #ifndef __ASSEMBLY__
6254 /*
6255  * WARNING: The C register and register group struct declarations are provided for
6256  * convenience and illustrative purposes. They should, however, be used with
6257  * caution as the C language standard provides no guarantees about the alignment or
6258  * atomicity of device memory accesses. The recommended practice for writing
6259  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6260  * alt_write_word() functions.
6261  *
6262  * The struct declaration for register ALT_CLKMGR_SDRPLL_EN.
6263  */
6265 {
6266  uint32_t ddrdqsclk : 1; /* ddr_dqs_clk Enable */
6267  uint32_t ddr2xdqsclk : 1; /* ddr_2x_dqs_clk Enable */
6268  uint32_t ddrdqclk : 1; /* ddr_dq_clk Enable */
6269  uint32_t s2fuser2clk : 1; /* s2f_user2_clk Enable */
6270  uint32_t : 28; /* *UNDEFINED* */
6271 };
6272 
6273 /* The typedef declaration for register ALT_CLKMGR_SDRPLL_EN. */
6274 typedef volatile struct ALT_CLKMGR_SDRPLL_EN_s ALT_CLKMGR_SDRPLL_EN_t;
6275 #endif /* __ASSEMBLY__ */
6276 
6277 /* The byte offset of the ALT_CLKMGR_SDRPLL_EN register from the beginning of the component. */
6278 #define ALT_CLKMGR_SDRPLL_EN_OFST 0x18
6279 
6280 /*
6281  * Register : SDRAM PLL Output Counter Reset Ack Status Register - stat
6282  *
6283  * Contains Output Clock Counter Reset acknowledge status.
6284  *
6285  * Register Layout
6286  *
6287  * Bits | Access | Reset | Description
6288  * :-------|:-------|:------|:---------------------------------
6289  * [5:0] | R | 0x0 | Output Counter Reset Acknowledge
6290  * [31:6] | ??? | 0x0 | *UNDEFINED*
6291  *
6292  */
6293 /*
6294  * Field : Output Counter Reset Acknowledge - outresetack
6295  *
6296  * These read only bits per PLL output indicate that the PLL has received the
6297  * Output Reset Counter request and has gracefully stopped the respective PLL
6298  * output clock.
6299  *
6300  * For software to change the PLL output counter without producing glitches on the
6301  * respective clock, SW must set the VCO register respective Output Counter Reset
6302  * bit. Software then polls the respective Output Counter Reset Acknowledge bit in
6303  * the Output Counter Reset Ack Status Register. Software then writes the
6304  * appropriate counter register, and then clears the respective VCO register Output
6305  * Counter Reset bit.
6306  *
6307  * The reset value of this bit is applied on a cold reset; warm reset has no affect
6308  * on this bit.
6309  *
6310  * Field Enumeration Values:
6311  *
6312  * Enum | Value | Description
6313  * :-------------------------------------------|:------|:-------------------------------------
6314  * ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_E_IDLE | 0x0 | Idle
6315  * ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_E_ACK_RXD | 0x1 | Output Counter Acknowledge received.
6316  *
6317  * Field Access Macros:
6318  *
6319  */
6320 /*
6321  * Enumerated value for register field ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK
6322  *
6323  * Idle
6324  */
6325 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_E_IDLE 0x0
6326 /*
6327  * Enumerated value for register field ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK
6328  *
6329  * Output Counter Acknowledge received.
6330  */
6331 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_E_ACK_RXD 0x1
6332 
6333 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field. */
6334 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_LSB 0
6335 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field. */
6336 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_MSB 5
6337 /* The width in bits of the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field. */
6338 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_WIDTH 6
6339 /* The mask used to set the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field value. */
6340 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_SET_MSK 0x0000003f
6341 /* The mask used to clear the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field value. */
6342 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_CLR_MSK 0xffffffc0
6343 /* The reset value of the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field. */
6344 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_RESET 0x0
6345 /* Extracts the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK field value from a register. */
6346 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_GET(value) (((value) & 0x0000003f) >> 0)
6347 /* Produces a ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field value suitable for setting the register. */
6348 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_SET(value) (((value) << 0) & 0x0000003f)
6349 
6350 #ifndef __ASSEMBLY__
6351 /*
6352  * WARNING: The C register and register group struct declarations are provided for
6353  * convenience and illustrative purposes. They should, however, be used with
6354  * caution as the C language standard provides no guarantees about the alignment or
6355  * atomicity of device memory accesses. The recommended practice for writing
6356  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6357  * alt_write_word() functions.
6358  *
6359  * The struct declaration for register ALT_CLKMGR_SDRPLL_STAT.
6360  */
6362 {
6363  const uint32_t outresetack : 6; /* Output Counter Reset Acknowledge */
6364  uint32_t : 26; /* *UNDEFINED* */
6365 };
6366 
6367 /* The typedef declaration for register ALT_CLKMGR_SDRPLL_STAT. */
6368 typedef volatile struct ALT_CLKMGR_SDRPLL_STAT_s ALT_CLKMGR_SDRPLL_STAT_t;
6369 #endif /* __ASSEMBLY__ */
6370 
6371 /* The byte offset of the ALT_CLKMGR_SDRPLL_STAT register from the beginning of the component. */
6372 #define ALT_CLKMGR_SDRPLL_STAT_OFST 0x1c
6373 
6374 #ifndef __ASSEMBLY__
6375 /*
6376  * WARNING: The C register and register group struct declarations are provided for
6377  * convenience and illustrative purposes. They should, however, be used with
6378  * caution as the C language standard provides no guarantees about the alignment or
6379  * atomicity of device memory accesses. The recommended practice for writing
6380  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6381  * alt_write_word() functions.
6382  *
6383  * The struct declaration for register group ALT_CLKMGR_SDRPLL.
6384  */
6386 {
6387  volatile ALT_CLKMGR_SDRPLL_VCO_t vco; /* ALT_CLKMGR_SDRPLL_VCO */
6388  volatile ALT_CLKMGR_SDRPLL_CTL_t ctrl; /* ALT_CLKMGR_SDRPLL_CTL */
6389  volatile ALT_CLKMGR_SDRPLL_DDRDQSCLK_t ddrdqsclk; /* ALT_CLKMGR_SDRPLL_DDRDQSCLK */
6390  volatile ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_t ddr2xdqsclk; /* ALT_CLKMGR_SDRPLL_DDR2XDQSCLK */
6391  volatile ALT_CLKMGR_SDRPLL_DDRDQCLK_t ddrdqclk; /* ALT_CLKMGR_SDRPLL_DDRDQCLK */
6392  volatile ALT_CLKMGR_SDRPLL_S2FUSER2CLK_t s2fuser2clk; /* ALT_CLKMGR_SDRPLL_S2FUSER2CLK */
6393  volatile ALT_CLKMGR_SDRPLL_EN_t en; /* ALT_CLKMGR_SDRPLL_EN */
6394  volatile ALT_CLKMGR_SDRPLL_STAT_t stat; /* ALT_CLKMGR_SDRPLL_STAT */
6395 };
6396 
6397 /* The typedef declaration for register group ALT_CLKMGR_SDRPLL. */
6398 typedef volatile struct ALT_CLKMGR_SDRPLL_s ALT_CLKMGR_SDRPLL_t;
6399 /* The struct declaration for the raw register contents of register group ALT_CLKMGR_SDRPLL. */
6401 {
6402  volatile uint32_t vco; /* ALT_CLKMGR_SDRPLL_VCO */
6403  volatile uint32_t ctrl; /* ALT_CLKMGR_SDRPLL_CTL */
6404  volatile uint32_t ddrdqsclk; /* ALT_CLKMGR_SDRPLL_DDRDQSCLK */
6405  volatile uint32_t ddr2xdqsclk; /* ALT_CLKMGR_SDRPLL_DDR2XDQSCLK */
6406  volatile uint32_t ddrdqclk; /* ALT_CLKMGR_SDRPLL_DDRDQCLK */
6407  volatile uint32_t s2fuser2clk; /* ALT_CLKMGR_SDRPLL_S2FUSER2CLK */
6408  volatile uint32_t en; /* ALT_CLKMGR_SDRPLL_EN */
6409  volatile uint32_t stat; /* ALT_CLKMGR_SDRPLL_STAT */
6410 };
6411 
6412 /* The typedef declaration for the raw register contents of register group ALT_CLKMGR_SDRPLL. */
6413 typedef volatile struct ALT_CLKMGR_SDRPLL_raw_s ALT_CLKMGR_SDRPLL_raw_t;
6414 #endif /* __ASSEMBLY__ */
6415 
6416 
6417 #ifndef __ASSEMBLY__
6418 /*
6419  * WARNING: The C register and register group struct declarations are provided for
6420  * convenience and illustrative purposes. They should, however, be used with
6421  * caution as the C language standard provides no guarantees about the alignment or
6422  * atomicity of device memory accesses. The recommended practice for writing
6423  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6424  * alt_write_word() functions.
6425  *
6426  * The struct declaration for register group ALT_CLKMGR.
6427  */
6429 {
6430  volatile ALT_CLKMGR_CTL_t ctrl; /* ALT_CLKMGR_CTL */
6431  volatile ALT_CLKMGR_BYPASS_t bypass; /* ALT_CLKMGR_BYPASS */
6432  volatile ALT_CLKMGR_INTER_t inter; /* ALT_CLKMGR_INTER */
6433  volatile ALT_CLKMGR_INTREN_t intren; /* ALT_CLKMGR_INTREN */
6434  volatile ALT_CLKMGR_DBCTL_t dbctrl; /* ALT_CLKMGR_DBCTL */
6435  volatile ALT_CLKMGR_STAT_t stat; /* ALT_CLKMGR_STAT */
6436  volatile uint32_t _pad_0x18_0x3f[10]; /* *UNDEFINED* */
6437  volatile ALT_CLKMGR_MAINPLL_t mainpllgrp; /* ALT_CLKMGR_MAINPLL */
6438  volatile ALT_CLKMGR_PERPLL_t perpllgrp; /* ALT_CLKMGR_PERPLL */
6439  volatile ALT_CLKMGR_SDRPLL_t sdrpllgrp; /* ALT_CLKMGR_SDRPLL */
6440  volatile uint32_t _pad_0xe0_0x200[72]; /* *UNDEFINED* */
6441 };
6442 
6443 /* The typedef declaration for register group ALT_CLKMGR. */
6444 typedef volatile struct ALT_CLKMGR_s ALT_CLKMGR_t;
6445 /* The struct declaration for the raw register contents of register group ALT_CLKMGR. */
6447 {
6448  volatile uint32_t ctrl; /* ALT_CLKMGR_CTL */
6449  volatile uint32_t bypass; /* ALT_CLKMGR_BYPASS */
6450  volatile uint32_t inter; /* ALT_CLKMGR_INTER */
6451  volatile uint32_t intren; /* ALT_CLKMGR_INTREN */
6452  volatile uint32_t dbctrl; /* ALT_CLKMGR_DBCTL */
6453  volatile uint32_t stat; /* ALT_CLKMGR_STAT */
6454  volatile uint32_t _pad_0x18_0x3f[10]; /* *UNDEFINED* */
6455  volatile ALT_CLKMGR_MAINPLL_raw_t mainpllgrp; /* ALT_CLKMGR_MAINPLL */
6456  volatile ALT_CLKMGR_PERPLL_raw_t perpllgrp; /* ALT_CLKMGR_PERPLL */
6457  volatile ALT_CLKMGR_SDRPLL_raw_t sdrpllgrp; /* ALT_CLKMGR_SDRPLL */
6458  volatile uint32_t _pad_0xe0_0x200[72]; /* *UNDEFINED* */
6459 };
6460 
6461 /* The typedef declaration for the raw register contents of register group ALT_CLKMGR. */
6462 typedef volatile struct ALT_CLKMGR_raw_s ALT_CLKMGR_raw_t;
6463 #endif /* __ASSEMBLY__ */
6464 
6465 
6466 #ifdef __cplusplus
6467 }
6468 #endif /* __cplusplus */
6469 #endif /* __ALTERA_ALT_CLKMGR_H__ */
6470 
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