39 #ifndef __ALTERA_ALT_CLKMGR_H__ 40 #define __ALTERA_ALT_CLKMGR_H__ 89 #define ALT_CLKMGR_CTL_SAFEMOD_LSB 0 91 #define ALT_CLKMGR_CTL_SAFEMOD_MSB 0 93 #define ALT_CLKMGR_CTL_SAFEMOD_WIDTH 1 95 #define ALT_CLKMGR_CTL_SAFEMOD_SET_MSK 0x00000001 97 #define ALT_CLKMGR_CTL_SAFEMOD_CLR_MSK 0xfffffffe 99 #define ALT_CLKMGR_CTL_SAFEMOD_RESET 0x1 101 #define ALT_CLKMGR_CTL_SAFEMOD_GET(value) (((value) & 0x00000001) >> 0) 103 #define ALT_CLKMGR_CTL_SAFEMOD_SET(value) (((value) << 0) & 0x00000001) 117 #define ALT_CLKMGR_CTL_ENSFMDWR_LSB 2 119 #define ALT_CLKMGR_CTL_ENSFMDWR_MSB 2 121 #define ALT_CLKMGR_CTL_ENSFMDWR_WIDTH 1 123 #define ALT_CLKMGR_CTL_ENSFMDWR_SET_MSK 0x00000004 125 #define ALT_CLKMGR_CTL_ENSFMDWR_CLR_MSK 0xfffffffb 127 #define ALT_CLKMGR_CTL_ENSFMDWR_RESET 0x1 129 #define ALT_CLKMGR_CTL_ENSFMDWR_GET(value) (((value) & 0x00000004) >> 2) 131 #define ALT_CLKMGR_CTL_ENSFMDWR_SET(value) (((value) << 2) & 0x00000004) 146 uint32_t safemode : 1;
148 uint32_t ensfmdwr : 1;
157 #define ALT_CLKMGR_CTL_OFST 0x0 190 #define ALT_CLKMGR_BYPASS_MAINPLL_LSB 0 192 #define ALT_CLKMGR_BYPASS_MAINPLL_MSB 0 194 #define ALT_CLKMGR_BYPASS_MAINPLL_WIDTH 1 196 #define ALT_CLKMGR_BYPASS_MAINPLL_SET_MSK 0x00000001 198 #define ALT_CLKMGR_BYPASS_MAINPLL_CLR_MSK 0xfffffffe 200 #define ALT_CLKMGR_BYPASS_MAINPLL_RESET 0x1 202 #define ALT_CLKMGR_BYPASS_MAINPLL_GET(value) (((value) & 0x00000001) >> 0) 204 #define ALT_CLKMGR_BYPASS_MAINPLL_SET(value) (((value) << 0) & 0x00000001) 223 #define ALT_CLKMGR_BYPASS_SDRPLL_LSB 1 225 #define ALT_CLKMGR_BYPASS_SDRPLL_MSB 1 227 #define ALT_CLKMGR_BYPASS_SDRPLL_WIDTH 1 229 #define ALT_CLKMGR_BYPASS_SDRPLL_SET_MSK 0x00000002 231 #define ALT_CLKMGR_BYPASS_SDRPLL_CLR_MSK 0xfffffffd 233 #define ALT_CLKMGR_BYPASS_SDRPLL_RESET 0x1 235 #define ALT_CLKMGR_BYPASS_SDRPLL_GET(value) (((value) & 0x00000002) >> 1) 237 #define ALT_CLKMGR_BYPASS_SDRPLL_SET(value) (((value) << 1) & 0x00000002) 265 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_E_SELECT_EOSC1 0x0 271 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_E_SELECT_INPUT_MUX 0x1 274 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_LSB 2 276 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_MSB 2 278 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_WIDTH 1 280 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_SET_MSK 0x00000004 282 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_CLR_MSK 0xfffffffb 284 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_RESET 0x0 286 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_GET(value) (((value) & 0x00000004) >> 2) 288 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_SET(value) (((value) << 2) & 0x00000004) 307 #define ALT_CLKMGR_BYPASS_PERPLL_LSB 3 309 #define ALT_CLKMGR_BYPASS_PERPLL_MSB 3 311 #define ALT_CLKMGR_BYPASS_PERPLL_WIDTH 1 313 #define ALT_CLKMGR_BYPASS_PERPLL_SET_MSK 0x00000008 315 #define ALT_CLKMGR_BYPASS_PERPLL_CLR_MSK 0xfffffff7 317 #define ALT_CLKMGR_BYPASS_PERPLL_RESET 0x1 319 #define ALT_CLKMGR_BYPASS_PERPLL_GET(value) (((value) & 0x00000008) >> 3) 321 #define ALT_CLKMGR_BYPASS_PERPLL_SET(value) (((value) << 3) & 0x00000008) 349 #define ALT_CLKMGR_BYPASS_PERPLLSRC_E_SELECT_EOSC1 0x0 355 #define ALT_CLKMGR_BYPASS_PERPLLSRC_E_SELECT_INPUT_MUX 0x1 358 #define ALT_CLKMGR_BYPASS_PERPLLSRC_LSB 4 360 #define ALT_CLKMGR_BYPASS_PERPLLSRC_MSB 4 362 #define ALT_CLKMGR_BYPASS_PERPLLSRC_WIDTH 1 364 #define ALT_CLKMGR_BYPASS_PERPLLSRC_SET_MSK 0x00000010 366 #define ALT_CLKMGR_BYPASS_PERPLLSRC_CLR_MSK 0xffffffef 368 #define ALT_CLKMGR_BYPASS_PERPLLSRC_RESET 0x0 370 #define ALT_CLKMGR_BYPASS_PERPLLSRC_GET(value) (((value) & 0x00000010) >> 4) 372 #define ALT_CLKMGR_BYPASS_PERPLLSRC_SET(value) (((value) << 4) & 0x00000010) 387 uint32_t mainpll : 1;
389 uint32_t sdrpllsrc : 1;
391 uint32_t perpllsrc : 1;
400 #define ALT_CLKMGR_BYPASS_OFST 0x4 435 #define ALT_CLKMGR_INTER_MAINPLLACHIEVED_LSB 0 437 #define ALT_CLKMGR_INTER_MAINPLLACHIEVED_MSB 0 439 #define ALT_CLKMGR_INTER_MAINPLLACHIEVED_WIDTH 1 441 #define ALT_CLKMGR_INTER_MAINPLLACHIEVED_SET_MSK 0x00000001 443 #define ALT_CLKMGR_INTER_MAINPLLACHIEVED_CLR_MSK 0xfffffffe 445 #define ALT_CLKMGR_INTER_MAINPLLACHIEVED_RESET 0x0 447 #define ALT_CLKMGR_INTER_MAINPLLACHIEVED_GET(value) (((value) & 0x00000001) >> 0) 449 #define ALT_CLKMGR_INTER_MAINPLLACHIEVED_SET(value) (((value) << 0) & 0x00000001) 462 #define ALT_CLKMGR_INTER_PERPLLACHIEVED_LSB 1 464 #define ALT_CLKMGR_INTER_PERPLLACHIEVED_MSB 1 466 #define ALT_CLKMGR_INTER_PERPLLACHIEVED_WIDTH 1 468 #define ALT_CLKMGR_INTER_PERPLLACHIEVED_SET_MSK 0x00000002 470 #define ALT_CLKMGR_INTER_PERPLLACHIEVED_CLR_MSK 0xfffffffd 472 #define ALT_CLKMGR_INTER_PERPLLACHIEVED_RESET 0x0 474 #define ALT_CLKMGR_INTER_PERPLLACHIEVED_GET(value) (((value) & 0x00000002) >> 1) 476 #define ALT_CLKMGR_INTER_PERPLLACHIEVED_SET(value) (((value) << 1) & 0x00000002) 488 #define ALT_CLKMGR_INTER_SDRPLLACHIEVED_LSB 2 490 #define ALT_CLKMGR_INTER_SDRPLLACHIEVED_MSB 2 492 #define ALT_CLKMGR_INTER_SDRPLLACHIEVED_WIDTH 1 494 #define ALT_CLKMGR_INTER_SDRPLLACHIEVED_SET_MSK 0x00000004 496 #define ALT_CLKMGR_INTER_SDRPLLACHIEVED_CLR_MSK 0xfffffffb 498 #define ALT_CLKMGR_INTER_SDRPLLACHIEVED_RESET 0x0 500 #define ALT_CLKMGR_INTER_SDRPLLACHIEVED_GET(value) (((value) & 0x00000004) >> 2) 502 #define ALT_CLKMGR_INTER_SDRPLLACHIEVED_SET(value) (((value) << 2) & 0x00000004) 514 #define ALT_CLKMGR_INTER_MAINPLLLOST_LSB 3 516 #define ALT_CLKMGR_INTER_MAINPLLLOST_MSB 3 518 #define ALT_CLKMGR_INTER_MAINPLLLOST_WIDTH 1 520 #define ALT_CLKMGR_INTER_MAINPLLLOST_SET_MSK 0x00000008 522 #define ALT_CLKMGR_INTER_MAINPLLLOST_CLR_MSK 0xfffffff7 524 #define ALT_CLKMGR_INTER_MAINPLLLOST_RESET 0x0 526 #define ALT_CLKMGR_INTER_MAINPLLLOST_GET(value) (((value) & 0x00000008) >> 3) 528 #define ALT_CLKMGR_INTER_MAINPLLLOST_SET(value) (((value) << 3) & 0x00000008) 540 #define ALT_CLKMGR_INTER_PERPLLLOST_LSB 4 542 #define ALT_CLKMGR_INTER_PERPLLLOST_MSB 4 544 #define ALT_CLKMGR_INTER_PERPLLLOST_WIDTH 1 546 #define ALT_CLKMGR_INTER_PERPLLLOST_SET_MSK 0x00000010 548 #define ALT_CLKMGR_INTER_PERPLLLOST_CLR_MSK 0xffffffef 550 #define ALT_CLKMGR_INTER_PERPLLLOST_RESET 0x0 552 #define ALT_CLKMGR_INTER_PERPLLLOST_GET(value) (((value) & 0x00000010) >> 4) 554 #define ALT_CLKMGR_INTER_PERPLLLOST_SET(value) (((value) << 4) & 0x00000010) 566 #define ALT_CLKMGR_INTER_SDRPLLLOST_LSB 5 568 #define ALT_CLKMGR_INTER_SDRPLLLOST_MSB 5 570 #define ALT_CLKMGR_INTER_SDRPLLLOST_WIDTH 1 572 #define ALT_CLKMGR_INTER_SDRPLLLOST_SET_MSK 0x00000020 574 #define ALT_CLKMGR_INTER_SDRPLLLOST_CLR_MSK 0xffffffdf 576 #define ALT_CLKMGR_INTER_SDRPLLLOST_RESET 0x0 578 #define ALT_CLKMGR_INTER_SDRPLLLOST_GET(value) (((value) & 0x00000020) >> 5) 580 #define ALT_CLKMGR_INTER_SDRPLLLOST_SET(value) (((value) << 5) & 0x00000020) 592 #define ALT_CLKMGR_INTER_MAINPLLLOCKED_LSB 6 594 #define ALT_CLKMGR_INTER_MAINPLLLOCKED_MSB 6 596 #define ALT_CLKMGR_INTER_MAINPLLLOCKED_WIDTH 1 598 #define ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK 0x00000040 600 #define ALT_CLKMGR_INTER_MAINPLLLOCKED_CLR_MSK 0xffffffbf 602 #define ALT_CLKMGR_INTER_MAINPLLLOCKED_RESET 0x0 604 #define ALT_CLKMGR_INTER_MAINPLLLOCKED_GET(value) (((value) & 0x00000040) >> 6) 606 #define ALT_CLKMGR_INTER_MAINPLLLOCKED_SET(value) (((value) << 6) & 0x00000040) 618 #define ALT_CLKMGR_INTER_PERPLLLOCKED_LSB 7 620 #define ALT_CLKMGR_INTER_PERPLLLOCKED_MSB 7 622 #define ALT_CLKMGR_INTER_PERPLLLOCKED_WIDTH 1 624 #define ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK 0x00000080 626 #define ALT_CLKMGR_INTER_PERPLLLOCKED_CLR_MSK 0xffffff7f 628 #define ALT_CLKMGR_INTER_PERPLLLOCKED_RESET 0x0 630 #define ALT_CLKMGR_INTER_PERPLLLOCKED_GET(value) (((value) & 0x00000080) >> 7) 632 #define ALT_CLKMGR_INTER_PERPLLLOCKED_SET(value) (((value) << 7) & 0x00000080) 644 #define ALT_CLKMGR_INTER_SDRPLLLOCKED_LSB 8 646 #define ALT_CLKMGR_INTER_SDRPLLLOCKED_MSB 8 648 #define ALT_CLKMGR_INTER_SDRPLLLOCKED_WIDTH 1 650 #define ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK 0x00000100 652 #define ALT_CLKMGR_INTER_SDRPLLLOCKED_CLR_MSK 0xfffffeff 654 #define ALT_CLKMGR_INTER_SDRPLLLOCKED_RESET 0x0 656 #define ALT_CLKMGR_INTER_SDRPLLLOCKED_GET(value) (((value) & 0x00000100) >> 8) 658 #define ALT_CLKMGR_INTER_SDRPLLLOCKED_SET(value) (((value) << 8) & 0x00000100) 673 uint32_t mainpllachieved : 1;
674 uint32_t perpllachieved : 1;
675 uint32_t sdrpllachieved : 1;
676 uint32_t mainplllost : 1;
677 uint32_t perplllost : 1;
678 uint32_t sdrplllost : 1;
679 const uint32_t mainplllocked : 1;
680 const uint32_t perplllocked : 1;
681 const uint32_t sdrplllocked : 1;
690 #define ALT_CLKMGR_INTER_OFST 0x8 723 #define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_LSB 0 725 #define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_MSB 0 727 #define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_WIDTH 1 729 #define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_SET_MSK 0x00000001 731 #define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_CLR_MSK 0xfffffffe 733 #define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_RESET 0x0 735 #define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_GET(value) (((value) & 0x00000001) >> 0) 737 #define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_SET(value) (((value) << 0) & 0x00000001) 750 #define ALT_CLKMGR_INTREN_PERPLLACHIEVED_LSB 1 752 #define ALT_CLKMGR_INTREN_PERPLLACHIEVED_MSB 1 754 #define ALT_CLKMGR_INTREN_PERPLLACHIEVED_WIDTH 1 756 #define ALT_CLKMGR_INTREN_PERPLLACHIEVED_SET_MSK 0x00000002 758 #define ALT_CLKMGR_INTREN_PERPLLACHIEVED_CLR_MSK 0xfffffffd 760 #define ALT_CLKMGR_INTREN_PERPLLACHIEVED_RESET 0x0 762 #define ALT_CLKMGR_INTREN_PERPLLACHIEVED_GET(value) (((value) & 0x00000002) >> 1) 764 #define ALT_CLKMGR_INTREN_PERPLLACHIEVED_SET(value) (((value) << 1) & 0x00000002) 777 #define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_LSB 2 779 #define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_MSB 2 781 #define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_WIDTH 1 783 #define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_SET_MSK 0x00000004 785 #define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_CLR_MSK 0xfffffffb 787 #define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_RESET 0x0 789 #define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_GET(value) (((value) & 0x00000004) >> 2) 791 #define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_SET(value) (((value) << 2) & 0x00000004) 804 #define ALT_CLKMGR_INTREN_MAINPLLLOST_LSB 3 806 #define ALT_CLKMGR_INTREN_MAINPLLLOST_MSB 3 808 #define ALT_CLKMGR_INTREN_MAINPLLLOST_WIDTH 1 810 #define ALT_CLKMGR_INTREN_MAINPLLLOST_SET_MSK 0x00000008 812 #define ALT_CLKMGR_INTREN_MAINPLLLOST_CLR_MSK 0xfffffff7 814 #define ALT_CLKMGR_INTREN_MAINPLLLOST_RESET 0x0 816 #define ALT_CLKMGR_INTREN_MAINPLLLOST_GET(value) (((value) & 0x00000008) >> 3) 818 #define ALT_CLKMGR_INTREN_MAINPLLLOST_SET(value) (((value) << 3) & 0x00000008) 831 #define ALT_CLKMGR_INTREN_PERPLLLOST_LSB 4 833 #define ALT_CLKMGR_INTREN_PERPLLLOST_MSB 4 835 #define ALT_CLKMGR_INTREN_PERPLLLOST_WIDTH 1 837 #define ALT_CLKMGR_INTREN_PERPLLLOST_SET_MSK 0x00000010 839 #define ALT_CLKMGR_INTREN_PERPLLLOST_CLR_MSK 0xffffffef 841 #define ALT_CLKMGR_INTREN_PERPLLLOST_RESET 0x0 843 #define ALT_CLKMGR_INTREN_PERPLLLOST_GET(value) (((value) & 0x00000010) >> 4) 845 #define ALT_CLKMGR_INTREN_PERPLLLOST_SET(value) (((value) << 4) & 0x00000010) 858 #define ALT_CLKMGR_INTREN_SDRPLLLOST_LSB 5 860 #define ALT_CLKMGR_INTREN_SDRPLLLOST_MSB 5 862 #define ALT_CLKMGR_INTREN_SDRPLLLOST_WIDTH 1 864 #define ALT_CLKMGR_INTREN_SDRPLLLOST_SET_MSK 0x00000020 866 #define ALT_CLKMGR_INTREN_SDRPLLLOST_CLR_MSK 0xffffffdf 868 #define ALT_CLKMGR_INTREN_SDRPLLLOST_RESET 0x0 870 #define ALT_CLKMGR_INTREN_SDRPLLLOST_GET(value) (((value) & 0x00000020) >> 5) 872 #define ALT_CLKMGR_INTREN_SDRPLLLOST_SET(value) (((value) << 5) & 0x00000020) 887 uint32_t mainpllachieved : 1;
888 uint32_t perpllachieved : 1;
889 uint32_t sdrpllachieved : 1;
890 uint32_t mainplllost : 1;
891 uint32_t perplllost : 1;
892 uint32_t sdrplllost : 1;
901 #define ALT_CLKMGR_INTREN_OFST 0xc 933 #define ALT_CLKMGR_DBCTL_STAYOSC1_LSB 0 935 #define ALT_CLKMGR_DBCTL_STAYOSC1_MSB 0 937 #define ALT_CLKMGR_DBCTL_STAYOSC1_WIDTH 1 939 #define ALT_CLKMGR_DBCTL_STAYOSC1_SET_MSK 0x00000001 941 #define ALT_CLKMGR_DBCTL_STAYOSC1_CLR_MSK 0xfffffffe 943 #define ALT_CLKMGR_DBCTL_STAYOSC1_RESET 0x1 945 #define ALT_CLKMGR_DBCTL_STAYOSC1_GET(value) (((value) & 0x00000001) >> 0) 947 #define ALT_CLKMGR_DBCTL_STAYOSC1_SET(value) (((value) << 0) & 0x00000001) 966 #define ALT_CLKMGR_DBCTL_ENSFMDWR_LSB 1 968 #define ALT_CLKMGR_DBCTL_ENSFMDWR_MSB 1 970 #define ALT_CLKMGR_DBCTL_ENSFMDWR_WIDTH 1 972 #define ALT_CLKMGR_DBCTL_ENSFMDWR_SET_MSK 0x00000002 974 #define ALT_CLKMGR_DBCTL_ENSFMDWR_CLR_MSK 0xfffffffd 976 #define ALT_CLKMGR_DBCTL_ENSFMDWR_RESET 0x1 978 #define ALT_CLKMGR_DBCTL_ENSFMDWR_GET(value) (((value) & 0x00000002) >> 1) 980 #define ALT_CLKMGR_DBCTL_ENSFMDWR_SET(value) (((value) << 1) & 0x00000002) 995 uint32_t stayosc1 : 1;
996 uint32_t ensfmdwr : 1;
1005 #define ALT_CLKMGR_DBCTL_OFST 0x10 1048 #define ALT_CLKMGR_STAT_BUSY_E_IDLE 0x0 1054 #define ALT_CLKMGR_STAT_BUSY_E_BUSY 0x1 1057 #define ALT_CLKMGR_STAT_BUSY_LSB 0 1059 #define ALT_CLKMGR_STAT_BUSY_MSB 0 1061 #define ALT_CLKMGR_STAT_BUSY_WIDTH 1 1063 #define ALT_CLKMGR_STAT_BUSY_SET_MSK 0x00000001 1065 #define ALT_CLKMGR_STAT_BUSY_CLR_MSK 0xfffffffe 1067 #define ALT_CLKMGR_STAT_BUSY_RESET 0x0 1069 #define ALT_CLKMGR_STAT_BUSY_GET(value) (((value) & 0x00000001) >> 0) 1071 #define ALT_CLKMGR_STAT_BUSY_SET(value) (((value) << 0) & 0x00000001) 1073 #ifndef __ASSEMBLY__ 1086 const uint32_t busy : 1;
1095 #define ALT_CLKMGR_STAT_OFST 0x14 1137 #define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_LSB 0 1139 #define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_MSB 0 1141 #define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_WIDTH 1 1143 #define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_SET_MSK 0x00000001 1145 #define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_CLR_MSK 0xfffffffe 1147 #define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_RESET 0x1 1149 #define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0) 1151 #define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_SET(value) (((value) << 0) & 0x00000001) 1162 #define ALT_CLKMGR_MAINPLL_VCO_EN_LSB 1 1164 #define ALT_CLKMGR_MAINPLL_VCO_EN_MSB 1 1166 #define ALT_CLKMGR_MAINPLL_VCO_EN_WIDTH 1 1168 #define ALT_CLKMGR_MAINPLL_VCO_EN_SET_MSK 0x00000002 1170 #define ALT_CLKMGR_MAINPLL_VCO_EN_CLR_MSK 0xfffffffd 1172 #define ALT_CLKMGR_MAINPLL_VCO_EN_RESET 0x0 1174 #define ALT_CLKMGR_MAINPLL_VCO_EN_GET(value) (((value) & 0x00000002) >> 1) 1176 #define ALT_CLKMGR_MAINPLL_VCO_EN_SET(value) (((value) << 1) & 0x00000002) 1187 #define ALT_CLKMGR_MAINPLL_VCO_PWRDN_LSB 2 1189 #define ALT_CLKMGR_MAINPLL_VCO_PWRDN_MSB 2 1191 #define ALT_CLKMGR_MAINPLL_VCO_PWRDN_WIDTH 1 1193 #define ALT_CLKMGR_MAINPLL_VCO_PWRDN_SET_MSK 0x00000004 1195 #define ALT_CLKMGR_MAINPLL_VCO_PWRDN_CLR_MSK 0xfffffffb 1197 #define ALT_CLKMGR_MAINPLL_VCO_PWRDN_RESET 0x1 1199 #define ALT_CLKMGR_MAINPLL_VCO_PWRDN_GET(value) (((value) & 0x00000004) >> 2) 1201 #define ALT_CLKMGR_MAINPLL_VCO_PWRDN_SET(value) (((value) << 2) & 0x00000004) 1215 #define ALT_CLKMGR_MAINPLL_VCO_NUMER_LSB 3 1217 #define ALT_CLKMGR_MAINPLL_VCO_NUMER_MSB 15 1219 #define ALT_CLKMGR_MAINPLL_VCO_NUMER_WIDTH 13 1221 #define ALT_CLKMGR_MAINPLL_VCO_NUMER_SET_MSK 0x0000fff8 1223 #define ALT_CLKMGR_MAINPLL_VCO_NUMER_CLR_MSK 0xffff0007 1225 #define ALT_CLKMGR_MAINPLL_VCO_NUMER_RESET 0x1 1227 #define ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(value) (((value) & 0x0000fff8) >> 3) 1229 #define ALT_CLKMGR_MAINPLL_VCO_NUMER_SET(value) (((value) << 3) & 0x0000fff8) 1243 #define ALT_CLKMGR_MAINPLL_VCO_DENOM_LSB 16 1245 #define ALT_CLKMGR_MAINPLL_VCO_DENOM_MSB 21 1247 #define ALT_CLKMGR_MAINPLL_VCO_DENOM_WIDTH 6 1249 #define ALT_CLKMGR_MAINPLL_VCO_DENOM_SET_MSK 0x003f0000 1251 #define ALT_CLKMGR_MAINPLL_VCO_DENOM_CLR_MSK 0xffc0ffff 1253 #define ALT_CLKMGR_MAINPLL_VCO_DENOM_RESET 0x1 1255 #define ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(value) (((value) & 0x003f0000) >> 16) 1257 #define ALT_CLKMGR_MAINPLL_VCO_DENOM_SET(value) (((value) << 16) & 0x003f0000) 1275 #define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_LSB 24 1277 #define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_MSB 24 1279 #define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_WIDTH 1 1281 #define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_SET_MSK 0x01000000 1283 #define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_CLR_MSK 0xfeffffff 1285 #define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_RESET 0x0 1287 #define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_GET(value) (((value) & 0x01000000) >> 24) 1289 #define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_SET(value) (((value) << 24) & 0x01000000) 1316 #define ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB 25 1318 #define ALT_CLKMGR_MAINPLL_VCO_OUTRST_MSB 30 1320 #define ALT_CLKMGR_MAINPLL_VCO_OUTRST_WIDTH 6 1322 #define ALT_CLKMGR_MAINPLL_VCO_OUTRST_SET_MSK 0x7e000000 1324 #define ALT_CLKMGR_MAINPLL_VCO_OUTRST_CLR_MSK 0x81ffffff 1326 #define ALT_CLKMGR_MAINPLL_VCO_OUTRST_RESET 0x0 1328 #define ALT_CLKMGR_MAINPLL_VCO_OUTRST_GET(value) (((value) & 0x7e000000) >> 25) 1330 #define ALT_CLKMGR_MAINPLL_VCO_OUTRST_SET(value) (((value) << 25) & 0x7e000000) 1353 #define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_LSB 31 1355 #define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_MSB 31 1357 #define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_WIDTH 1 1359 #define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_SET_MSK 0x80000000 1361 #define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_CLR_MSK 0x7fffffff 1363 #define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_RESET 0x1 1365 #define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_GET(value) (((value) & 0x80000000) >> 31) 1367 #define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_SET(value) (((value) << 31) & 0x80000000) 1369 #ifndef __ASSEMBLY__ 1382 uint32_t bgpwrdn : 1;
1385 uint32_t numer : 13;
1388 uint32_t outresetall : 1;
1389 uint32_t outreset : 6;
1390 uint32_t regextsel : 1;
1398 #define ALT_CLKMGR_MAINPLL_VCO_OFST 0x0 1433 #define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_LSB 0 1435 #define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_MSB 0 1437 #define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_WIDTH 1 1439 #define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_SET_MSK 0x00000001 1441 #define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_CLR_MSK 0xfffffffe 1443 #define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_RESET 0x0 1445 #define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_GET(value) (((value) & 0x00000001) >> 0) 1447 #define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_SET(value) (((value) << 0) & 0x00000001) 1458 #define ALT_CLKMGR_MAINPLL_MISC_BWADJ_LSB 1 1460 #define ALT_CLKMGR_MAINPLL_MISC_BWADJ_MSB 12 1462 #define ALT_CLKMGR_MAINPLL_MISC_BWADJ_WIDTH 12 1464 #define ALT_CLKMGR_MAINPLL_MISC_BWADJ_SET_MSK 0x00001ffe 1466 #define ALT_CLKMGR_MAINPLL_MISC_BWADJ_CLR_MSK 0xffffe001 1468 #define ALT_CLKMGR_MAINPLL_MISC_BWADJ_RESET 0x1 1470 #define ALT_CLKMGR_MAINPLL_MISC_BWADJ_GET(value) (((value) & 0x00001ffe) >> 1) 1472 #define ALT_CLKMGR_MAINPLL_MISC_BWADJ_SET(value) (((value) << 1) & 0x00001ffe) 1483 #define ALT_CLKMGR_MAINPLL_MISC_FASTEN_LSB 13 1485 #define ALT_CLKMGR_MAINPLL_MISC_FASTEN_MSB 13 1487 #define ALT_CLKMGR_MAINPLL_MISC_FASTEN_WIDTH 1 1489 #define ALT_CLKMGR_MAINPLL_MISC_FASTEN_SET_MSK 0x00002000 1491 #define ALT_CLKMGR_MAINPLL_MISC_FASTEN_CLR_MSK 0xffffdfff 1493 #define ALT_CLKMGR_MAINPLL_MISC_FASTEN_RESET 0x0 1495 #define ALT_CLKMGR_MAINPLL_MISC_FASTEN_GET(value) (((value) & 0x00002000) >> 13) 1497 #define ALT_CLKMGR_MAINPLL_MISC_FASTEN_SET(value) (((value) << 13) & 0x00002000) 1508 #define ALT_CLKMGR_MAINPLL_MISC_SATEN_LSB 14 1510 #define ALT_CLKMGR_MAINPLL_MISC_SATEN_MSB 14 1512 #define ALT_CLKMGR_MAINPLL_MISC_SATEN_WIDTH 1 1514 #define ALT_CLKMGR_MAINPLL_MISC_SATEN_SET_MSK 0x00004000 1516 #define ALT_CLKMGR_MAINPLL_MISC_SATEN_CLR_MSK 0xffffbfff 1518 #define ALT_CLKMGR_MAINPLL_MISC_SATEN_RESET 0x1 1520 #define ALT_CLKMGR_MAINPLL_MISC_SATEN_GET(value) (((value) & 0x00004000) >> 14) 1522 #define ALT_CLKMGR_MAINPLL_MISC_SATEN_SET(value) (((value) << 14) & 0x00004000) 1524 #ifndef __ASSEMBLY__ 1537 uint32_t bwadjen : 1;
1538 uint32_t bwadj : 12;
1539 uint32_t fasten : 1;
1549 #define ALT_CLKMGR_MAINPLL_MISC_OFST 0x4 1576 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_LSB 0 1578 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_MSB 8 1580 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_WIDTH 9 1582 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_SET_MSK 0x000001ff 1584 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_CLR_MSK 0xfffffe00 1586 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_RESET 0x0 1588 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) 1590 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) 1592 #ifndef __ASSEMBLY__ 1614 #define ALT_CLKMGR_MAINPLL_MPUCLK_OFST 0x8 1641 #define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_LSB 0 1643 #define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_MSB 8 1645 #define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_WIDTH 9 1647 #define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_SET_MSK 0x000001ff 1649 #define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_CLR_MSK 0xfffffe00 1651 #define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_RESET 0x0 1653 #define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) 1655 #define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) 1657 #ifndef __ASSEMBLY__ 1679 #define ALT_CLKMGR_MAINPLL_MAINCLK_OFST 0xc 1706 #define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_LSB 0 1708 #define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_MSB 8 1710 #define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_WIDTH 9 1712 #define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_SET_MSK 0x000001ff 1714 #define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_CLR_MSK 0xfffffe00 1716 #define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_RESET 0x0 1718 #define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) 1720 #define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) 1722 #ifndef __ASSEMBLY__ 1744 #define ALT_CLKMGR_MAINPLL_DBGATCLK_OFST 0x10 1771 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_LSB 0 1773 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_MSB 8 1775 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_WIDTH 9 1777 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_SET_MSK 0x000001ff 1779 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_CLR_MSK 0xfffffe00 1781 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_RESET 0x3 1783 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) 1785 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_SET(value) (((value) << 0) & 0x000001ff) 1787 #ifndef __ASSEMBLY__ 1809 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_OFST 0x14 1836 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_LSB 0 1838 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_MSB 8 1840 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_WIDTH 9 1842 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_SET_MSK 0x000001ff 1844 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_CLR_MSK 0xfffffe00 1846 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_RESET 0x3 1848 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) 1850 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) 1852 #ifndef __ASSEMBLY__ 1874 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_OFST 0x18 1903 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_LSB 0 1905 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_MSB 8 1907 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_WIDTH 9 1909 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_SET_MSK 0x000001ff 1911 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_CLR_MSK 0xfffffe00 1913 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_RESET 0xf 1915 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) 1917 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_SET(value) (((value) << 0) & 0x000001ff) 1919 #ifndef __ASSEMBLY__ 1941 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_OFST 0x1c 1980 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_LSB 0 1982 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_MSB 0 1984 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_WIDTH 1 1986 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET_MSK 0x00000001 1988 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_CLR_MSK 0xfffffffe 1990 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_RESET 0x1 1992 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_GET(value) (((value) & 0x00000001) >> 0) 1994 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET(value) (((value) << 0) & 0x00000001) 2005 #define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_LSB 1 2007 #define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_MSB 1 2009 #define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_WIDTH 1 2011 #define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK 0x00000002 2013 #define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_CLR_MSK 0xfffffffd 2015 #define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_RESET 0x1 2017 #define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_GET(value) (((value) & 0x00000002) >> 1) 2019 #define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET(value) (((value) << 1) & 0x00000002) 2030 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_LSB 2 2032 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_MSB 2 2034 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_WIDTH 1 2036 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK 0x00000004 2038 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK 0xfffffffb 2040 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_RESET 0x1 2042 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_GET(value) (((value) & 0x00000004) >> 2) 2044 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET(value) (((value) << 2) & 0x00000004) 2055 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_LSB 3 2057 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_MSB 3 2059 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_WIDTH 1 2061 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK 0x00000008 2063 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK 0xfffffff7 2065 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_RESET 0x1 2067 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_GET(value) (((value) & 0x00000008) >> 3) 2069 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET(value) (((value) << 3) & 0x00000008) 2080 #define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_LSB 4 2082 #define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_MSB 4 2084 #define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_WIDTH 1 2086 #define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK 0x00000010 2088 #define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_CLR_MSK 0xffffffef 2090 #define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_RESET 0x1 2092 #define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_GET(value) (((value) & 0x00000010) >> 4) 2094 #define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET(value) (((value) << 4) & 0x00000010) 2105 #define ALT_CLKMGR_MAINPLL_EN_DBGCLK_LSB 5 2107 #define ALT_CLKMGR_MAINPLL_EN_DBGCLK_MSB 5 2109 #define ALT_CLKMGR_MAINPLL_EN_DBGCLK_WIDTH 1 2111 #define ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET_MSK 0x00000020 2113 #define ALT_CLKMGR_MAINPLL_EN_DBGCLK_CLR_MSK 0xffffffdf 2115 #define ALT_CLKMGR_MAINPLL_EN_DBGCLK_RESET 0x1 2117 #define ALT_CLKMGR_MAINPLL_EN_DBGCLK_GET(value) (((value) & 0x00000020) >> 5) 2119 #define ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET(value) (((value) << 5) & 0x00000020) 2130 #define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_LSB 6 2132 #define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_MSB 6 2134 #define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_WIDTH 1 2136 #define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK 0x00000040 2138 #define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_CLR_MSK 0xffffffbf 2140 #define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_RESET 0x1 2142 #define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_GET(value) (((value) & 0x00000040) >> 6) 2144 #define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET(value) (((value) << 6) & 0x00000040) 2155 #define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_LSB 7 2157 #define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_MSB 7 2159 #define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_WIDTH 1 2161 #define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET_MSK 0x00000080 2163 #define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_CLR_MSK 0xffffff7f 2165 #define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_RESET 0x1 2167 #define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_GET(value) (((value) & 0x00000080) >> 7) 2169 #define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET(value) (((value) << 7) & 0x00000080) 2180 #define ALT_CLKMGR_MAINPLL_EN_CFGCLK_LSB 8 2182 #define ALT_CLKMGR_MAINPLL_EN_CFGCLK_MSB 8 2184 #define ALT_CLKMGR_MAINPLL_EN_CFGCLK_WIDTH 1 2186 #define ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK 0x00000100 2188 #define ALT_CLKMGR_MAINPLL_EN_CFGCLK_CLR_MSK 0xfffffeff 2190 #define ALT_CLKMGR_MAINPLL_EN_CFGCLK_RESET 0x1 2192 #define ALT_CLKMGR_MAINPLL_EN_CFGCLK_GET(value) (((value) & 0x00000100) >> 8) 2194 #define ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET(value) (((value) << 8) & 0x00000100) 2207 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_LSB 9 2209 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_MSB 9 2211 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_WIDTH 1 2213 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK 0x00000200 2215 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_CLR_MSK 0xfffffdff 2217 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_RESET 0x1 2219 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_GET(value) (((value) & 0x00000200) >> 9) 2221 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET(value) (((value) << 9) & 0x00000200) 2223 #ifndef __ASSEMBLY__ 2236 uint32_t l4mainclk : 1;
2237 uint32_t l3mpclk : 1;
2238 uint32_t l4mpclk : 1;
2239 uint32_t l4spclk : 1;
2240 uint32_t dbgatclk : 1;
2241 uint32_t dbgclk : 1;
2242 uint32_t dbgtraceclk : 1;
2243 uint32_t dbgtimerclk : 1;
2244 uint32_t cfgclk : 1;
2245 uint32_t s2fuser0clk : 1;
2254 #define ALT_CLKMGR_MAINPLL_EN_OFST 0x20 2296 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV1 0x0 2302 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV2 0x1 2305 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_LSB 0 2307 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_MSB 1 2309 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_WIDTH 2 2311 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_SET_MSK 0x00000003 2313 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_CLR_MSK 0xfffffffc 2315 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_RESET 0x0 2317 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_GET(value) (((value) & 0x00000003) >> 0) 2319 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_SET(value) (((value) << 0) & 0x00000003) 2342 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV1 0x0 2348 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2 0x1 2351 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_LSB 2 2353 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_MSB 3 2355 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_WIDTH 2 2357 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_SET_MSK 0x0000000c 2359 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_CLR_MSK 0xfffffff3 2361 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_RESET 0x0 2363 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_GET(value) (((value) & 0x0000000c) >> 2) 2365 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_SET(value) (((value) << 2) & 0x0000000c) 2394 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV1 0x0 2400 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV2 0x1 2406 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV4 0x2 2412 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV8 0x3 2418 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV16 0x4 2424 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_1 0x5 2430 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_2 0x6 2436 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_3 0x7 2439 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_LSB 4 2441 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_MSB 6 2443 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_WIDTH 3 2445 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_SET_MSK 0x00000070 2447 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_CLR_MSK 0xffffff8f 2449 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_RESET 0x0 2451 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_GET(value) (((value) & 0x00000070) >> 4) 2453 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_SET(value) (((value) << 4) & 0x00000070) 2482 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV1 0x0 2488 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV2 0x1 2494 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV4 0x2 2500 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV8 0x3 2506 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV16 0x4 2512 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_1 0x5 2518 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_2 0x6 2524 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_3 0x7 2527 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_LSB 7 2529 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_MSB 9 2531 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_WIDTH 3 2533 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_SET_MSK 0x00000380 2535 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_CLR_MSK 0xfffffc7f 2537 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_RESET 0x0 2539 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_GET(value) (((value) & 0x00000380) >> 7) 2541 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_SET(value) (((value) << 7) & 0x00000380) 2543 #ifndef __ASSEMBLY__ 2556 uint32_t l3mpclk : 2;
2557 uint32_t l3spclk : 2;
2558 uint32_t l4mpclk : 3;
2559 uint32_t l4spclk : 3;
2568 #define ALT_CLKMGR_MAINPLL_MAINDIV_OFST 0x24 2609 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV1 0x0 2615 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV2 0x1 2621 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV4 0x2 2624 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_LSB 0 2626 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_MSB 1 2628 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_WIDTH 2 2630 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_SET_MSK 0x00000003 2632 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_CLR_MSK 0xfffffffc 2634 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_RESET 0x0 2636 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_GET(value) (((value) & 0x00000003) >> 0) 2638 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_SET(value) (((value) << 0) & 0x00000003) 2661 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV2 0x1 2667 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV4 0x2 2670 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_LSB 2 2672 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_MSB 3 2674 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_WIDTH 2 2676 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_SET_MSK 0x0000000c 2678 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_CLR_MSK 0xfffffff3 2680 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_RESET 0x1 2682 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_GET(value) (((value) & 0x0000000c) >> 2) 2684 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_SET(value) (((value) << 2) & 0x0000000c) 2686 #ifndef __ASSEMBLY__ 2699 uint32_t dbgatclk : 2;
2700 uint32_t dbgclk : 2;
2709 #define ALT_CLKMGR_MAINPLL_DBGDIV_OFST 0x28 2754 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV1 0x0 2760 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV2 0x1 2766 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV4 0x2 2772 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV8 0x3 2778 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV16 0x4 2784 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_1 0x5 2790 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_2 0x6 2796 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_3 0x7 2799 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_LSB 0 2801 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_MSB 2 2803 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_WIDTH 3 2805 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_SET_MSK 0x00000007 2807 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_CLR_MSK 0xfffffff8 2809 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_RESET 0x0 2811 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_GET(value) (((value) & 0x00000007) >> 0) 2813 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_SET(value) (((value) << 0) & 0x00000007) 2815 #ifndef __ASSEMBLY__ 2828 uint32_t traceclk : 3;
2837 #define ALT_CLKMGR_MAINPLL_TRACEDIV_OFST 0x2c 2875 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL 0x0 2881 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_PERIPHPLL 0x1 2884 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_LSB 0 2886 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_MSB 0 2888 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_WIDTH 1 2890 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK 0x00000001 2892 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_CLR_MSK 0xfffffffe 2894 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_RESET 0x0 2896 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_GET(value) (((value) & 0x00000001) >> 0) 2898 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET(value) (((value) << 0) & 0x00000001) 2920 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL 0x0 2926 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_PERIPHPLL 0x1 2929 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_LSB 1 2931 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_MSB 1 2933 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_WIDTH 1 2935 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK 0x00000002 2937 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_CLR_MSK 0xfffffffd 2939 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_RESET 0x0 2941 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_GET(value) (((value) & 0x00000002) >> 1) 2943 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET(value) (((value) << 1) & 0x00000002) 2945 #ifndef __ASSEMBLY__ 2968 #define ALT_CLKMGR_MAINPLL_L4SRC_OFST 0x30 3015 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_E_IDLE 0x0 3021 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_E_ACK_RXD 0x1 3024 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_LSB 0 3026 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_MSB 5 3028 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_WIDTH 6 3030 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_SET_MSK 0x0000003f 3032 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_CLR_MSK 0xffffffc0 3034 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_RESET 0x0 3036 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_GET(value) (((value) & 0x0000003f) >> 0) 3038 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_SET(value) (((value) << 0) & 0x0000003f) 3040 #ifndef __ASSEMBLY__ 3053 const uint32_t outresetack : 6;
3062 #define ALT_CLKMGR_MAINPLL_STAT_OFST 0x34 3064 #ifndef __ASSEMBLY__ 3077 volatile ALT_CLKMGR_MAINPLL_VCO_t vco;
3078 volatile ALT_CLKMGR_MAINPLL_MISC_t misc;
3079 volatile ALT_CLKMGR_MAINPLL_MPUCLK_t mpuclk;
3080 volatile ALT_CLKMGR_MAINPLL_MAINCLK_t mainclk;
3081 volatile ALT_CLKMGR_MAINPLL_DBGATCLK_t dbgatclk;
3082 volatile ALT_CLKMGR_MAINPLL_MAINQSPICLK_t mainqspiclk;
3083 volatile ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_t mainnandsdmmcclk;
3084 volatile ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_t cfgs2fuser0clk;
3085 volatile ALT_CLKMGR_MAINPLL_EN_t en;
3086 volatile ALT_CLKMGR_MAINPLL_MAINDIV_t maindiv;
3087 volatile ALT_CLKMGR_MAINPLL_DBGDIV_t dbgdiv;
3088 volatile ALT_CLKMGR_MAINPLL_TRACEDIV_t tracediv;
3089 volatile ALT_CLKMGR_MAINPLL_L4SRC_t l4src;
3090 volatile ALT_CLKMGR_MAINPLL_STAT_t stat;
3091 volatile uint32_t _pad_0x38_0x40[2];
3099 volatile uint32_t vco;
3100 volatile uint32_t misc;
3101 volatile uint32_t mpuclk;
3102 volatile uint32_t mainclk;
3103 volatile uint32_t dbgatclk;
3104 volatile uint32_t mainqspiclk;
3105 volatile uint32_t mainnandsdmmcclk;
3106 volatile uint32_t cfgs2fuser0clk;
3107 volatile uint32_t en;
3108 volatile uint32_t maindiv;
3109 volatile uint32_t dbgdiv;
3110 volatile uint32_t tracediv;
3111 volatile uint32_t l4src;
3112 volatile uint32_t stat;
3113 volatile uint32_t _pad_0x38_0x40[2];
3161 #define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_LSB 0 3163 #define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_MSB 0 3165 #define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_WIDTH 1 3167 #define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_SET_MSK 0x00000001 3169 #define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_CLR_MSK 0xfffffffe 3171 #define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_RESET 0x1 3173 #define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0) 3175 #define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_SET(value) (((value) << 0) & 0x00000001) 3186 #define ALT_CLKMGR_PERPLL_VCO_EN_LSB 1 3188 #define ALT_CLKMGR_PERPLL_VCO_EN_MSB 1 3190 #define ALT_CLKMGR_PERPLL_VCO_EN_WIDTH 1 3192 #define ALT_CLKMGR_PERPLL_VCO_EN_SET_MSK 0x00000002 3194 #define ALT_CLKMGR_PERPLL_VCO_EN_CLR_MSK 0xfffffffd 3196 #define ALT_CLKMGR_PERPLL_VCO_EN_RESET 0x0 3198 #define ALT_CLKMGR_PERPLL_VCO_EN_GET(value) (((value) & 0x00000002) >> 1) 3200 #define ALT_CLKMGR_PERPLL_VCO_EN_SET(value) (((value) << 1) & 0x00000002) 3211 #define ALT_CLKMGR_PERPLL_VCO_PWRDN_LSB 2 3213 #define ALT_CLKMGR_PERPLL_VCO_PWRDN_MSB 2 3215 #define ALT_CLKMGR_PERPLL_VCO_PWRDN_WIDTH 1 3217 #define ALT_CLKMGR_PERPLL_VCO_PWRDN_SET_MSK 0x00000004 3219 #define ALT_CLKMGR_PERPLL_VCO_PWRDN_CLR_MSK 0xfffffffb 3221 #define ALT_CLKMGR_PERPLL_VCO_PWRDN_RESET 0x1 3223 #define ALT_CLKMGR_PERPLL_VCO_PWRDN_GET(value) (((value) & 0x00000004) >> 2) 3225 #define ALT_CLKMGR_PERPLL_VCO_PWRDN_SET(value) (((value) << 2) & 0x00000004) 3239 #define ALT_CLKMGR_PERPLL_VCO_NUMER_LSB 3 3241 #define ALT_CLKMGR_PERPLL_VCO_NUMER_MSB 15 3243 #define ALT_CLKMGR_PERPLL_VCO_NUMER_WIDTH 13 3245 #define ALT_CLKMGR_PERPLL_VCO_NUMER_SET_MSK 0x0000fff8 3247 #define ALT_CLKMGR_PERPLL_VCO_NUMER_CLR_MSK 0xffff0007 3249 #define ALT_CLKMGR_PERPLL_VCO_NUMER_RESET 0x1 3251 #define ALT_CLKMGR_PERPLL_VCO_NUMER_GET(value) (((value) & 0x0000fff8) >> 3) 3253 #define ALT_CLKMGR_PERPLL_VCO_NUMER_SET(value) (((value) << 3) & 0x0000fff8) 3267 #define ALT_CLKMGR_PERPLL_VCO_DENOM_LSB 16 3269 #define ALT_CLKMGR_PERPLL_VCO_DENOM_MSB 21 3271 #define ALT_CLKMGR_PERPLL_VCO_DENOM_WIDTH 6 3273 #define ALT_CLKMGR_PERPLL_VCO_DENOM_SET_MSK 0x003f0000 3275 #define ALT_CLKMGR_PERPLL_VCO_DENOM_CLR_MSK 0xffc0ffff 3277 #define ALT_CLKMGR_PERPLL_VCO_DENOM_RESET 0x1 3279 #define ALT_CLKMGR_PERPLL_VCO_DENOM_GET(value) (((value) & 0x003f0000) >> 16) 3281 #define ALT_CLKMGR_PERPLL_VCO_DENOM_SET(value) (((value) << 16) & 0x003f0000) 3306 #define ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1 0x0 3312 #define ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2 0x1 3318 #define ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF 0x2 3321 #define ALT_CLKMGR_PERPLL_VCO_PSRC_LSB 22 3323 #define ALT_CLKMGR_PERPLL_VCO_PSRC_MSB 23 3325 #define ALT_CLKMGR_PERPLL_VCO_PSRC_WIDTH 2 3327 #define ALT_CLKMGR_PERPLL_VCO_PSRC_SET_MSK 0x00c00000 3329 #define ALT_CLKMGR_PERPLL_VCO_PSRC_CLR_MSK 0xff3fffff 3331 #define ALT_CLKMGR_PERPLL_VCO_PSRC_RESET 0x0 3333 #define ALT_CLKMGR_PERPLL_VCO_PSRC_GET(value) (((value) & 0x00c00000) >> 22) 3335 #define ALT_CLKMGR_PERPLL_VCO_PSRC_SET(value) (((value) << 22) & 0x00c00000) 3353 #define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_LSB 24 3355 #define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_MSB 24 3357 #define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_WIDTH 1 3359 #define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_SET_MSK 0x01000000 3361 #define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_CLR_MSK 0xfeffffff 3363 #define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_RESET 0x0 3365 #define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_GET(value) (((value) & 0x01000000) >> 24) 3367 #define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_SET(value) (((value) << 24) & 0x01000000) 3394 #define ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB 25 3396 #define ALT_CLKMGR_PERPLL_VCO_OUTRST_MSB 30 3398 #define ALT_CLKMGR_PERPLL_VCO_OUTRST_WIDTH 6 3400 #define ALT_CLKMGR_PERPLL_VCO_OUTRST_SET_MSK 0x7e000000 3402 #define ALT_CLKMGR_PERPLL_VCO_OUTRST_CLR_MSK 0x81ffffff 3404 #define ALT_CLKMGR_PERPLL_VCO_OUTRST_RESET 0x0 3406 #define ALT_CLKMGR_PERPLL_VCO_OUTRST_GET(value) (((value) & 0x7e000000) >> 25) 3408 #define ALT_CLKMGR_PERPLL_VCO_OUTRST_SET(value) (((value) << 25) & 0x7e000000) 3431 #define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_LSB 31 3433 #define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_MSB 31 3435 #define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_WIDTH 1 3437 #define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_SET_MSK 0x80000000 3439 #define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_CLR_MSK 0x7fffffff 3441 #define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_RESET 0x1 3443 #define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_GET(value) (((value) & 0x80000000) >> 31) 3445 #define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_SET(value) (((value) << 31) & 0x80000000) 3447 #ifndef __ASSEMBLY__ 3460 uint32_t bgpwrdn : 1;
3463 uint32_t numer : 13;
3466 uint32_t outresetall : 1;
3467 uint32_t outreset : 6;
3468 uint32_t regextsel : 1;
3476 #define ALT_CLKMGR_PERPLL_VCO_OFST 0x0 3511 #define ALT_CLKMGR_PERPLL_MISC_BWADJEN_LSB 0 3513 #define ALT_CLKMGR_PERPLL_MISC_BWADJEN_MSB 0 3515 #define ALT_CLKMGR_PERPLL_MISC_BWADJEN_WIDTH 1 3517 #define ALT_CLKMGR_PERPLL_MISC_BWADJEN_SET_MSK 0x00000001 3519 #define ALT_CLKMGR_PERPLL_MISC_BWADJEN_CLR_MSK 0xfffffffe 3521 #define ALT_CLKMGR_PERPLL_MISC_BWADJEN_RESET 0x0 3523 #define ALT_CLKMGR_PERPLL_MISC_BWADJEN_GET(value) (((value) & 0x00000001) >> 0) 3525 #define ALT_CLKMGR_PERPLL_MISC_BWADJEN_SET(value) (((value) << 0) & 0x00000001) 3536 #define ALT_CLKMGR_PERPLL_MISC_BWADJ_LSB 1 3538 #define ALT_CLKMGR_PERPLL_MISC_BWADJ_MSB 12 3540 #define ALT_CLKMGR_PERPLL_MISC_BWADJ_WIDTH 12 3542 #define ALT_CLKMGR_PERPLL_MISC_BWADJ_SET_MSK 0x00001ffe 3544 #define ALT_CLKMGR_PERPLL_MISC_BWADJ_CLR_MSK 0xffffe001 3546 #define ALT_CLKMGR_PERPLL_MISC_BWADJ_RESET 0x1 3548 #define ALT_CLKMGR_PERPLL_MISC_BWADJ_GET(value) (((value) & 0x00001ffe) >> 1) 3550 #define ALT_CLKMGR_PERPLL_MISC_BWADJ_SET(value) (((value) << 1) & 0x00001ffe) 3561 #define ALT_CLKMGR_PERPLL_MISC_FASTEN_LSB 13 3563 #define ALT_CLKMGR_PERPLL_MISC_FASTEN_MSB 13 3565 #define ALT_CLKMGR_PERPLL_MISC_FASTEN_WIDTH 1 3567 #define ALT_CLKMGR_PERPLL_MISC_FASTEN_SET_MSK 0x00002000 3569 #define ALT_CLKMGR_PERPLL_MISC_FASTEN_CLR_MSK 0xffffdfff 3571 #define ALT_CLKMGR_PERPLL_MISC_FASTEN_RESET 0x0 3573 #define ALT_CLKMGR_PERPLL_MISC_FASTEN_GET(value) (((value) & 0x00002000) >> 13) 3575 #define ALT_CLKMGR_PERPLL_MISC_FASTEN_SET(value) (((value) << 13) & 0x00002000) 3586 #define ALT_CLKMGR_PERPLL_MISC_SATEN_LSB 14 3588 #define ALT_CLKMGR_PERPLL_MISC_SATEN_MSB 14 3590 #define ALT_CLKMGR_PERPLL_MISC_SATEN_WIDTH 1 3592 #define ALT_CLKMGR_PERPLL_MISC_SATEN_SET_MSK 0x00004000 3594 #define ALT_CLKMGR_PERPLL_MISC_SATEN_CLR_MSK 0xffffbfff 3596 #define ALT_CLKMGR_PERPLL_MISC_SATEN_RESET 0x1 3598 #define ALT_CLKMGR_PERPLL_MISC_SATEN_GET(value) (((value) & 0x00004000) >> 14) 3600 #define ALT_CLKMGR_PERPLL_MISC_SATEN_SET(value) (((value) << 14) & 0x00004000) 3602 #ifndef __ASSEMBLY__ 3615 uint32_t bwadjen : 1;
3616 uint32_t bwadj : 12;
3617 uint32_t fasten : 1;
3627 #define ALT_CLKMGR_PERPLL_MISC_OFST 0x4 3654 #define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_LSB 0 3656 #define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_MSB 8 3658 #define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_WIDTH 9 3660 #define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_SET_MSK 0x000001ff 3662 #define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_CLR_MSK 0xfffffe00 3664 #define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_RESET 0x1 3666 #define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) 3668 #define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_SET(value) (((value) << 0) & 0x000001ff) 3670 #ifndef __ASSEMBLY__ 3692 #define ALT_CLKMGR_PERPLL_EMAC0CLK_OFST 0x8 3719 #define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_LSB 0 3721 #define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_MSB 8 3723 #define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_WIDTH 9 3725 #define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_SET_MSK 0x000001ff 3727 #define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_CLR_MSK 0xfffffe00 3729 #define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_RESET 0x1 3731 #define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) 3733 #define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_SET(value) (((value) << 0) & 0x000001ff) 3735 #ifndef __ASSEMBLY__ 3757 #define ALT_CLKMGR_PERPLL_EMAC1CLK_OFST 0xc 3784 #define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_LSB 0 3786 #define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_MSB 8 3788 #define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_WIDTH 9 3790 #define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_SET_MSK 0x000001ff 3792 #define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_CLR_MSK 0xfffffe00 3794 #define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_RESET 0x1 3796 #define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) 3798 #define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_SET(value) (((value) << 0) & 0x000001ff) 3800 #ifndef __ASSEMBLY__ 3822 #define ALT_CLKMGR_PERPLL_PERQSPICLK_OFST 0x10 3849 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_LSB 0 3851 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_MSB 8 3853 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_WIDTH 9 3855 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_SET_MSK 0x000001ff 3857 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_CLR_MSK 0xfffffe00 3859 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_RESET 0x1 3861 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) 3863 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) 3865 #ifndef __ASSEMBLY__ 3887 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_OFST 0x14 3914 #define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_LSB 0 3916 #define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_MSB 8 3918 #define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_WIDTH 9 3920 #define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_SET_MSK 0x000001ff 3922 #define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_CLR_MSK 0xfffffe00 3924 #define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_RESET 0x1 3926 #define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) 3928 #define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_SET(value) (((value) << 0) & 0x000001ff) 3930 #ifndef __ASSEMBLY__ 3952 #define ALT_CLKMGR_PERPLL_PERBASECLK_OFST 0x18 3981 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_LSB 0 3983 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_MSB 8 3985 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_WIDTH 9 3987 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_SET_MSK 0x000001ff 3989 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_CLR_MSK 0xfffffe00 3991 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_RESET 0x1 3993 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) 3995 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_SET(value) (((value) << 0) & 0x000001ff) 3997 #ifndef __ASSEMBLY__ 4019 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_OFST 0x1c 4061 #define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_LSB 0 4063 #define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_MSB 0 4065 #define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_WIDTH 1 4067 #define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK 0x00000001 4069 #define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_CLR_MSK 0xfffffffe 4071 #define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_RESET 0x1 4073 #define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_GET(value) (((value) & 0x00000001) >> 0) 4075 #define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET(value) (((value) << 0) & 0x00000001) 4086 #define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_LSB 1 4088 #define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_MSB 1 4090 #define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_WIDTH 1 4092 #define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK 0x00000002 4094 #define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_CLR_MSK 0xfffffffd 4096 #define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_RESET 0x1 4098 #define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_GET(value) (((value) & 0x00000002) >> 1) 4100 #define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET(value) (((value) << 1) & 0x00000002) 4111 #define ALT_CLKMGR_PERPLL_EN_USBCLK_LSB 2 4113 #define ALT_CLKMGR_PERPLL_EN_USBCLK_MSB 2 4115 #define ALT_CLKMGR_PERPLL_EN_USBCLK_WIDTH 1 4117 #define ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK 0x00000004 4119 #define ALT_CLKMGR_PERPLL_EN_USBCLK_CLR_MSK 0xfffffffb 4121 #define ALT_CLKMGR_PERPLL_EN_USBCLK_RESET 0x1 4123 #define ALT_CLKMGR_PERPLL_EN_USBCLK_GET(value) (((value) & 0x00000004) >> 2) 4125 #define ALT_CLKMGR_PERPLL_EN_USBCLK_SET(value) (((value) << 2) & 0x00000004) 4136 #define ALT_CLKMGR_PERPLL_EN_SPIMCLK_LSB 3 4138 #define ALT_CLKMGR_PERPLL_EN_SPIMCLK_MSB 3 4140 #define ALT_CLKMGR_PERPLL_EN_SPIMCLK_WIDTH 1 4142 #define ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK 0x00000008 4144 #define ALT_CLKMGR_PERPLL_EN_SPIMCLK_CLR_MSK 0xfffffff7 4146 #define ALT_CLKMGR_PERPLL_EN_SPIMCLK_RESET 0x1 4148 #define ALT_CLKMGR_PERPLL_EN_SPIMCLK_GET(value) (((value) & 0x00000008) >> 3) 4150 #define ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET(value) (((value) << 3) & 0x00000008) 4161 #define ALT_CLKMGR_PERPLL_EN_CAN0CLK_LSB 4 4163 #define ALT_CLKMGR_PERPLL_EN_CAN0CLK_MSB 4 4165 #define ALT_CLKMGR_PERPLL_EN_CAN0CLK_WIDTH 1 4167 #define ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK 0x00000010 4169 #define ALT_CLKMGR_PERPLL_EN_CAN0CLK_CLR_MSK 0xffffffef 4171 #define ALT_CLKMGR_PERPLL_EN_CAN0CLK_RESET 0x1 4173 #define ALT_CLKMGR_PERPLL_EN_CAN0CLK_GET(value) (((value) & 0x00000010) >> 4) 4175 #define ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET(value) (((value) << 4) & 0x00000010) 4186 #define ALT_CLKMGR_PERPLL_EN_CAN1CLK_LSB 5 4188 #define ALT_CLKMGR_PERPLL_EN_CAN1CLK_MSB 5 4190 #define ALT_CLKMGR_PERPLL_EN_CAN1CLK_WIDTH 1 4192 #define ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK 0x00000020 4194 #define ALT_CLKMGR_PERPLL_EN_CAN1CLK_CLR_MSK 0xffffffdf 4196 #define ALT_CLKMGR_PERPLL_EN_CAN1CLK_RESET 0x1 4198 #define ALT_CLKMGR_PERPLL_EN_CAN1CLK_GET(value) (((value) & 0x00000020) >> 5) 4200 #define ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET(value) (((value) << 5) & 0x00000020) 4211 #define ALT_CLKMGR_PERPLL_EN_GPIOCLK_LSB 6 4213 #define ALT_CLKMGR_PERPLL_EN_GPIOCLK_MSB 6 4215 #define ALT_CLKMGR_PERPLL_EN_GPIOCLK_WIDTH 1 4217 #define ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK 0x00000040 4219 #define ALT_CLKMGR_PERPLL_EN_GPIOCLK_CLR_MSK 0xffffffbf 4221 #define ALT_CLKMGR_PERPLL_EN_GPIOCLK_RESET 0x1 4223 #define ALT_CLKMGR_PERPLL_EN_GPIOCLK_GET(value) (((value) & 0x00000040) >> 6) 4225 #define ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET(value) (((value) << 6) & 0x00000040) 4238 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_LSB 7 4240 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_MSB 7 4242 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_WIDTH 1 4244 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK 0x00000080 4246 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_CLR_MSK 0xffffff7f 4248 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_RESET 0x1 4250 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_GET(value) (((value) & 0x00000080) >> 7) 4252 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET(value) (((value) << 7) & 0x00000080) 4263 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_LSB 8 4265 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_MSB 8 4267 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_WIDTH 1 4269 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK 0x00000100 4271 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_CLR_MSK 0xfffffeff 4273 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_RESET 0x1 4275 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_GET(value) (((value) & 0x00000100) >> 8) 4277 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET(value) (((value) << 8) & 0x00000100) 4293 #define ALT_CLKMGR_PERPLL_EN_NANDXCLK_LSB 9 4295 #define ALT_CLKMGR_PERPLL_EN_NANDXCLK_MSB 9 4297 #define ALT_CLKMGR_PERPLL_EN_NANDXCLK_WIDTH 1 4299 #define ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK 0x00000200 4301 #define ALT_CLKMGR_PERPLL_EN_NANDXCLK_CLR_MSK 0xfffffdff 4303 #define ALT_CLKMGR_PERPLL_EN_NANDXCLK_RESET 0x1 4305 #define ALT_CLKMGR_PERPLL_EN_NANDXCLK_GET(value) (((value) & 0x00000200) >> 9) 4307 #define ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET(value) (((value) << 9) & 0x00000200) 4323 #define ALT_CLKMGR_PERPLL_EN_NANDCLK_LSB 10 4325 #define ALT_CLKMGR_PERPLL_EN_NANDCLK_MSB 10 4327 #define ALT_CLKMGR_PERPLL_EN_NANDCLK_WIDTH 1 4329 #define ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK 0x00000400 4331 #define ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK 0xfffffbff 4333 #define ALT_CLKMGR_PERPLL_EN_NANDCLK_RESET 0x1 4335 #define ALT_CLKMGR_PERPLL_EN_NANDCLK_GET(value) (((value) & 0x00000400) >> 10) 4337 #define ALT_CLKMGR_PERPLL_EN_NANDCLK_SET(value) (((value) << 10) & 0x00000400) 4348 #define ALT_CLKMGR_PERPLL_EN_QSPICLK_LSB 11 4350 #define ALT_CLKMGR_PERPLL_EN_QSPICLK_MSB 11 4352 #define ALT_CLKMGR_PERPLL_EN_QSPICLK_WIDTH 1 4354 #define ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK 0x00000800 4356 #define ALT_CLKMGR_PERPLL_EN_QSPICLK_CLR_MSK 0xfffff7ff 4358 #define ALT_CLKMGR_PERPLL_EN_QSPICLK_RESET 0x1 4360 #define ALT_CLKMGR_PERPLL_EN_QSPICLK_GET(value) (((value) & 0x00000800) >> 11) 4362 #define ALT_CLKMGR_PERPLL_EN_QSPICLK_SET(value) (((value) << 11) & 0x00000800) 4364 #ifndef __ASSEMBLY__ 4377 uint32_t emac0clk : 1;
4378 uint32_t emac1clk : 1;
4379 uint32_t usbclk : 1;
4380 uint32_t spimclk : 1;
4381 uint32_t can0clk : 1;
4382 uint32_t can1clk : 1;
4383 uint32_t gpioclk : 1;
4384 uint32_t s2fuser1clk : 1;
4385 uint32_t sdmmcclk : 1;
4386 uint32_t nandxclk : 1;
4387 uint32_t nandclk : 1;
4388 uint32_t qspiclk : 1;
4397 #define ALT_CLKMGR_PERPLL_EN_OFST 0x20 4445 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV1 0x0 4451 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV2 0x1 4457 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV4 0x2 4463 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV8 0x3 4469 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV16 0x4 4475 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_1 0x5 4481 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_2 0x6 4487 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_3 0x7 4490 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_LSB 0 4492 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_MSB 2 4494 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_WIDTH 3 4496 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_SET_MSK 0x00000007 4498 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_CLR_MSK 0xfffffff8 4500 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_RESET 0x0 4502 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_GET(value) (((value) & 0x00000007) >> 0) 4504 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_SET(value) (((value) << 0) & 0x00000007) 4533 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV1 0x0 4539 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV2 0x1 4545 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV4 0x2 4551 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV8 0x3 4557 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV16 0x4 4563 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_1 0x5 4569 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_2 0x6 4575 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_3 0x7 4578 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_LSB 3 4580 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_MSB 5 4582 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_WIDTH 3 4584 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_SET_MSK 0x00000038 4586 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_CLR_MSK 0xffffffc7 4588 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_RESET 0x0 4590 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_GET(value) (((value) & 0x00000038) >> 3) 4592 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_SET(value) (((value) << 3) & 0x00000038) 4621 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV1 0x0 4627 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV2 0x1 4633 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV4 0x2 4639 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV8 0x3 4645 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV16 0x4 4651 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_1 0x5 4657 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_2 0x6 4663 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_3 0x7 4666 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_LSB 6 4668 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_MSB 8 4670 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_WIDTH 3 4672 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_SET_MSK 0x000001c0 4674 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_CLR_MSK 0xfffffe3f 4676 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_RESET 0x0 4678 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_GET(value) (((value) & 0x000001c0) >> 6) 4680 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_SET(value) (((value) << 6) & 0x000001c0) 4709 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV1 0x0 4715 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV2 0x1 4721 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV4 0x2 4727 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV8 0x3 4733 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV16 0x4 4739 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_1 0x5 4745 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_2 0x6 4751 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_3 0x7 4754 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_LSB 9 4756 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_MSB 11 4758 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_WIDTH 3 4760 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_SET_MSK 0x00000e00 4762 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_CLR_MSK 0xfffff1ff 4764 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_RESET 0x0 4766 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_GET(value) (((value) & 0x00000e00) >> 9) 4768 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_SET(value) (((value) << 9) & 0x00000e00) 4770 #ifndef __ASSEMBLY__ 4783 uint32_t usbclk : 3;
4784 uint32_t spimclk : 3;
4785 uint32_t can0clk : 3;
4786 uint32_t can1clk : 3;
4795 #define ALT_CLKMGR_PERPLL_DIV_OFST 0x24 4823 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_LSB 0 4825 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_MSB 23 4827 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_WIDTH 24 4829 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET_MSK 0x00ffffff 4831 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_CLR_MSK 0xff000000 4833 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_RESET 0x1 4835 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_GET(value) (((value) & 0x00ffffff) >> 0) 4837 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(value) (((value) << 0) & 0x00ffffff) 4839 #ifndef __ASSEMBLY__ 4852 uint32_t gpiodbclk : 24;
4861 #define ALT_CLKMGR_PERPLL_GPIODIV_OFST 0x28 4903 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK 0x0 4909 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK 0x1 4915 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK 0x2 4918 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_LSB 0 4920 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_MSB 1 4922 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_WIDTH 2 4924 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_SET_MSK 0x00000003 4926 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_CLR_MSK 0xfffffffc 4928 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_RESET 0x1 4930 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(value) (((value) & 0x00000003) >> 0) 4932 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_SET(value) (((value) << 0) & 0x00000003) 4957 #define ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK 0x0 4963 #define ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK 0x1 4969 #define ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK 0x2 4972 #define ALT_CLKMGR_PERPLL_SRC_NAND_LSB 2 4974 #define ALT_CLKMGR_PERPLL_SRC_NAND_MSB 3 4976 #define ALT_CLKMGR_PERPLL_SRC_NAND_WIDTH 2 4978 #define ALT_CLKMGR_PERPLL_SRC_NAND_SET_MSK 0x0000000c 4980 #define ALT_CLKMGR_PERPLL_SRC_NAND_CLR_MSK 0xfffffff3 4982 #define ALT_CLKMGR_PERPLL_SRC_NAND_RESET 0x1 4984 #define ALT_CLKMGR_PERPLL_SRC_NAND_GET(value) (((value) & 0x0000000c) >> 2) 4986 #define ALT_CLKMGR_PERPLL_SRC_NAND_SET(value) (((value) << 2) & 0x0000000c) 5011 #define ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK 0x0 5017 #define ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK 0x1 5023 #define ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK 0x2 5026 #define ALT_CLKMGR_PERPLL_SRC_QSPI_LSB 4 5028 #define ALT_CLKMGR_PERPLL_SRC_QSPI_MSB 5 5030 #define ALT_CLKMGR_PERPLL_SRC_QSPI_WIDTH 2 5032 #define ALT_CLKMGR_PERPLL_SRC_QSPI_SET_MSK 0x00000030 5034 #define ALT_CLKMGR_PERPLL_SRC_QSPI_CLR_MSK 0xffffffcf 5036 #define ALT_CLKMGR_PERPLL_SRC_QSPI_RESET 0x1 5038 #define ALT_CLKMGR_PERPLL_SRC_QSPI_GET(value) (((value) & 0x00000030) >> 4) 5040 #define ALT_CLKMGR_PERPLL_SRC_QSPI_SET(value) (((value) << 4) & 0x00000030) 5042 #ifndef __ASSEMBLY__ 5066 #define ALT_CLKMGR_PERPLL_SRC_OFST 0x2c 5113 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_E_IDLE 0x0 5119 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_E_ACK_RXD 0x1 5122 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_LSB 0 5124 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_MSB 5 5126 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_WIDTH 6 5128 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_SET_MSK 0x0000003f 5130 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_CLR_MSK 0xffffffc0 5132 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_RESET 0x0 5134 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_GET(value) (((value) & 0x0000003f) >> 0) 5136 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_SET(value) (((value) << 0) & 0x0000003f) 5138 #ifndef __ASSEMBLY__ 5151 const uint32_t outresetack : 6;
5160 #define ALT_CLKMGR_PERPLL_STAT_OFST 0x30 5162 #ifndef __ASSEMBLY__ 5175 volatile ALT_CLKMGR_PERPLL_VCO_t vco;
5176 volatile ALT_CLKMGR_PERPLL_MISC_t misc;
5177 volatile ALT_CLKMGR_PERPLL_EMAC0CLK_t emac0clk;
5178 volatile ALT_CLKMGR_PERPLL_EMAC1CLK_t emac1clk;
5179 volatile ALT_CLKMGR_PERPLL_PERQSPICLK_t perqspiclk;
5180 volatile ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_t pernandsdmmcclk;
5181 volatile ALT_CLKMGR_PERPLL_PERBASECLK_t perbaseclk;
5182 volatile ALT_CLKMGR_PERPLL_S2FUSER1CLK_t s2fuser1clk;
5183 volatile ALT_CLKMGR_PERPLL_EN_t en;
5184 volatile ALT_CLKMGR_PERPLL_DIV_t div;
5185 volatile ALT_CLKMGR_PERPLL_GPIODIV_t gpiodiv;
5186 volatile ALT_CLKMGR_PERPLL_SRC_t src;
5187 volatile ALT_CLKMGR_PERPLL_STAT_t stat;
5188 volatile uint32_t _pad_0x34_0x40[3];
5196 volatile uint32_t vco;
5197 volatile uint32_t misc;
5198 volatile uint32_t emac0clk;
5199 volatile uint32_t emac1clk;
5200 volatile uint32_t perqspiclk;
5201 volatile uint32_t pernandsdmmcclk;
5202 volatile uint32_t perbaseclk;
5203 volatile uint32_t s2fuser1clk;
5204 volatile uint32_t en;
5205 volatile uint32_t div;
5206 volatile uint32_t gpiodiv;
5207 volatile uint32_t src;
5208 volatile uint32_t stat;
5209 volatile uint32_t _pad_0x34_0x40[3];
5257 #define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_LSB 0 5259 #define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_MSB 0 5261 #define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_WIDTH 1 5263 #define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_SET_MSK 0x00000001 5265 #define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_CLR_MSK 0xfffffffe 5267 #define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_RESET 0x1 5269 #define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0) 5271 #define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_SET(value) (((value) << 0) & 0x00000001) 5282 #define ALT_CLKMGR_SDRPLL_VCO_EN_LSB 1 5284 #define ALT_CLKMGR_SDRPLL_VCO_EN_MSB 1 5286 #define ALT_CLKMGR_SDRPLL_VCO_EN_WIDTH 1 5288 #define ALT_CLKMGR_SDRPLL_VCO_EN_SET_MSK 0x00000002 5290 #define ALT_CLKMGR_SDRPLL_VCO_EN_CLR_MSK 0xfffffffd 5292 #define ALT_CLKMGR_SDRPLL_VCO_EN_RESET 0x0 5294 #define ALT_CLKMGR_SDRPLL_VCO_EN_GET(value) (((value) & 0x00000002) >> 1) 5296 #define ALT_CLKMGR_SDRPLL_VCO_EN_SET(value) (((value) << 1) & 0x00000002) 5307 #define ALT_CLKMGR_SDRPLL_VCO_PWRDN_LSB 2 5309 #define ALT_CLKMGR_SDRPLL_VCO_PWRDN_MSB 2 5311 #define ALT_CLKMGR_SDRPLL_VCO_PWRDN_WIDTH 1 5313 #define ALT_CLKMGR_SDRPLL_VCO_PWRDN_SET_MSK 0x00000004 5315 #define ALT_CLKMGR_SDRPLL_VCO_PWRDN_CLR_MSK 0xfffffffb 5317 #define ALT_CLKMGR_SDRPLL_VCO_PWRDN_RESET 0x1 5319 #define ALT_CLKMGR_SDRPLL_VCO_PWRDN_GET(value) (((value) & 0x00000004) >> 2) 5321 #define ALT_CLKMGR_SDRPLL_VCO_PWRDN_SET(value) (((value) << 2) & 0x00000004) 5335 #define ALT_CLKMGR_SDRPLL_VCO_NUMER_LSB 3 5337 #define ALT_CLKMGR_SDRPLL_VCO_NUMER_MSB 15 5339 #define ALT_CLKMGR_SDRPLL_VCO_NUMER_WIDTH 13 5341 #define ALT_CLKMGR_SDRPLL_VCO_NUMER_SET_MSK 0x0000fff8 5343 #define ALT_CLKMGR_SDRPLL_VCO_NUMER_CLR_MSK 0xffff0007 5345 #define ALT_CLKMGR_SDRPLL_VCO_NUMER_RESET 0x1 5347 #define ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(value) (((value) & 0x0000fff8) >> 3) 5349 #define ALT_CLKMGR_SDRPLL_VCO_NUMER_SET(value) (((value) << 3) & 0x0000fff8) 5363 #define ALT_CLKMGR_SDRPLL_VCO_DENOM_LSB 16 5365 #define ALT_CLKMGR_SDRPLL_VCO_DENOM_MSB 21 5367 #define ALT_CLKMGR_SDRPLL_VCO_DENOM_WIDTH 6 5369 #define ALT_CLKMGR_SDRPLL_VCO_DENOM_SET_MSK 0x003f0000 5371 #define ALT_CLKMGR_SDRPLL_VCO_DENOM_CLR_MSK 0xffc0ffff 5373 #define ALT_CLKMGR_SDRPLL_VCO_DENOM_RESET 0x1 5375 #define ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(value) (((value) & 0x003f0000) >> 16) 5377 #define ALT_CLKMGR_SDRPLL_VCO_DENOM_SET(value) (((value) << 16) & 0x003f0000) 5403 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1 0x0 5409 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2 0x1 5415 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF 0x2 5418 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_LSB 22 5420 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_MSB 23 5422 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_WIDTH 2 5424 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_SET_MSK 0x00c00000 5426 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_CLR_MSK 0xff3fffff 5428 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_RESET 0x0 5430 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(value) (((value) & 0x00c00000) >> 22) 5432 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(value) (((value) << 22) & 0x00c00000) 5450 #define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_LSB 24 5452 #define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_MSB 24 5454 #define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_WIDTH 1 5456 #define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET_MSK 0x01000000 5458 #define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_CLR_MSK 0xfeffffff 5460 #define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_RESET 0x0 5462 #define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_GET(value) (((value) & 0x01000000) >> 24) 5464 #define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET(value) (((value) << 24) & 0x01000000) 5491 #define ALT_CLKMGR_SDRPLL_VCO_OUTRST_LSB 25 5493 #define ALT_CLKMGR_SDRPLL_VCO_OUTRST_MSB 30 5495 #define ALT_CLKMGR_SDRPLL_VCO_OUTRST_WIDTH 6 5497 #define ALT_CLKMGR_SDRPLL_VCO_OUTRST_SET_MSK 0x7e000000 5499 #define ALT_CLKMGR_SDRPLL_VCO_OUTRST_CLR_MSK 0x81ffffff 5501 #define ALT_CLKMGR_SDRPLL_VCO_OUTRST_RESET 0x0 5503 #define ALT_CLKMGR_SDRPLL_VCO_OUTRST_GET(value) (((value) & 0x7e000000) >> 25) 5505 #define ALT_CLKMGR_SDRPLL_VCO_OUTRST_SET(value) (((value) << 25) & 0x7e000000) 5528 #define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_LSB 31 5530 #define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_MSB 31 5532 #define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_WIDTH 1 5534 #define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_SET_MSK 0x80000000 5536 #define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_CLR_MSK 0x7fffffff 5538 #define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_RESET 0x1 5540 #define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_GET(value) (((value) & 0x80000000) >> 31) 5542 #define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_SET(value) (((value) << 31) & 0x80000000) 5544 #ifndef __ASSEMBLY__ 5557 uint32_t bgpwrdn : 1;
5560 uint32_t numer : 13;
5563 uint32_t outresetall : 1;
5564 uint32_t outreset : 6;
5565 uint32_t regextsel : 1;
5573 #define ALT_CLKMGR_SDRPLL_VCO_OFST 0x0 5608 #define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_LSB 0 5610 #define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_MSB 0 5612 #define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_WIDTH 1 5614 #define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_SET_MSK 0x00000001 5616 #define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_CLR_MSK 0xfffffffe 5618 #define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_RESET 0x0 5620 #define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_GET(value) (((value) & 0x00000001) >> 0) 5622 #define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_SET(value) (((value) << 0) & 0x00000001) 5633 #define ALT_CLKMGR_SDRPLL_CTL_BWADJ_LSB 1 5635 #define ALT_CLKMGR_SDRPLL_CTL_BWADJ_MSB 12 5637 #define ALT_CLKMGR_SDRPLL_CTL_BWADJ_WIDTH 12 5639 #define ALT_CLKMGR_SDRPLL_CTL_BWADJ_SET_MSK 0x00001ffe 5641 #define ALT_CLKMGR_SDRPLL_CTL_BWADJ_CLR_MSK 0xffffe001 5643 #define ALT_CLKMGR_SDRPLL_CTL_BWADJ_RESET 0x1 5645 #define ALT_CLKMGR_SDRPLL_CTL_BWADJ_GET(value) (((value) & 0x00001ffe) >> 1) 5647 #define ALT_CLKMGR_SDRPLL_CTL_BWADJ_SET(value) (((value) << 1) & 0x00001ffe) 5658 #define ALT_CLKMGR_SDRPLL_CTL_FASTEN_LSB 13 5660 #define ALT_CLKMGR_SDRPLL_CTL_FASTEN_MSB 13 5662 #define ALT_CLKMGR_SDRPLL_CTL_FASTEN_WIDTH 1 5664 #define ALT_CLKMGR_SDRPLL_CTL_FASTEN_SET_MSK 0x00002000 5666 #define ALT_CLKMGR_SDRPLL_CTL_FASTEN_CLR_MSK 0xffffdfff 5668 #define ALT_CLKMGR_SDRPLL_CTL_FASTEN_RESET 0x0 5670 #define ALT_CLKMGR_SDRPLL_CTL_FASTEN_GET(value) (((value) & 0x00002000) >> 13) 5672 #define ALT_CLKMGR_SDRPLL_CTL_FASTEN_SET(value) (((value) << 13) & 0x00002000) 5683 #define ALT_CLKMGR_SDRPLL_CTL_SATEN_LSB 14 5685 #define ALT_CLKMGR_SDRPLL_CTL_SATEN_MSB 14 5687 #define ALT_CLKMGR_SDRPLL_CTL_SATEN_WIDTH 1 5689 #define ALT_CLKMGR_SDRPLL_CTL_SATEN_SET_MSK 0x00004000 5691 #define ALT_CLKMGR_SDRPLL_CTL_SATEN_CLR_MSK 0xffffbfff 5693 #define ALT_CLKMGR_SDRPLL_CTL_SATEN_RESET 0x1 5695 #define ALT_CLKMGR_SDRPLL_CTL_SATEN_GET(value) (((value) & 0x00004000) >> 14) 5697 #define ALT_CLKMGR_SDRPLL_CTL_SATEN_SET(value) (((value) << 14) & 0x00004000) 5699 #ifndef __ASSEMBLY__ 5712 uint32_t bwadjen : 1;
5713 uint32_t bwadj : 12;
5714 uint32_t fasten : 1;
5724 #define ALT_CLKMGR_SDRPLL_CTL_OFST 0x4 5752 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_LSB 0 5754 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_MSB 8 5756 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_WIDTH 9 5758 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET_MSK 0x000001ff 5760 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_CLR_MSK 0xfffffe00 5762 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_RESET 0x1 5764 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) 5766 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) 5785 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_LSB 9 5787 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_MSB 20 5789 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_WIDTH 12 5791 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET_MSK 0x001ffe00 5793 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_CLR_MSK 0xffe001ff 5795 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_RESET 0x0 5797 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9) 5799 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00) 5801 #ifndef __ASSEMBLY__ 5815 uint32_t phase : 12;
5824 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_OFST 0x8 5852 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_LSB 0 5854 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_MSB 8 5856 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_WIDTH 9 5858 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET_MSK 0x000001ff 5860 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_CLR_MSK 0xfffffe00 5862 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_RESET 0x1 5864 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) 5866 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) 5885 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_LSB 9 5887 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_MSB 20 5889 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_WIDTH 12 5891 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET_MSK 0x001ffe00 5893 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_CLR_MSK 0xffe001ff 5895 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_RESET 0x0 5897 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9) 5899 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00) 5901 #ifndef __ASSEMBLY__ 5915 uint32_t phase : 12;
5924 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_OFST 0xc 5952 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_LSB 0 5954 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_MSB 8 5956 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_WIDTH 9 5958 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET_MSK 0x000001ff 5960 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_CLR_MSK 0xfffffe00 5962 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_RESET 0x1 5964 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) 5966 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) 5985 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_LSB 9 5987 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_MSB 20 5989 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_WIDTH 12 5991 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET_MSK 0x001ffe00 5993 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_CLR_MSK 0xffe001ff 5995 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_RESET 0x0 5997 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9) 5999 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00) 6001 #ifndef __ASSEMBLY__ 6015 uint32_t phase : 12;
6024 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_OFST 0x10 6054 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_LSB 0 6056 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_MSB 8 6058 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_WIDTH 9 6060 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET_MSK 0x000001ff 6062 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_CLR_MSK 0xfffffe00 6064 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_RESET 0x1 6066 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) 6068 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET(value) (((value) << 0) & 0x000001ff) 6087 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_LSB 9 6089 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_MSB 20 6091 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_WIDTH 12 6093 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET_MSK 0x001ffe00 6095 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_CLR_MSK 0xffe001ff 6097 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_RESET 0x0 6099 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9) 6101 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00) 6103 #ifndef __ASSEMBLY__ 6117 uint32_t phase : 12;
6126 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_OFST 0x14 6160 #define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_LSB 0 6162 #define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_MSB 0 6164 #define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_WIDTH 1 6166 #define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK 0x00000001 6168 #define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_CLR_MSK 0xfffffffe 6170 #define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_RESET 0x1 6172 #define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_GET(value) (((value) & 0x00000001) >> 0) 6174 #define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET(value) (((value) << 0) & 0x00000001) 6185 #define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_LSB 1 6187 #define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_MSB 1 6189 #define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_WIDTH 1 6191 #define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK 0x00000002 6193 #define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_CLR_MSK 0xfffffffd 6195 #define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_RESET 0x1 6197 #define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_GET(value) (((value) & 0x00000002) >> 1) 6199 #define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET(value) (((value) << 1) & 0x00000002) 6210 #define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_LSB 2 6212 #define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_MSB 2 6214 #define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_WIDTH 1 6216 #define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK 0x00000004 6218 #define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_CLR_MSK 0xfffffffb 6220 #define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_RESET 0x1 6222 #define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_GET(value) (((value) & 0x00000004) >> 2) 6224 #define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET(value) (((value) << 2) & 0x00000004) 6237 #define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_LSB 3 6239 #define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_MSB 3 6241 #define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_WIDTH 1 6243 #define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK 0x00000008 6245 #define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_CLR_MSK 0xfffffff7 6247 #define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_RESET 0x1 6249 #define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_GET(value) (((value) & 0x00000008) >> 3) 6251 #define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET(value) (((value) << 3) & 0x00000008) 6253 #ifndef __ASSEMBLY__ 6266 uint32_t ddrdqsclk : 1;
6267 uint32_t ddr2xdqsclk : 1;
6268 uint32_t ddrdqclk : 1;
6269 uint32_t s2fuser2clk : 1;
6278 #define ALT_CLKMGR_SDRPLL_EN_OFST 0x18 6325 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_E_IDLE 0x0 6331 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_E_ACK_RXD 0x1 6334 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_LSB 0 6336 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_MSB 5 6338 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_WIDTH 6 6340 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_SET_MSK 0x0000003f 6342 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_CLR_MSK 0xffffffc0 6344 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_RESET 0x0 6346 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_GET(value) (((value) & 0x0000003f) >> 0) 6348 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_SET(value) (((value) << 0) & 0x0000003f) 6350 #ifndef __ASSEMBLY__ 6363 const uint32_t outresetack : 6;
6372 #define ALT_CLKMGR_SDRPLL_STAT_OFST 0x1c 6374 #ifndef __ASSEMBLY__ 6387 volatile ALT_CLKMGR_SDRPLL_VCO_t vco;
6388 volatile ALT_CLKMGR_SDRPLL_CTL_t ctrl;
6389 volatile ALT_CLKMGR_SDRPLL_DDRDQSCLK_t ddrdqsclk;
6390 volatile ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_t ddr2xdqsclk;
6391 volatile ALT_CLKMGR_SDRPLL_DDRDQCLK_t ddrdqclk;
6392 volatile ALT_CLKMGR_SDRPLL_S2FUSER2CLK_t s2fuser2clk;
6393 volatile ALT_CLKMGR_SDRPLL_EN_t en;
6394 volatile ALT_CLKMGR_SDRPLL_STAT_t stat;
6402 volatile uint32_t vco;
6403 volatile uint32_t ctrl;
6404 volatile uint32_t ddrdqsclk;
6405 volatile uint32_t ddr2xdqsclk;
6406 volatile uint32_t ddrdqclk;
6407 volatile uint32_t s2fuser2clk;
6408 volatile uint32_t en;
6409 volatile uint32_t stat;
6417 #ifndef __ASSEMBLY__ 6430 volatile ALT_CLKMGR_CTL_t ctrl;
6431 volatile ALT_CLKMGR_BYPASS_t bypass;
6432 volatile ALT_CLKMGR_INTER_t inter;
6433 volatile ALT_CLKMGR_INTREN_t intren;
6434 volatile ALT_CLKMGR_DBCTL_t dbctrl;
6435 volatile ALT_CLKMGR_STAT_t stat;
6436 volatile uint32_t _pad_0x18_0x3f[10];
6437 volatile ALT_CLKMGR_MAINPLL_t mainpllgrp;
6438 volatile ALT_CLKMGR_PERPLL_t perpllgrp;
6439 volatile ALT_CLKMGR_SDRPLL_t sdrpllgrp;
6440 volatile uint32_t _pad_0xe0_0x200[72];
6448 volatile uint32_t ctrl;
6449 volatile uint32_t bypass;
6450 volatile uint32_t inter;
6451 volatile uint32_t intren;
6452 volatile uint32_t dbctrl;
6453 volatile uint32_t stat;
6454 volatile uint32_t _pad_0x18_0x3f[10];
6455 volatile ALT_CLKMGR_MAINPLL_raw_t mainpllgrp;
6456 volatile ALT_CLKMGR_PERPLL_raw_t perpllgrp;
6457 volatile ALT_CLKMGR_SDRPLL_raw_t sdrpllgrp;
6458 volatile uint32_t _pad_0xe0_0x200[72];
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