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RTEMS 6.1
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Information Related to a Zilog Z8530 SCC Chip. More...
Go to the source code of this file.
Macros | |
| #define | VOL8(ptr) ((volatile uint8_t *)(ptr)) |
| #define | Z8x30_STATE0 |
| #define | Z8x30_WRITE_CONTROL(z8530, reg, data) |
| #define | Z8x30_READ_CONTROL(z8530, reg, data) |
| #define | Z8x30_WRITE_DATA(z8530, data) *(VOL8(z8530)) = (data); |
| #define | Z8x30_READ_DATA(z8530, data) (data) = *(VOL8(z8530)); |
| #define | RR_0_TX_BUFFER_EMPTY 0x04 |
| #define | RR_0_RX_DATA_AVAILABLE 0x01 |
| #define | RR_0 0x00 |
| #define | RR_1 0x01 |
| #define | RR_2 0x02 |
| #define | RR_3 0x03 |
| #define | RR_4 0x04 |
| #define | RR_5 0x05 |
| #define | RR_6 0x06 |
| #define | RR_7 0x07 |
| #define | RR_8 0x08 |
| #define | RR_9 0x09 |
| #define | RR_10 0x0A |
| #define | RR_11 0x0B |
| #define | RR_12 0x0C |
| #define | RR_13 0x0D |
| #define | RR_14 0x0E |
| #define | RR_15 0x0F |
| #define | WR_0 0x00 |
| #define | WR_1 0x01 |
| #define | WR_2 0x02 |
| #define | WR_3 0x03 |
| #define | WR_4 0x04 |
| #define | WR_5 0x05 |
| #define | WR_6 0x06 |
| #define | WR_7 0x07 |
| #define | WR_8 0x08 |
| #define | WR_9 0x09 |
| #define | WR_10 0x0A |
| #define | WR_11 0x0B |
| #define | WR_12 0x0C |
| #define | WR_13 0x0D |
| #define | WR_14 0x0E |
| #define | WR_15 0x0F |
Information Related to a Zilog Z8530 SCC Chip.
This include file defines information related to a Zilog Z8530 SCC Chip. It is a IO mapped part.
| #define Z8x30_READ_CONTROL | ( | z8530, | |
| reg, | |||
| data | |||
| ) |
| #define Z8x30_STATE0 |
| #define Z8x30_WRITE_CONTROL | ( | z8530, | |
| reg, | |||
| data | |||
| ) |