RTEMS 6.1
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Data Fields
TTCAN_TypeDef Struct Reference
CMSIS_Device » Stm32h723xx | CMSIS_Device » Stm32h725xx | CMSIS_Device » Stm32h730xx | CMSIS_Device » Stm32h730xxQ | CMSIS_Device » Stm32h733xx | CMSIS_Device » Stm32h735xx | CMSIS_Device » Stm32h742xx | CMSIS_Device » Stm32h743xx | CMSIS_Device » Stm32h745xg | CMSIS_Device » Stm32h745xx | CMSIS_Device » Stm32h747xg | CMSIS_Device » Stm32h747xx | CMSIS_Device » Stm32h750xx | CMSIS_Device » Stm32h753xx | CMSIS_Device » Stm32h755xx | CMSIS_Device » Stm32h757xx | CMSIS_Device » Stm32h7a3xx | CMSIS_Device » Stm32h7a3xxq | CMSIS_Device » Stm32h7b0xx | CMSIS_Device » Stm32h7b0xxQ | CMSIS_Device » Stm32h7b3xx | CMSIS_Device » Stm32h7b3xxq » Peripheral_registers_structures

TTFD Controller Area Network. More...

#include <stm32h723xx.h>

Data Fields

__IO uint32_t TTTMC
 
__IO uint32_t TTRMC
 
__IO uint32_t TTOCF
 
__IO uint32_t TTMLM
 
__IO uint32_t TURCF
 
__IO uint32_t TTOCN
 
__IO uint32_t TTGTP
 
__IO uint32_t TTTMK
 
__IO uint32_t TTIR
 
__IO uint32_t TTIE
 
__IO uint32_t TTILS
 
__IO uint32_t TTOST
 
__IO uint32_t TURNA
 
__IO uint32_t TTLGT
 
__IO uint32_t TTCTC
 
__IO uint32_t TTCPT
 
__IO uint32_t TTCSM
 
__IO uint32_t RESERVED1 [111]
 
__IO uint32_t TTTS
 

Detailed Description

TTFD Controller Area Network.

Field Documentation

◆ RESERVED1

__IO uint32_t TTCAN_TypeDef::RESERVED1

Reserved, 0x144 - 0x2FC

◆ TTCPT

__IO uint32_t TTCAN_TypeDef::TTCPT

TT Capture Time register, Address offset: 0x13C

◆ TTCSM

__IO uint32_t TTCAN_TypeDef::TTCSM

TT Cycle Sync Mark register, Address offset: 0x140

◆ TTCTC

__IO uint32_t TTCAN_TypeDef::TTCTC

TT Cycle Time and Count register, Address offset: 0x138

◆ TTGTP

__IO uint32_t TTCAN_TypeDef::TTGTP

TT Global Time Preset register, Address offset: 0x118

◆ TTIE

__IO uint32_t TTCAN_TypeDef::TTIE

TT Interrupt Enable register, Address offset: 0x124

◆ TTILS

__IO uint32_t TTCAN_TypeDef::TTILS

TT Interrupt Line Select register, Address offset: 0x128

◆ TTIR

__IO uint32_t TTCAN_TypeDef::TTIR

TT Interrupt register, Address offset: 0x120

◆ TTLGT

__IO uint32_t TTCAN_TypeDef::TTLGT

TT Local and Global Time register, Address offset: 0x134

◆ TTMLM

__IO uint32_t TTCAN_TypeDef::TTMLM

TT Matrix Limits register, Address offset: 0x10C

◆ TTOCF

__IO uint32_t TTCAN_TypeDef::TTOCF

TT Operation Configuration register, Address offset: 0x108

◆ TTOCN

__IO uint32_t TTCAN_TypeDef::TTOCN

TT Operation Control register, Address offset: 0x114

◆ TTOST

__IO uint32_t TTCAN_TypeDef::TTOST

TT Operation Status register, Address offset: 0x12C

◆ TTRMC

__IO uint32_t TTCAN_TypeDef::TTRMC

TT Reference Message Configuration register, Address offset: 0x104

◆ TTTMC

__IO uint32_t TTCAN_TypeDef::TTTMC

TT Trigger Memory Configuration register, Address offset: 0x100

◆ TTTMK

__IO uint32_t TTCAN_TypeDef::TTTMK

TT Time Mark register, Address offset: 0x11C

◆ TTTS

__IO uint32_t TTCAN_TypeDef::TTTS

TT Trigger Select register, Address offset: 0x300

◆ TURCF

__IO uint32_t TTCAN_TypeDef::TURCF

TUR Configuration register, Address offset: 0x110

◆ TURNA

__IO uint32_t TTCAN_TypeDef::TURNA

TT TUR Numerator Actual register, Address offset: 0x130

The documentation for this struct was generated from the following files:
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