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RTEMS 6.1
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RTEMS 6.1
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Single Wire Protocol Master Interface SPWMI. More...
#include <stm32h723xx.h>
Data Fields | |
| __IO uint32_t | CR |
| __IO uint32_t | BRR |
| uint32_t | RESERVED1 |
| __IO uint32_t | ISR |
| __IO uint32_t | ICR |
| __IO uint32_t | IER |
| __IO uint32_t | RFL |
| __IO uint32_t | TDR |
| __IO uint32_t | RDR |
| __IO uint32_t | OR |
Single Wire Protocol Master Interface SPWMI.
| __IO uint32_t SWPMI_TypeDef::BRR |
SWPMI bitrate register, Address offset: 0x04
| __IO uint32_t SWPMI_TypeDef::CR |
SWPMI Configuration/Control register, Address offset: 0x00
| __IO uint32_t SWPMI_TypeDef::ICR |
SWPMI Interrupt Flag Clear register, Address offset: 0x10
| __IO uint32_t SWPMI_TypeDef::IER |
SWPMI Interrupt Enable register, Address offset: 0x14
| __IO uint32_t SWPMI_TypeDef::ISR |
SWPMI Interrupt and Status register, Address offset: 0x0C
| __IO uint32_t SWPMI_TypeDef::OR |
SWPMI Option register, Address offset: 0x24
| __IO uint32_t SWPMI_TypeDef::RDR |
SWPMI Receive data register, Address offset: 0x20
| uint32_t SWPMI_TypeDef::RESERVED1 |
Reserved, 0x08
| __IO uint32_t SWPMI_TypeDef::RFL |
SWPMI Receive Frame Length register, Address offset: 0x18
| __IO uint32_t SWPMI_TypeDef::TDR |
SWPMI Transmit data register, Address offset: 0x1C
1.9.6