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RTEMS 6.1
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Rtc hardware registers. More...
#include <component_rtc.h>
Data Fields | |
| __IO uint32_t | RTC_CR |
| (Rtc Offset: 0x00) Control Register | |
| __IO uint32_t | RTC_MR |
| (Rtc Offset: 0x04) Mode Register | |
| __IO uint32_t | RTC_TIMR |
| (Rtc Offset: 0x08) Time Register | |
| __IO uint32_t | RTC_CALR |
| (Rtc Offset: 0x0C) Calendar Register | |
| __IO uint32_t | RTC_TIMALR |
| (Rtc Offset: 0x10) Time Alarm Register | |
| __IO uint32_t | RTC_CALALR |
| (Rtc Offset: 0x14) Calendar Alarm Register | |
| __I uint32_t | RTC_SR |
| (Rtc Offset: 0x18) Status Register | |
| __O uint32_t | RTC_SCCR |
| (Rtc Offset: 0x1C) Status Clear Command Register | |
| __O uint32_t | RTC_IER |
| (Rtc Offset: 0x20) Interrupt Enable Register | |
| __O uint32_t | RTC_IDR |
| (Rtc Offset: 0x24) Interrupt Disable Register | |
| __I uint32_t | RTC_IMR |
| (Rtc Offset: 0x28) Interrupt Mask Register | |
| __I uint32_t | RTC_VER |
| (Rtc Offset: 0x2C) Valid Entry Register | |
| __I uint32_t | Reserved1 [45] |
| __IO uint32_t | RTC_WPMR |
| (Rtc Offset: 0xE4) Write Protection Mode Register | |
| __I uint32_t | Reserved2 [5] |
| __I uint32_t | RTC_VERSION |
| (Rtc Offset: 0xFC) Version Register | |
Rtc hardware registers.