RTEMS 6.1
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Data Fields
QUADSPI_TypeDef Struct Reference
CMSIS_Device » Stm32h723xx | CMSIS_Device » Stm32h725xx | CMSIS_Device » Stm32h730xx | CMSIS_Device » Stm32h730xxQ | CMSIS_Device » Stm32h733xx | CMSIS_Device » Stm32h735xx | CMSIS_Device » Stm32h742xx | CMSIS_Device » Stm32h743xx | CMSIS_Device » Stm32h745xg | CMSIS_Device » Stm32h745xx | CMSIS_Device » Stm32h747xg | CMSIS_Device » Stm32h747xx | CMSIS_Device » Stm32h750xx | CMSIS_Device » Stm32h753xx | CMSIS_Device » Stm32h755xx | CMSIS_Device » Stm32h757xx | CMSIS_Device » Stm32h7a3xx | CMSIS_Device » Stm32h7a3xxq | CMSIS_Device » Stm32h7b0xx | CMSIS_Device » Stm32h7b0xxQ | CMSIS_Device » Stm32h7b3xx | CMSIS_Device » Stm32h7b3xxq » Peripheral_registers_structures

QUAD Serial Peripheral Interface. More...

#include <stm32h742xx.h>

Data Fields

__IO uint32_t CR
 
__IO uint32_t DCR
 
__IO uint32_t SR
 
__IO uint32_t FCR
 
__IO uint32_t DLR
 
__IO uint32_t CCR
 
__IO uint32_t AR
 
__IO uint32_t ABR
 
__IO uint32_t DR
 
__IO uint32_t PSMKR
 
__IO uint32_t PSMAR
 
__IO uint32_t PIR
 
__IO uint32_t LPTR
 

Detailed Description

QUAD Serial Peripheral Interface.

Field Documentation

◆ ABR

__IO uint32_t QUADSPI_TypeDef::ABR

QUADSPI Alternate Bytes register, Address offset: 0x1C

◆ AR

__IO uint32_t QUADSPI_TypeDef::AR

QUADSPI Address register, Address offset: 0x18

◆ CCR

__IO uint32_t QUADSPI_TypeDef::CCR

QUADSPI Communication Configuration register, Address offset: 0x14

◆ CR

__IO uint32_t QUADSPI_TypeDef::CR

QUADSPI Control register, Address offset: 0x00

◆ DCR

__IO uint32_t QUADSPI_TypeDef::DCR

QUADSPI Device Configuration register, Address offset: 0x04

◆ DLR

__IO uint32_t QUADSPI_TypeDef::DLR

QUADSPI Data Length register, Address offset: 0x10

◆ DR

__IO uint32_t QUADSPI_TypeDef::DR

QUADSPI Data register, Address offset: 0x20

◆ FCR

__IO uint32_t QUADSPI_TypeDef::FCR

QUADSPI Flag Clear register, Address offset: 0x0C

◆ LPTR

__IO uint32_t QUADSPI_TypeDef::LPTR

QUADSPI Low Power Timeout register, Address offset: 0x30

◆ PIR

__IO uint32_t QUADSPI_TypeDef::PIR

QUADSPI Polling Interval register, Address offset: 0x2C

◆ PSMAR

__IO uint32_t QUADSPI_TypeDef::PSMAR

QUADSPI Polling Status Match register, Address offset: 0x28

◆ PSMKR

__IO uint32_t QUADSPI_TypeDef::PSMKR

QUADSPI Polling Status Mask register, Address offset: 0x24

◆ SR

__IO uint32_t QUADSPI_TypeDef::SR

QUADSPI Status register, Address offset: 0x08

The documentation for this struct was generated from the following files:
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