RTEMS 6.1
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Data Fields
PSSI_TypeDef Struct Reference
CMSIS_Device » Stm32h723xx | CMSIS_Device » Stm32h725xx | CMSIS_Device » Stm32h730xx | CMSIS_Device » Stm32h730xxQ | CMSIS_Device » Stm32h733xx | CMSIS_Device » Stm32h735xx | CMSIS_Device » Stm32h742xx | CMSIS_Device » Stm32h743xx | CMSIS_Device » Stm32h745xg | CMSIS_Device » Stm32h745xx | CMSIS_Device » Stm32h747xg | CMSIS_Device » Stm32h747xx | CMSIS_Device » Stm32h750xx | CMSIS_Device » Stm32h753xx | CMSIS_Device » Stm32h755xx | CMSIS_Device » Stm32h757xx | CMSIS_Device » Stm32h7a3xx | CMSIS_Device » Stm32h7a3xxq | CMSIS_Device » Stm32h7b0xx | CMSIS_Device » Stm32h7b0xxQ | CMSIS_Device » Stm32h7b3xx | CMSIS_Device » Stm32h7b3xxq » Peripheral_registers_structures

PSSI. More...

#include <stm32h723xx.h>

Data Fields

__IO uint32_t CR
 
__IO uint32_t SR
 
__IO uint32_t RIS
 
__IO uint32_t IER
 
__IO uint32_t MIS
 
__IO uint32_t ICR
 
__IO uint32_t RESERVED1 [4]
 
__IO uint32_t DR
 
__IO uint32_t RESERVED2 [241]
 
__IO uint32_t HWCFGR
 
__IO uint32_t VERR
 
__IO uint32_t IPIDR
 
__IO uint32_t SIDR
 

Detailed Description

PSSI.

Field Documentation

◆ CR

__IO uint32_t PSSI_TypeDef::CR

PSSI control register 1, Address offset: 0x000

◆ DR

__IO uint32_t PSSI_TypeDef::DR

PSSI data register, Address offset: 0x028

◆ HWCFGR

__IO uint32_t PSSI_TypeDef::HWCFGR

PSSI IP HW configuration register, Address offset: 0x3F0

◆ ICR

__IO uint32_t PSSI_TypeDef::ICR

PSSI interrupt clear register, Address offset: 0x014

◆ IER

__IO uint32_t PSSI_TypeDef::IER

PSSI interrupt enable register, Address offset: 0x00C

◆ IPIDR

__IO uint32_t PSSI_TypeDef::IPIDR

PSSI IP ID register, Address offset: 0x3F8

◆ MIS

__IO uint32_t PSSI_TypeDef::MIS

PSSI masked interrupt status register, Address offset: 0x010

◆ RESERVED1

__IO uint32_t PSSI_TypeDef::RESERVED1

Reserved, 0x018 - 0x024

◆ RESERVED2

__IO uint32_t PSSI_TypeDef::RESERVED2

Reserved, 0x02C - 0x3EC

◆ RIS

__IO uint32_t PSSI_TypeDef::RIS

PSSI raw interrupt status register, Address offset: 0x008

◆ SIDR

__IO uint32_t PSSI_TypeDef::SIDR

PSSI SIZE ID register, Address offset: 0x3FC

◆ SR

__IO uint32_t PSSI_TypeDef::SR

PSSI status register, Address offset: 0x004

◆ VERR

__IO uint32_t PSSI_TypeDef::VERR

PSSI IP version register, Address offset: 0x3F4

The documentation for this struct was generated from the following files:
Generated by doxygen 1.9.6