RTEMS 6.1
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Data Fields
LTDC_TypeDef Struct Reference
CMSIS_Device » Stm32h723xx | CMSIS_Device » Stm32h725xx | CMSIS_Device » Stm32h730xx | CMSIS_Device » Stm32h730xxQ | CMSIS_Device » Stm32h733xx | CMSIS_Device » Stm32h735xx | CMSIS_Device » Stm32h742xx | CMSIS_Device » Stm32h743xx | CMSIS_Device » Stm32h745xg | CMSIS_Device » Stm32h745xx | CMSIS_Device » Stm32h747xg | CMSIS_Device » Stm32h747xx | CMSIS_Device » Stm32h750xx | CMSIS_Device » Stm32h753xx | CMSIS_Device » Stm32h755xx | CMSIS_Device » Stm32h757xx | CMSIS_Device » Stm32h7a3xx | CMSIS_Device » Stm32h7a3xxq | CMSIS_Device » Stm32h7b0xx | CMSIS_Device » Stm32h7b0xxQ | CMSIS_Device » Stm32h7b3xx | CMSIS_Device » Stm32h7b3xxq » Peripheral_registers_structures

LCD-TFT Display Controller. More...

#include <stm32h723xx.h>

Data Fields

uint32_t RESERVED0 [2]
 
__IO uint32_t SSCR
 
__IO uint32_t BPCR
 
__IO uint32_t AWCR
 
__IO uint32_t TWCR
 
__IO uint32_t GCR
 
uint32_t RESERVED1 [2]
 
__IO uint32_t SRCR
 
uint32_t RESERVED2 [1]
 
__IO uint32_t BCCR
 
uint32_t RESERVED3 [1]
 
__IO uint32_t IER
 
__IO uint32_t ISR
 
__IO uint32_t ICR
 
__IO uint32_t LIPCR
 
__IO uint32_t CPSR
 
__IO uint32_t CDSR
 

Detailed Description

LCD-TFT Display Controller.

Field Documentation

◆ AWCR

__IO uint32_t LTDC_TypeDef::AWCR

LTDC Active Width Configuration Register, Address offset: 0x10

◆ BCCR

__IO uint32_t LTDC_TypeDef::BCCR

LTDC Background Color Configuration Register, Address offset: 0x2C

◆ BPCR

__IO uint32_t LTDC_TypeDef::BPCR

LTDC Back Porch Configuration Register, Address offset: 0x0C

◆ CDSR

__IO uint32_t LTDC_TypeDef::CDSR

LTDC Current Display Status Register, Address offset: 0x48

◆ CPSR

__IO uint32_t LTDC_TypeDef::CPSR

LTDC Current Position Status Register, Address offset: 0x44

◆ GCR

__IO uint32_t LTDC_TypeDef::GCR

LTDC Global Control Register, Address offset: 0x18

◆ ICR

__IO uint32_t LTDC_TypeDef::ICR

LTDC Interrupt Clear Register, Address offset: 0x3C

◆ IER

__IO uint32_t LTDC_TypeDef::IER

LTDC Interrupt Enable Register, Address offset: 0x34

◆ ISR

__IO uint32_t LTDC_TypeDef::ISR

LTDC Interrupt Status Register, Address offset: 0x38

◆ LIPCR

__IO uint32_t LTDC_TypeDef::LIPCR

LTDC Line Interrupt Position Configuration Register, Address offset: 0x40

◆ RESERVED0

uint32_t LTDC_TypeDef::RESERVED0

Reserved, 0x00-0x04

◆ RESERVED1

uint32_t LTDC_TypeDef::RESERVED1

Reserved, 0x1C-0x20

◆ RESERVED2

uint32_t LTDC_TypeDef::RESERVED2

Reserved, 0x28

◆ RESERVED3

uint32_t LTDC_TypeDef::RESERVED3

Reserved, 0x30

◆ SRCR

__IO uint32_t LTDC_TypeDef::SRCR

LTDC Shadow Reload Configuration Register, Address offset: 0x24

◆ SSCR

__IO uint32_t LTDC_TypeDef::SSCR

LTDC Synchronization Size Configuration Register, Address offset: 0x08

◆ TWCR

__IO uint32_t LTDC_TypeDef::TWCR

LTDC Total Width Configuration Register, Address offset: 0x14

The documentation for this struct was generated from the following files:
Generated by doxygen 1.9.6