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RTEMS 6.1
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RTEMS 6.1
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LCD-TFT Display layer x Controller. More...
#include <stm32h723xx.h>
Data Fields | |
| __IO uint32_t | CR |
| __IO uint32_t | WHPCR |
| __IO uint32_t | WVPCR |
| __IO uint32_t | CKCR |
| __IO uint32_t | PFCR |
| __IO uint32_t | CACR |
| __IO uint32_t | DCCR |
| __IO uint32_t | BFCR |
| uint32_t | RESERVED0 [2] |
| __IO uint32_t | CFBAR |
| __IO uint32_t | CFBLR |
| __IO uint32_t | CFBLNR |
| uint32_t | RESERVED1 [3] |
| __IO uint32_t | CLUTWR |
LCD-TFT Display layer x Controller.
| __IO uint32_t LTDC_Layer_TypeDef::BFCR |
LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0
| __IO uint32_t LTDC_Layer_TypeDef::CACR |
LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98
| __IO uint32_t LTDC_Layer_TypeDef::CFBAR |
LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC
| __IO uint32_t LTDC_Layer_TypeDef::CFBLNR |
LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4
| __IO uint32_t LTDC_Layer_TypeDef::CFBLR |
LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0
| __IO uint32_t LTDC_Layer_TypeDef::CKCR |
LTDC Layerx Color Keying Configuration Register Address offset: 0x90
| __IO uint32_t LTDC_Layer_TypeDef::CLUTWR |
LTDC Layerx CLUT Write Register Address offset: 0x144
| __IO uint32_t LTDC_Layer_TypeDef::CR |
LTDC Layerx Control Register Address offset: 0x84
| __IO uint32_t LTDC_Layer_TypeDef::DCCR |
LTDC Layerx Default Color Configuration Register Address offset: 0x9C
| __IO uint32_t LTDC_Layer_TypeDef::PFCR |
LTDC Layerx Pixel Format Configuration Register Address offset: 0x94
| uint32_t LTDC_Layer_TypeDef::RESERVED0 |
Reserved
| uint32_t LTDC_Layer_TypeDef::RESERVED1 |
Reserved
| __IO uint32_t LTDC_Layer_TypeDef::WHPCR |
LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88
| __IO uint32_t LTDC_Layer_TypeDef::WVPCR |
LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C
1.9.6