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RTEMS 6.1
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Isi hardware registers. More...
#include <component_isi.h>
Data Fields | |
| __IO uint32_t | ISI_CFG1 |
| (Isi Offset: 0x00) ISI Configuration 1 Register | |
| __IO uint32_t | ISI_CFG2 |
| (Isi Offset: 0x04) ISI Configuration 2 Register | |
| __IO uint32_t | ISI_PSIZE |
| (Isi Offset: 0x08) ISI Preview Size Register | |
| __IO uint32_t | ISI_PDECF |
| (Isi Offset: 0x0C) ISI Preview Decimation Factor Register | |
| __IO uint32_t | ISI_Y2R_SET0 |
| (Isi Offset: 0x10) ISI Color Space Conversion YCrCb To RGB Set 0 Register | |
| __IO uint32_t | ISI_Y2R_SET1 |
| (Isi Offset: 0x14) ISI Color Space Conversion YCrCb To RGB Set 1 Register | |
| __IO uint32_t | ISI_R2Y_SET0 |
| (Isi Offset: 0x18) ISI Color Space Conversion RGB To YCrCb Set 0 Register | |
| __IO uint32_t | ISI_R2Y_SET1 |
| (Isi Offset: 0x1C) ISI Color Space Conversion RGB To YCrCb Set 1 Register | |
| __IO uint32_t | ISI_R2Y_SET2 |
| (Isi Offset: 0x20) ISI Color Space Conversion RGB To YCrCb Set 2 Register | |
| __O uint32_t | ISI_CR |
| (Isi Offset: 0x24) ISI Control Register | |
| __I uint32_t | ISI_SR |
| (Isi Offset: 0x28) ISI Status Register | |
| __O uint32_t | ISI_IER |
| (Isi Offset: 0x2C) ISI Interrupt Enable Register | |
| __O uint32_t | ISI_IDR |
| (Isi Offset: 0x30) ISI Interrupt Disable Register | |
| __I uint32_t | ISI_IMR |
| (Isi Offset: 0x34) ISI Interrupt Mask Register | |
| __O uint32_t | ISI_DMA_CHER |
| (Isi Offset: 0x38) DMA Channel Enable Register | |
| __O uint32_t | ISI_DMA_CHDR |
| (Isi Offset: 0x3C) DMA Channel Disable Register | |
| __I uint32_t | ISI_DMA_CHSR |
| (Isi Offset: 0x40) DMA Channel Status Register | |
| __IO uint32_t | ISI_DMA_P_ADDR |
| (Isi Offset: 0x44) DMA Preview Base Address Register | |
| __IO uint32_t | ISI_DMA_P_CTRL |
| (Isi Offset: 0x48) DMA Preview Control Register | |
| __IO uint32_t | ISI_DMA_P_DSCR |
| (Isi Offset: 0x4C) DMA Preview Descriptor Address Register | |
| __IO uint32_t | ISI_DMA_C_ADDR |
| (Isi Offset: 0x50) DMA Codec Base Address Register | |
| __IO uint32_t | ISI_DMA_C_CTRL |
| (Isi Offset: 0x54) DMA Codec Control Register | |
| __IO uint32_t | ISI_DMA_C_DSCR |
| (Isi Offset: 0x58) DMA Codec Descriptor Address Register | |
| __I uint32_t | Reserved1 [34] |
| __IO uint32_t | ISI_WPMR |
| (Isi Offset: 0xE4) Write Protection Mode Register | |
| __I uint32_t | ISI_WPSR |
| (Isi Offset: 0xE8) Write Protection Status Register | |
| __I uint32_t | Reserved2 [4] |
| __I uint32_t | ISI_VERSION |
| (Isi Offset: 0xFC) Version Register | |
Isi hardware registers.