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RTEMS 6.1
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RTEMS 6.1
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High resolution Timer (HRTIM) More...
#include <stm32h742xx.h>
Data Fields | |
| __IO uint32_t | MCR |
| __IO uint32_t | MISR |
| __IO uint32_t | MICR |
| __IO uint32_t | MDIER |
| __IO uint32_t | MCNTR |
| __IO uint32_t | MPER |
| __IO uint32_t | MREP |
| __IO uint32_t | MCMP1R |
| uint32_t | RESERVED0 |
| __IO uint32_t | MCMP2R |
| __IO uint32_t | MCMP3R |
| __IO uint32_t | MCMP4R |
| uint32_t | RESERVED1 [20] |
High resolution Timer (HRTIM)
| __IO uint32_t HRTIM_Master_TypeDef::MCMP1R |
HRTIM Master Timer compare 1 register, Address offset: 0x1C
| __IO uint32_t HRTIM_Master_TypeDef::MCMP2R |
HRTIM Master Timer compare 2 register, Address offset: 0x24
| __IO uint32_t HRTIM_Master_TypeDef::MCMP3R |
HRTIM Master Timer compare 3 register, Address offset: 0x28
| __IO uint32_t HRTIM_Master_TypeDef::MCMP4R |
HRTIM Master Timer compare 4 register, Address offset: 0x2C
| __IO uint32_t HRTIM_Master_TypeDef::MCNTR |
HRTIM Master Timer counter register, Address offset: 0x10
| __IO uint32_t HRTIM_Master_TypeDef::MCR |
HRTIM Master Timer control register, Address offset: 0x00
| __IO uint32_t HRTIM_Master_TypeDef::MDIER |
HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C
| __IO uint32_t HRTIM_Master_TypeDef::MICR |
HRTIM Master Timer interrupt clear register, Address offset: 0x08
| __IO uint32_t HRTIM_Master_TypeDef::MISR |
HRTIM Master Timer interrupt status register, Address offset: 0x04
| __IO uint32_t HRTIM_Master_TypeDef::MPER |
HRTIM Master Timer period register, Address offset: 0x14
| __IO uint32_t HRTIM_Master_TypeDef::MREP |
HRTIM Master Timer repetition register, Address offset: 0x18
| uint32_t HRTIM_Master_TypeDef::RESERVED0 |
Reserved, 0x20
| uint32_t HRTIM_Master_TypeDef::RESERVED1 |
Reserved, 0x30..0x7C
1.9.6