RTEMS 6.1
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Data Fields
HRTIM_Common_TypeDef Struct Reference
CMSIS_Device » Stm32h742xx | CMSIS_Device » Stm32h743xx | CMSIS_Device » Stm32h745xg | CMSIS_Device » Stm32h745xx | CMSIS_Device » Stm32h747xg | CMSIS_Device » Stm32h747xx | CMSIS_Device » Stm32h750xx | CMSIS_Device » Stm32h753xx | CMSIS_Device » Stm32h755xx | CMSIS_Device » Stm32h757xx

Data Fields

__IO uint32_t CR1
 
__IO uint32_t CR2
 
__IO uint32_t ISR
 
__IO uint32_t ICR
 
__IO uint32_t IER
 
__IO uint32_t OENR
 
__IO uint32_t ODISR
 
__IO uint32_t ODSR
 
__IO uint32_t BMCR
 
__IO uint32_t BMTRGR
 
__IO uint32_t BMCMPR
 
__IO uint32_t BMPER
 
__IO uint32_t EECR1
 
__IO uint32_t EECR2
 
__IO uint32_t EECR3
 
__IO uint32_t ADC1R
 
__IO uint32_t ADC2R
 
__IO uint32_t ADC3R
 
__IO uint32_t ADC4R
 
__IO uint32_t RESERVED0
 
__IO uint32_t FLTINR1
 
__IO uint32_t FLTINR2
 
__IO uint32_t BDMUPR
 
__IO uint32_t BDTAUPR
 
__IO uint32_t BDTBUPR
 
__IO uint32_t BDTCUPR
 
__IO uint32_t BDTDUPR
 
__IO uint32_t BDTEUPR
 
__IO uint32_t BDMADR
 

Field Documentation

◆ ADC1R

__IO uint32_t HRTIM_Common_TypeDef::ADC1R

HRTIM ADC Trigger 1 register, Address offset: 0x3C

◆ ADC2R

__IO uint32_t HRTIM_Common_TypeDef::ADC2R

HRTIM ADC Trigger 2 register, Address offset: 0x40

◆ ADC3R

__IO uint32_t HRTIM_Common_TypeDef::ADC3R

HRTIM ADC Trigger 3 register, Address offset: 0x44

◆ ADC4R

__IO uint32_t HRTIM_Common_TypeDef::ADC4R

HRTIM ADC Trigger 4 register, Address offset: 0x48

◆ BDMADR

__IO uint32_t HRTIM_Common_TypeDef::BDMADR

HRTIM Burst DMA Master Data register, Address offset: 0x70

◆ BDMUPR

__IO uint32_t HRTIM_Common_TypeDef::BDMUPR

HRTIM Burst DMA Master Timer update register, Address offset: 0x58

◆ BDTAUPR

__IO uint32_t HRTIM_Common_TypeDef::BDTAUPR

HRTIM Burst DMA Timerx update register, Address offset: 0x5C

◆ BDTBUPR

__IO uint32_t HRTIM_Common_TypeDef::BDTBUPR

HRTIM Burst DMA Timerx update register, Address offset: 0x60

◆ BDTCUPR

__IO uint32_t HRTIM_Common_TypeDef::BDTCUPR

HRTIM Burst DMA Timerx update register, Address offset: 0x64

◆ BDTDUPR

__IO uint32_t HRTIM_Common_TypeDef::BDTDUPR

HRTIM Burst DMA Timerx update register, Address offset: 0x68

◆ BDTEUPR

__IO uint32_t HRTIM_Common_TypeDef::BDTEUPR

HRTIM Burst DMA Timerx update register, Address offset: 0x6C

◆ BMCMPR

__IO uint32_t HRTIM_Common_TypeDef::BMCMPR

HRTIM Burst mode compare register, Address offset: 0x28

◆ BMCR

__IO uint32_t HRTIM_Common_TypeDef::BMCR

HRTIM Burst mode control register, Address offset: 0x20

◆ BMPER

__IO uint32_t HRTIM_Common_TypeDef::BMPER

HRTIM Burst mode period register, Address offset: 0x2C

◆ BMTRGR

__IO uint32_t HRTIM_Common_TypeDef::BMTRGR

HRTIM Burst mode trigger register, Address offset: 0x24

◆ CR1

__IO uint32_t HRTIM_Common_TypeDef::CR1

HRTIM control register1, Address offset: 0x00

◆ CR2

__IO uint32_t HRTIM_Common_TypeDef::CR2

HRTIM control register2, Address offset: 0x04

◆ EECR1

__IO uint32_t HRTIM_Common_TypeDef::EECR1

HRTIM Timer external event control register1, Address offset: 0x30

◆ EECR2

__IO uint32_t HRTIM_Common_TypeDef::EECR2

HRTIM Timer external event control register2, Address offset: 0x34

◆ EECR3

__IO uint32_t HRTIM_Common_TypeDef::EECR3

HRTIM Timer external event control register3, Address offset: 0x38

◆ FLTINR1

__IO uint32_t HRTIM_Common_TypeDef::FLTINR1

HRTIM Fault input register1, Address offset: 0x50

◆ FLTINR2

__IO uint32_t HRTIM_Common_TypeDef::FLTINR2

HRTIM Fault input register2, Address offset: 0x54

◆ ICR

__IO uint32_t HRTIM_Common_TypeDef::ICR

HRTIM interrupt clear register, Address offset: 0x0C

◆ IER

__IO uint32_t HRTIM_Common_TypeDef::IER

HRTIM interrupt enable register, Address offset: 0x10

◆ ISR

__IO uint32_t HRTIM_Common_TypeDef::ISR

HRTIM interrupt status register, Address offset: 0x08

◆ ODISR

__IO uint32_t HRTIM_Common_TypeDef::ODISR

HRTIM Output disable register, Address offset: 0x18

◆ ODSR

__IO uint32_t HRTIM_Common_TypeDef::ODSR

HRTIM Output disable status register, Address offset: 0x1C

◆ OENR

__IO uint32_t HRTIM_Common_TypeDef::OENR

HRTIM Output enable register, Address offset: 0x14

◆ RESERVED0

__IO uint32_t HRTIM_Common_TypeDef::RESERVED0

Reserved, Address offset: 0x4C

The documentation for this struct was generated from the following files:
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