GFXMMU_TypeDef Struct Reference

GFXMMU registers. More...

#include <stm32h7a3xx.h>

Data Fields
__IO uint32_t	CR
__IO uint32_t	SR
__IO uint32_t	FCR
__IO uint32_t	CCR
__IO uint32_t	DVR
uint32_t	RESERVED1 [3]
__IO uint32_t	B0CR
__IO uint32_t	B1CR
__IO uint32_t	B2CR
__IO uint32_t	B3CR
uint32_t	RESERVED2 [1012]
__IO uint32_t	LUT [2048]

Detailed Description

GFXMMU registers.

Field Documentation

B0CR

__IO uint32_t GFXMMU_TypeDef::B0CR

GFXMMU buffer 0 configuration register, Address offset: 0x20

B1CR

__IO uint32_t GFXMMU_TypeDef::B1CR

GFXMMU buffer 1 configuration register, Address offset: 0x24

B2CR

__IO uint32_t GFXMMU_TypeDef::B2CR

GFXMMU buffer 2 configuration register, Address offset: 0x28

B3CR

__IO uint32_t GFXMMU_TypeDef::B3CR

GFXMMU buffer 3 configuration register, Address offset: 0x2C

CCR

__IO uint32_t GFXMMU_TypeDef::CCR

GFXMMU Cache Control Register, Address offset: 0x0C

CR

__IO uint32_t GFXMMU_TypeDef::CR

GFXMMU configuration register, Address offset: 0x00

DVR

__IO uint32_t GFXMMU_TypeDef::DVR

GFXMMU default value register, Address offset: 0x10

FCR

__IO uint32_t GFXMMU_TypeDef::FCR

GFXMMU flag clear register, Address offset: 0x08

LUT

__IO uint32_t GFXMMU_TypeDef::LUT

GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1]

RESERVED1

uint32_t GFXMMU_TypeDef::RESERVED1

Reserved1, Address offset: 0x14 to 0x1C

RESERVED2

uint32_t GFXMMU_TypeDef::RESERVED2

Reserved2, Address offset: 0x30 to 0xFFC

SR

__IO uint32_t GFXMMU_TypeDef::SR

GFXMMU status register, Address offset: 0x04

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The documentation for this struct was generated from the following files:

• bsps/arm/stm32h7/include/stm32h7a3xx.h
• bsps/arm/stm32h7/include/stm32h7a3xxq.h
• bsps/arm/stm32h7/include/stm32h7b0xx.h
• bsps/arm/stm32h7/include/stm32h7b0xxq.h
• bsps/arm/stm32h7/include/stm32h7b3xx.h
• bsps/arm/stm32h7/include/stm32h7b3xxq.h