RTEMS 6.1
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Data Fields
FMC_Bank3_TypeDef Struct Reference
CMSIS_Device » Stm32h723xx | CMSIS_Device » Stm32h725xx | CMSIS_Device » Stm32h730xx | CMSIS_Device » Stm32h730xxQ | CMSIS_Device » Stm32h733xx | CMSIS_Device » Stm32h735xx | CMSIS_Device » Stm32h742xx | CMSIS_Device » Stm32h743xx | CMSIS_Device » Stm32h745xg | CMSIS_Device » Stm32h745xx | CMSIS_Device » Stm32h747xg | CMSIS_Device » Stm32h747xx | CMSIS_Device » Stm32h750xx | CMSIS_Device » Stm32h753xx | CMSIS_Device » Stm32h755xx | CMSIS_Device » Stm32h757xx | CMSIS_Device » Stm32h7a3xx | CMSIS_Device » Stm32h7a3xxq | CMSIS_Device » Stm32h7b0xx | CMSIS_Device » Stm32h7b0xxQ | CMSIS_Device » Stm32h7b3xx | CMSIS_Device » Stm32h7b3xxq » Peripheral_registers_structures

Flexible Memory Controller Bank3. More...

#include <stm32h723xx.h>

Data Fields

__IO uint32_t PCR
 
__IO uint32_t SR
 
__IO uint32_t PMEM
 
__IO uint32_t PATT
 
uint32_t RESERVED
 
__IO uint32_t ECCR
 

Detailed Description

Flexible Memory Controller Bank3.

Field Documentation

◆ ECCR

__IO uint32_t FMC_Bank3_TypeDef::ECCR

NAND Flash ECC result registers 3, Address offset: 0x94

◆ PATT

__IO uint32_t FMC_Bank3_TypeDef::PATT

NAND Flash Attribute memory space timing register 3, Address offset: 0x8C

◆ PCR

__IO uint32_t FMC_Bank3_TypeDef::PCR

NAND Flash control register 3, Address offset: 0x80

◆ PMEM

__IO uint32_t FMC_Bank3_TypeDef::PMEM

NAND Flash Common memory space timing register 3, Address offset: 0x88

◆ RESERVED

uint32_t FMC_Bank3_TypeDef::RESERVED

Reserved, 0x90

◆ SR

__IO uint32_t FMC_Bank3_TypeDef::SR

NAND Flash FIFO status and interrupt register 3, Address offset: 0x84

The documentation for this struct was generated from the following files:
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