RTEMS 6.1
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Data Fields
FLASH_TypeDef Struct Reference
CMSIS_Device » Stm32h723xx | CMSIS_Device » Stm32h725xx | CMSIS_Device » Stm32h730xx | CMSIS_Device » Stm32h730xxQ | CMSIS_Device » Stm32h733xx | CMSIS_Device » Stm32h735xx | CMSIS_Device » Stm32h742xx | CMSIS_Device » Stm32h743xx | CMSIS_Device » Stm32h745xg | CMSIS_Device » Stm32h745xx | CMSIS_Device » Stm32h747xg | CMSIS_Device » Stm32h747xx | CMSIS_Device » Stm32h750xx | CMSIS_Device » Stm32h753xx | CMSIS_Device » Stm32h755xx | CMSIS_Device » Stm32h757xx | CMSIS_Device » Stm32h7a3xx | CMSIS_Device » Stm32h7a3xxq | CMSIS_Device » Stm32h7b0xx | CMSIS_Device » Stm32h7b0xxQ | CMSIS_Device » Stm32h7b3xx | CMSIS_Device » Stm32h7b3xxq » Peripheral_registers_structures

FLASH Registers. More...

#include <stm32h723xx.h>

Data Fields

__IO uint32_t ACR
 
__IO uint32_t KEYR1
 
__IO uint32_t OPTKEYR
 
__IO uint32_t CR1
 
__IO uint32_t SR1
 
__IO uint32_t CCR1
 
__IO uint32_t OPTCR
 
__IO uint32_t OPTSR_CUR
 
__IO uint32_t OPTSR_PRG
 
__IO uint32_t OPTCCR
 
__IO uint32_t PRAR_CUR1
 
__IO uint32_t PRAR_PRG1
 
__IO uint32_t SCAR_CUR1
 
__IO uint32_t SCAR_PRG1
 
__IO uint32_t WPSN_CUR1
 
__IO uint32_t WPSN_PRG1
 
__IO uint32_t BOOT_CUR
 
__IO uint32_t BOOT_PRG
 
uint32_t RESERVED0 [2]
 
__IO uint32_t CRCCR1
 
__IO uint32_t CRCSADD1
 
__IO uint32_t CRCEADD1
 
__IO uint32_t CRCDATA
 
__IO uint32_t ECC_FA1
 
uint32_t RESERVED [3]
 
__IO uint32_t OPTSR2_CUR
 
__IO uint32_t OPTSR2_PRG
 
uint32_t RESERVED1 [40]
 
__IO uint32_t KEYR2
 
uint32_t RESERVED2
 
__IO uint32_t CR2
 
__IO uint32_t SR2
 
__IO uint32_t CCR2
 
uint32_t RESERVED3 [4]
 
__IO uint32_t PRAR_CUR2
 
__IO uint32_t PRAR_PRG2
 
__IO uint32_t SCAR_CUR2
 
__IO uint32_t SCAR_PRG2
 
__IO uint32_t WPSN_CUR2
 
__IO uint32_t WPSN_PRG2
 
uint32_t RESERVED4 [4]
 
__IO uint32_t CRCCR2
 
__IO uint32_t CRCSADD2
 
__IO uint32_t CRCEADD2
 
__IO uint32_t CRCDATA2
 
__IO uint32_t ECC_FA2
 
__IO uint32_t BOOT7_CUR
 
__IO uint32_t BOOT7_PRG
 
__IO uint32_t BOOT4_CUR
 
__IO uint32_t BOOT4_PRG
 
__IO uint32_t OTPBL_CUR
 
__IO uint32_t OTPBL_PRG
 

Detailed Description

FLASH Registers.

Field Documentation

◆ ACR

__IO uint32_t FLASH_TypeDef::ACR

FLASH access control register, Address offset: 0x00

◆ BOOT4_CUR

__IO uint32_t FLASH_TypeDef::BOOT4_CUR

Flash Current Boot Address for M4 Core Register, Address offset: 0x48

◆ BOOT4_PRG

__IO uint32_t FLASH_TypeDef::BOOT4_PRG

Flash Boot Address to Program for M4 Core Register, Address offset: 0x4C

◆ BOOT7_CUR

__IO uint32_t FLASH_TypeDef::BOOT7_CUR

Flash Current Boot Address for Pelican Core Register, Address offset: 0x40

◆ BOOT7_PRG

__IO uint32_t FLASH_TypeDef::BOOT7_PRG

Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44

◆ BOOT_CUR

__IO uint32_t FLASH_TypeDef::BOOT_CUR

Flash Current Boot Address for Pelican Core Register, Address offset: 0x40

◆ BOOT_PRG

__IO uint32_t FLASH_TypeDef::BOOT_PRG

Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44

◆ CCR1

__IO uint32_t FLASH_TypeDef::CCR1

Flash Control Register for bank1, Address offset: 0x14

◆ CCR2

__IO uint32_t FLASH_TypeDef::CCR2

Flash Status Register for bank2, Address offset: 0x114

◆ CR1

__IO uint32_t FLASH_TypeDef::CR1

Flash Control Register for bank1, Address offset: 0x0C

◆ CR2

__IO uint32_t FLASH_TypeDef::CR2

Flash Control Register for bank2, Address offset: 0x10C

◆ CRCCR1

__IO uint32_t FLASH_TypeDef::CRCCR1

Flash CRC Control register For Bank1 Register , Address offset: 0x50

◆ CRCCR2

__IO uint32_t FLASH_TypeDef::CRCCR2

Flash CRC Control register For Bank2 Register , Address offset: 0x150

◆ CRCDATA

__IO uint32_t FLASH_TypeDef::CRCDATA

Flash CRC Data Register for Bank1 , Address offset: 0x5C

◆ CRCDATA2

__IO uint32_t FLASH_TypeDef::CRCDATA2

Flash CRC Data Register for Bank2 , Address offset: 0x15C

◆ CRCEADD1

__IO uint32_t FLASH_TypeDef::CRCEADD1

Flash CRC End Address Register for Bank1 , Address offset: 0x58

◆ CRCEADD2

__IO uint32_t FLASH_TypeDef::CRCEADD2

Flash CRC End Address Register for Bank2 , Address offset: 0x158

◆ CRCSADD1

__IO uint32_t FLASH_TypeDef::CRCSADD1

Flash CRC Start Address Register for Bank1 , Address offset: 0x54

◆ CRCSADD2

__IO uint32_t FLASH_TypeDef::CRCSADD2

Flash CRC Start Address Register for Bank2 , Address offset: 0x154

◆ ECC_FA1

__IO uint32_t FLASH_TypeDef::ECC_FA1

Flash ECC Fail Address For Bank1 Register , Address offset: 0x60

◆ ECC_FA2

__IO uint32_t FLASH_TypeDef::ECC_FA2

Flash ECC Fail Address For Bank2 Register , Address offset: 0x160

◆ KEYR1

__IO uint32_t FLASH_TypeDef::KEYR1

Flash Key Register for bank1, Address offset: 0x04

◆ KEYR2

__IO uint32_t FLASH_TypeDef::KEYR2

Flash Key Register for bank2, Address offset: 0x104

◆ OPTCCR

__IO uint32_t FLASH_TypeDef::OPTCCR

Flash Option Clear Control Register, Address offset: 0x24

◆ OPTCR

__IO uint32_t FLASH_TypeDef::OPTCR

Flash Option Control Register, Address offset: 0x18

◆ OPTKEYR

__IO uint32_t FLASH_TypeDef::OPTKEYR

Flash Option Key Register, Address offset: 0x08

◆ OPTSR2_CUR

__IO uint32_t FLASH_TypeDef::OPTSR2_CUR

Flash Option Status Current Register 2, Address offset: 0x70

◆ OPTSR2_PRG

__IO uint32_t FLASH_TypeDef::OPTSR2_PRG

Flash Option Status to Program Register 2, Address offset: 0x74

◆ OPTSR_CUR

__IO uint32_t FLASH_TypeDef::OPTSR_CUR

Flash Option Status Current Register, Address offset: 0x1C

◆ OPTSR_PRG

__IO uint32_t FLASH_TypeDef::OPTSR_PRG

Flash Option Status to Program Register, Address offset: 0x20

◆ OTPBL_CUR

__IO uint32_t FLASH_TypeDef::OTPBL_CUR

Flash Current OTP Block Lock Register, Address offset: 0x68

◆ OTPBL_PRG

__IO uint32_t FLASH_TypeDef::OTPBL_PRG

Flash OTP Block Lock to Program Register, Address offset: 0x6C

◆ PRAR_CUR1

__IO uint32_t FLASH_TypeDef::PRAR_CUR1

Flash Current Protection Address Register for bank1, Address offset: 0x28

◆ PRAR_CUR2

__IO uint32_t FLASH_TypeDef::PRAR_CUR2

Flash Current Protection Address Register for bank2, Address offset: 0x128

◆ PRAR_PRG1

__IO uint32_t FLASH_TypeDef::PRAR_PRG1

Flash Protection Address to Program Register for bank1, Address offset: 0x2C

◆ PRAR_PRG2

__IO uint32_t FLASH_TypeDef::PRAR_PRG2

Flash Protection Address to Program Register for bank2, Address offset: 0x12C

◆ RESERVED

uint32_t FLASH_TypeDef::RESERVED

Reserved, 0x64 to 0x6C

Reserved, 0x64

◆ RESERVED0

uint32_t FLASH_TypeDef::RESERVED0

Reserved, 0x48 to 0x4C

◆ RESERVED1

uint32_t FLASH_TypeDef::RESERVED1

Reserved, 0x64 to 0x100

Reserved, 0x70 to 0x100

◆ RESERVED2

uint32_t FLASH_TypeDef::RESERVED2

Reserved, 0x108

◆ RESERVED3

uint32_t FLASH_TypeDef::RESERVED3

Reserved, 0x118 to 0x124

◆ RESERVED4

uint32_t FLASH_TypeDef::RESERVED4

Reserved, 0x140 to 0x14C

◆ SCAR_CUR1

__IO uint32_t FLASH_TypeDef::SCAR_CUR1

Flash Current Secure Address Register for bank1, Address offset: 0x30

◆ SCAR_CUR2

__IO uint32_t FLASH_TypeDef::SCAR_CUR2

Flash Current Secure Address Register for bank2, Address offset: 0x130

◆ SCAR_PRG1

__IO uint32_t FLASH_TypeDef::SCAR_PRG1

Flash Secure Address to Program Register for bank1, Address offset: 0x34

◆ SCAR_PRG2

__IO uint32_t FLASH_TypeDef::SCAR_PRG2

Flash Secure Address Register for bank2, Address offset: 0x134

◆ SR1

__IO uint32_t FLASH_TypeDef::SR1

Flash Status Register for bank1, Address offset: 0x10

◆ SR2

__IO uint32_t FLASH_TypeDef::SR2

Flash Status Register for bank2, Address offset: 0x110

◆ WPSN_CUR1

__IO uint32_t FLASH_TypeDef::WPSN_CUR1

Flash Current Write Protection Register on bank1, Address offset: 0x38

◆ WPSN_CUR2

__IO uint32_t FLASH_TypeDef::WPSN_CUR2

Flash Current Write Protection Register on bank2, Address offset: 0x138

◆ WPSN_PRG1

__IO uint32_t FLASH_TypeDef::WPSN_PRG1

Flash Write Protection to Program Register on bank1, Address offset: 0x3C

◆ WPSN_PRG2

__IO uint32_t FLASH_TypeDef::WPSN_PRG2

Flash Write Protection to Program Register on bank2, Address offset: 0x13C

The documentation for this struct was generated from the following files:
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