DTS. More...

#include <stm32h723xx.h>

Data Fields
__IO uint32_t	CFGR1

uint32_t	RESERVED0

__IO uint32_t	T0VALR1

uint32_t	RESERVED1

__IO uint32_t	RAMPVALR

__IO uint32_t	ITR1

uint32_t	RESERVED2

__IO uint32_t	DR

__IO uint32_t	SR

__IO uint32_t	ITENR

__IO uint32_t	ICIFR

__IO uint32_t	OR

Detailed Description

DTS.

Field Documentation

◆ CFGR1

__IO uint32_t DTS_TypeDef::CFGR1

DTS configuration register, Address offset: 0x00

◆ DR

__IO uint32_t DTS_TypeDef::DR

DTS data register, Address offset: 0x1C

◆ ICIFR

__IO uint32_t DTS_TypeDef::ICIFR

DTS Clear Interrupt flag register, Address offset: 0x28

◆ ITENR

__IO uint32_t DTS_TypeDef::ITENR

DTS Interrupt enable register, Address offset: 0x24

◆ ITR1

__IO uint32_t DTS_TypeDef::ITR1

DTS Interrupt threshold register, Address offset: 0x14

◆ OR

__IO uint32_t DTS_TypeDef::OR

DTS option register 1, Address offset: 0x2C

◆ RAMPVALR

__IO uint32_t DTS_TypeDef::RAMPVALR

DTS Ramp value register, Address offset: 0x10

◆ RESERVED0

uint32_t DTS_TypeDef::RESERVED0

Reserved, Address offset: 0x04

◆ RESERVED1

uint32_t DTS_TypeDef::RESERVED1

Reserved, Address offset: 0x0C

◆ RESERVED2

uint32_t DTS_TypeDef::RESERVED2

Reserved, Address offset: 0x18

◆ SR

__IO uint32_t DTS_TypeDef::SR

DTS status register Address offset: 0x20

◆ T0VALR1

__IO uint32_t DTS_TypeDef::T0VALR1

DTS T0 Value register, Address offset: 0x08

The documentation for this struct was generated from the following files:

bsps/arm/stm32h7/include/stm32h723xx.h
bsps/arm/stm32h7/include/stm32h725xx.h
bsps/arm/stm32h7/include/stm32h730xx.h
bsps/arm/stm32h7/include/stm32h730xxq.h
bsps/arm/stm32h7/include/stm32h733xx.h
bsps/arm/stm32h7/include/stm32h735xx.h
bsps/arm/stm32h7/include/stm32h7a3xx.h
bsps/arm/stm32h7/include/stm32h7a3xxq.h
bsps/arm/stm32h7/include/stm32h7b0xx.h
bsps/arm/stm32h7/include/stm32h7b0xxq.h
bsps/arm/stm32h7/include/stm32h7b3xx.h
bsps/arm/stm32h7/include/stm32h7b3xxq.h

Data Fields