DSI_TypeDef Struct Reference

DSI Controller. More...

#include <stm32h747xg.h>

Data Fields
__IO uint32_t	VR
__IO uint32_t	CR
__IO uint32_t	CCR
__IO uint32_t	LVCIDR
__IO uint32_t	LCOLCR
__IO uint32_t	LPCR
__IO uint32_t	LPMCR
uint32_t	RESERVED0 [4]
__IO uint32_t	PCR
__IO uint32_t	GVCIDR
__IO uint32_t	MCR
__IO uint32_t	VMCR
__IO uint32_t	VPCR
__IO uint32_t	VCCR
__IO uint32_t	VNPCR
__IO uint32_t	VHSACR
__IO uint32_t	VHBPCR
__IO uint32_t	VLCR
__IO uint32_t	VVSACR
__IO uint32_t	VVBPCR
__IO uint32_t	VVFPCR
__IO uint32_t	VVACR
__IO uint32_t	LCCR
__IO uint32_t	CMCR
__IO uint32_t	GHCR
__IO uint32_t	GPDR
__IO uint32_t	GPSR
__IO uint32_t	TCCR [6]
__IO uint32_t	TDCR
__IO uint32_t	CLCR
__IO uint32_t	CLTCR
__IO uint32_t	DLTCR
__IO uint32_t	PCTLR
__IO uint32_t	PCONFR
__IO uint32_t	PUCR
__IO uint32_t	PTTCR
__IO uint32_t	PSR
uint32_t	RESERVED1 [2]
__IO uint32_t	ISR [2]
__IO uint32_t	IER [2]
uint32_t	RESERVED2 [3]
__IO uint32_t	FIR [2]
uint32_t	RESERVED3 [8]
__IO uint32_t	VSCR
uint32_t	RESERVED4 [2]
__IO uint32_t	LCVCIDR
__IO uint32_t	LCCCR
uint32_t	RESERVED5
__IO uint32_t	LPMCCR
uint32_t	RESERVED6 [7]
__IO uint32_t	VMCCR
__IO uint32_t	VPCCR
__IO uint32_t	VCCCR
__IO uint32_t	VNPCCR
__IO uint32_t	VHSACCR
__IO uint32_t	VHBPCCR
__IO uint32_t	VLCCR
__IO uint32_t	VVSACCR
__IO uint32_t	VVBPCCR
__IO uint32_t	VVFPCCR
__IO uint32_t	VVACCR
uint32_t	RESERVED7 [11]
__IO uint32_t	TDCCR
uint32_t	RESERVED8 [155]
__IO uint32_t	WCFGR
__IO uint32_t	WCR
__IO uint32_t	WIER
__IO uint32_t	WISR
__IO uint32_t	WIFCR
uint32_t	RESERVED9
__IO uint32_t	WPCR [5]
uint32_t	RESERVED10
__IO uint32_t	WRPCR

Detailed Description

DSI Controller.

Field Documentation

CCR

__IO uint32_t DSI_TypeDef::CCR

DSI HOST Clock Control Register, Address offset: 0x08

CLCR

__IO uint32_t DSI_TypeDef::CLCR

DSI Host Clock Lane Configuration Register, Address offset: 0x94

CLTCR

__IO uint32_t DSI_TypeDef::CLTCR

DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98

CMCR

__IO uint32_t DSI_TypeDef::CMCR

DSI Host Command Mode Configuration Register, Address offset: 0x68

CR

__IO uint32_t DSI_TypeDef::CR

DSI Host Control Register, Address offset: 0x04

DLTCR

__IO uint32_t DSI_TypeDef::DLTCR

DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C

FIR

__IO uint32_t DSI_TypeDef::FIR

DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF

GHCR

__IO uint32_t DSI_TypeDef::GHCR

DSI Host Generic Header Configuration Register, Address offset: 0x6C

GPDR

__IO uint32_t DSI_TypeDef::GPDR

DSI Host Generic Payload Data Register, Address offset: 0x70

GPSR

__IO uint32_t DSI_TypeDef::GPSR

DSI Host Generic Packet Status Register, Address offset: 0x74

GVCIDR

__IO uint32_t DSI_TypeDef::GVCIDR

DSI Host Generic VCID Register, Address offset: 0x30

IER

__IO uint32_t DSI_TypeDef::IER

DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB

ISR

__IO uint32_t DSI_TypeDef::ISR

DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3

LCCCR

__IO uint32_t DSI_TypeDef::LCCCR

DSI Host LTDC Current Color Coding Register, Address offset: 0x110

LCCR

__IO uint32_t DSI_TypeDef::LCCR

DSI Host LTDC Command Configuration Register, Address offset: 0x64

LCOLCR

__IO uint32_t DSI_TypeDef::LCOLCR

DSI Host LTDC Color Coding Register, Address offset: 0x10

LCVCIDR

__IO uint32_t DSI_TypeDef::LCVCIDR

DSI Host LTDC Current VCID Register, Address offset: 0x10C

LPCR

__IO uint32_t DSI_TypeDef::LPCR

DSI Host LTDC Polarity Configuration Register, Address offset: 0x14

LPMCCR

__IO uint32_t DSI_TypeDef::LPMCCR

DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118

LPMCR

__IO uint32_t DSI_TypeDef::LPMCR

DSI Host Low-Power Mode Configuration Register, Address offset: 0x18

LVCIDR

__IO uint32_t DSI_TypeDef::LVCIDR

DSI Host LTDC VCID Register, Address offset: 0x0C

MCR

__IO uint32_t DSI_TypeDef::MCR

DSI Host Mode Configuration Register, Address offset: 0x34

PCONFR

__IO uint32_t DSI_TypeDef::PCONFR

DSI Host PHY Configuration Register, Address offset: 0xA4

PCR

__IO uint32_t DSI_TypeDef::PCR

DSI Host Protocol Configuration Register, Address offset: 0x2C

PCTLR

__IO uint32_t DSI_TypeDef::PCTLR

DSI Host PHY Control Register, Address offset: 0xA0

PSR

__IO uint32_t DSI_TypeDef::PSR

DSI Host PHY Status Register, Address offset: 0xB0

PTTCR

__IO uint32_t DSI_TypeDef::PTTCR

DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC

PUCR

__IO uint32_t DSI_TypeDef::PUCR

DSI Host PHY ULPS Control Register, Address offset: 0xA8

RESERVED0

uint32_t DSI_TypeDef::RESERVED0

Reserved, 0x1C - 0x2B

RESERVED1

uint32_t DSI_TypeDef::RESERVED1

Reserved, 0xB4 - 0xBB

RESERVED10

uint32_t DSI_TypeDef::RESERVED10

Reserved, 0x42C

RESERVED2

uint32_t DSI_TypeDef::RESERVED2

Reserved, 0xD0 - 0xD7

RESERVED3

uint32_t DSI_TypeDef::RESERVED3

Reserved, 0xE0 - 0xFF

RESERVED4

uint32_t DSI_TypeDef::RESERVED4

Reserved, 0x104 - 0x10B

RESERVED5

uint32_t DSI_TypeDef::RESERVED5

Reserved, 0x114

RESERVED6

uint32_t DSI_TypeDef::RESERVED6

Reserved, 0x11C - 0x137

RESERVED7

uint32_t DSI_TypeDef::RESERVED7

Reserved, 0x164 - 0x18F

RESERVED8

uint32_t DSI_TypeDef::RESERVED8

Reserved, 0x194 - 0x3FF

RESERVED9

uint32_t DSI_TypeDef::RESERVED9

Reserved, 0x414

TCCR

__IO uint32_t DSI_TypeDef::TCCR

DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F

TDCCR

__IO uint32_t DSI_TypeDef::TDCCR

DSI Host 3D Current Configuration Register, Address offset: 0x190

TDCR

__IO uint32_t DSI_TypeDef::TDCR

DSI Host 3D Configuration Register, Address offset: 0x90

VCCCR

__IO uint32_t DSI_TypeDef::VCCCR

DSI Host Video Chunks Current Configuration Register, Address offset: 0x140

VCCR

__IO uint32_t DSI_TypeDef::VCCR

DSI Host Video Chunks Configuration Register, Address offset: 0x40

VHBPCCR

__IO uint32_t DSI_TypeDef::VHBPCCR

DSI Host Video HBP Current Configuration Register, Address offset: 0x14C

VHBPCR

__IO uint32_t DSI_TypeDef::VHBPCR

DSI Host Video HBP Configuration Register, Address offset: 0x4C

VHSACCR

__IO uint32_t DSI_TypeDef::VHSACCR

DSI Host Video HSA Current Configuration Register, Address offset: 0x148

VHSACR

__IO uint32_t DSI_TypeDef::VHSACR

DSI Host Video HSA Configuration Register, Address offset: 0x48

VLCCR

__IO uint32_t DSI_TypeDef::VLCCR

DSI Host Video Line Current Configuration Register, Address offset: 0x150

VLCR

__IO uint32_t DSI_TypeDef::VLCR

DSI Host Video Line Configuration Register, Address offset: 0x50

VMCCR

__IO uint32_t DSI_TypeDef::VMCCR

DSI Host Video Mode Current Configuration Register, Address offset: 0x138

VMCR

__IO uint32_t DSI_TypeDef::VMCR

DSI Host Video Mode Configuration Register, Address offset: 0x38

VNPCCR

__IO uint32_t DSI_TypeDef::VNPCCR

DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144

VNPCR

__IO uint32_t DSI_TypeDef::VNPCR

DSI Host Video Null Packet Configuration Register, Address offset: 0x44

VPCCR

__IO uint32_t DSI_TypeDef::VPCCR

DSI Host Video Packet Current Configuration Register, Address offset: 0x13C

VPCR

__IO uint32_t DSI_TypeDef::VPCR

DSI Host Video Packet Configuration Register, Address offset: 0x3C

VR

__IO uint32_t DSI_TypeDef::VR

DSI Host Version Register, Address offset: 0x00

VSCR

__IO uint32_t DSI_TypeDef::VSCR

DSI Host Video Shadow Control Register, Address offset: 0x100

VVACCR

__IO uint32_t DSI_TypeDef::VVACCR

DSI Host Video VA Current Configuration Register, Address offset: 0x160

VVACR

__IO uint32_t DSI_TypeDef::VVACR

DSI Host Video VA Configuration Register, Address offset: 0x60

VVBPCCR

__IO uint32_t DSI_TypeDef::VVBPCCR

DSI Host Video VBP Current Configuration Register, Address offset: 0x158

VVBPCR

__IO uint32_t DSI_TypeDef::VVBPCR

DSI Host Video VBP Configuration Register, Address offset: 0x58

VVFPCCR

__IO uint32_t DSI_TypeDef::VVFPCCR

DSI Host Video VFP Current Configuration Register, Address offset: 0x15C

VVFPCR

__IO uint32_t DSI_TypeDef::VVFPCR

DSI Host Video VFP Configuration Register, Address offset: 0x5C

VVSACCR

__IO uint32_t DSI_TypeDef::VVSACCR

DSI Host Video VSA Current Configuration Register, Address offset: 0x154

VVSACR

__IO uint32_t DSI_TypeDef::VVSACR

DSI Host Video VSA Configuration Register, Address offset: 0x54

WCFGR

__IO uint32_t DSI_TypeDef::WCFGR

DSI Wrapper Configuration Register, Address offset: 0x400

WCR

__IO uint32_t DSI_TypeDef::WCR

DSI Wrapper Control Register, Address offset: 0x404

WIER

__IO uint32_t DSI_TypeDef::WIER

DSI Wrapper Interrupt Enable Register, Address offset: 0x408

WIFCR

__IO uint32_t DSI_TypeDef::WIFCR

DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410

WISR

__IO uint32_t DSI_TypeDef::WISR

DSI Wrapper Interrupt and Status Register, Address offset: 0x40C

WPCR

__IO uint32_t DSI_TypeDef::WPCR

DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B

WRPCR

__IO uint32_t DSI_TypeDef::WRPCR

DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430

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The documentation for this struct was generated from the following files:

• bsps/arm/stm32h7/include/stm32h747xg.h
• bsps/arm/stm32h7/include/stm32h747xx.h
• bsps/arm/stm32h7/include/stm32h757xx.h