RTEMS 6.1
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Data Fields
DMA2D_TypeDef Struct Reference
CMSIS_Device » Stm32h723xx | CMSIS_Device » Stm32h725xx | CMSIS_Device » Stm32h730xx | CMSIS_Device » Stm32h730xxQ | CMSIS_Device » Stm32h733xx | CMSIS_Device » Stm32h735xx | CMSIS_Device » Stm32h742xx | CMSIS_Device » Stm32h743xx | CMSIS_Device » Stm32h745xg | CMSIS_Device » Stm32h745xx | CMSIS_Device » Stm32h747xg | CMSIS_Device » Stm32h747xx | CMSIS_Device » Stm32h750xx | CMSIS_Device » Stm32h753xx | CMSIS_Device » Stm32h755xx | CMSIS_Device » Stm32h757xx | CMSIS_Device » Stm32h7a3xx | CMSIS_Device » Stm32h7a3xxq | CMSIS_Device » Stm32h7b0xx | CMSIS_Device » Stm32h7b0xxQ | CMSIS_Device » Stm32h7b3xx | CMSIS_Device » Stm32h7b3xxq » Peripheral_registers_structures

DMA2D Controller. More...

#include <stm32h723xx.h>

Data Fields

__IO uint32_t CR
 
__IO uint32_t ISR
 
__IO uint32_t IFCR
 
__IO uint32_t FGMAR
 
__IO uint32_t FGOR
 
__IO uint32_t BGMAR
 
__IO uint32_t BGOR
 
__IO uint32_t FGPFCCR
 
__IO uint32_t FGCOLR
 
__IO uint32_t BGPFCCR
 
__IO uint32_t BGCOLR
 
__IO uint32_t FGCMAR
 
__IO uint32_t BGCMAR
 
__IO uint32_t OPFCCR
 
__IO uint32_t OCOLR
 
__IO uint32_t OMAR
 
__IO uint32_t OOR
 
__IO uint32_t NLR
 
__IO uint32_t LWR
 
__IO uint32_t AMTCR
 
uint32_t RESERVED [236]
 
__IO uint32_t FGCLUT [256]
 
__IO uint32_t BGCLUT [256]
 

Detailed Description

DMA2D Controller.

Field Documentation

◆ AMTCR

__IO uint32_t DMA2D_TypeDef::AMTCR

DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C

◆ BGCLUT

__IO uint32_t DMA2D_TypeDef::BGCLUT

DMA2D Background CLUT, Address offset:800-BFF

◆ BGCMAR

__IO uint32_t DMA2D_TypeDef::BGCMAR

DMA2D Background CLUT Memory Address Register, Address offset: 0x30

◆ BGCOLR

__IO uint32_t DMA2D_TypeDef::BGCOLR

DMA2D Background Color Register, Address offset: 0x28

◆ BGMAR

__IO uint32_t DMA2D_TypeDef::BGMAR

DMA2D Background Memory Address Register, Address offset: 0x14

◆ BGOR

__IO uint32_t DMA2D_TypeDef::BGOR

DMA2D Background Offset Register, Address offset: 0x18

◆ BGPFCCR

__IO uint32_t DMA2D_TypeDef::BGPFCCR

DMA2D Background PFC Control Register, Address offset: 0x24

◆ CR

__IO uint32_t DMA2D_TypeDef::CR

DMA2D Control Register, Address offset: 0x00

◆ FGCLUT

__IO uint32_t DMA2D_TypeDef::FGCLUT

DMA2D Foreground CLUT, Address offset:400-7FF

◆ FGCMAR

__IO uint32_t DMA2D_TypeDef::FGCMAR

DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C

◆ FGCOLR

__IO uint32_t DMA2D_TypeDef::FGCOLR

DMA2D Foreground Color Register, Address offset: 0x20

◆ FGMAR

__IO uint32_t DMA2D_TypeDef::FGMAR

DMA2D Foreground Memory Address Register, Address offset: 0x0C

◆ FGOR

__IO uint32_t DMA2D_TypeDef::FGOR

DMA2D Foreground Offset Register, Address offset: 0x10

◆ FGPFCCR

__IO uint32_t DMA2D_TypeDef::FGPFCCR

DMA2D Foreground PFC Control Register, Address offset: 0x1C

◆ IFCR

__IO uint32_t DMA2D_TypeDef::IFCR

DMA2D Interrupt Flag Clear Register, Address offset: 0x08

◆ ISR

__IO uint32_t DMA2D_TypeDef::ISR

DMA2D Interrupt Status Register, Address offset: 0x04

◆ LWR

__IO uint32_t DMA2D_TypeDef::LWR

DMA2D Line Watermark Register, Address offset: 0x48

◆ NLR

__IO uint32_t DMA2D_TypeDef::NLR

DMA2D Number of Line Register, Address offset: 0x44

◆ OCOLR

__IO uint32_t DMA2D_TypeDef::OCOLR

DMA2D Output Color Register, Address offset: 0x38

◆ OMAR

__IO uint32_t DMA2D_TypeDef::OMAR

DMA2D Output Memory Address Register, Address offset: 0x3C

◆ OOR

__IO uint32_t DMA2D_TypeDef::OOR

DMA2D Output Offset Register, Address offset: 0x40

◆ OPFCCR

__IO uint32_t DMA2D_TypeDef::OPFCCR

DMA2D Output PFC Control Register, Address offset: 0x34

◆ RESERVED

uint32_t DMA2D_TypeDef::RESERVED

Reserved, 0x50-0x3FF

The documentation for this struct was generated from the following files:
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